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1 - 50 of about 601 for 8b10b |
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First line: 5 to 32 decoder circuit Encoder/Decoder notes 8B10B datasheet 5.1 decoder 8B10B Encoder/Decoder MegaCore Function October 2005, Version 1.6.0 Release Notes These release notes 8B10B Encoder/Decoder MegaCore® function contain following information: Abstract: .. Altera Corporation 1. RN-8B10B-1.0 Preliminary. Release Notes. 8B10B Encoder/Decoder MegaCore Function. These release notes for the 8B10B Encoder/Decoder MegaCore ® function contain the following .. Tags: datasheet 5.1 decoder 8B10B Encoder/Decoder notes 5 to 32 decoder circuit datasheet abstract.. |
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First line: history of encoder decoder configuration 8B10B 8B10B Encoder/Decoder MegaCore Function April 2007, MegaCore Function Version This document addresses known errata documentation issues 8B10B Encoder/Decoder MegaCore Function version 6.1. Errata functional defects errors, which cause 8B10B Encoder/Deco Abstract: .. 8B10B Encoder/Decoder MegaCore Function. This document addresses known errata and documentation issues for the 8B10B Encoder/Decoder MegaCore Function version 6.1. Errata are functional .. Tags: decoder configuration history of encoder Encoder/Decoder 8b10b 8B10B Encoder Decoder MegaCore Function v6 1 Errata Sheet |
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First line: 8B10B Encoder/Decoder MegaCore Function April 2007, MegaCore Function Version This document addresses known errata documentation issues 8B10B Encoder/Decoder MegaCore Function version 7.0. Errata functional defects errors, which cause 8B10B Encoder/Decoder MegaCore Function deviate from published sp Abstract: .. 8B10B Encoder/Decoder MegaCore Function. This document addresses known errata and documentation issues for the 8B10B Encoder/Decoder MegaCore Function version 7.0. Errata are functional .. Tags: Encoder/Decoder* encoder / decoder Altera 8b10b 8b10b decoder 8B10B 8B10B Encoder Decoder MegaCore Function v7 0 Errata Sheet |
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First line: 8B10B Encoder/Decoder MegaCore Function April 2006, Version 1.6.1 Release Notes These release notes 8B10B Encoder/Decoder MegaCore® function v1.6.1 contain following information: Abstract: .. 8B10B Encoder/Decoder MegaCore Function. These release notes for the 8B10B Encoder/Decoder MegaCore ® function v1.6.1 contain the following information: â– System Requirements â– New Features .. Tags: datasheet abstract.. |
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First line: Altera 8b10b 8B10B Encoder/Decoder MegaCore Function April 2006, MegaCore Function Version 1.6.1 This document addresses known errata documentation issues Altera® 8B10B Encoder/Decoder MegaCore® function version 1.6.1. Errata functional defects errors, which cause 8B10B Encoder/Decoder MegaC Abstract: .. 8B10B Encoder/Decoder MegaCore Function. This document addresses known errata and documentation issues for the Altera ® 8B10B Encoder/Decoder MegaCore ® function version 1.6.1. Errata are .. Tags: Encoder/Decoder Altera 8b10b Altera 8B10B Encoder Decoder MegaCore Function v1 6 1 Errata Sheet |
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First line: 8B10B Encoder/Decoder MegaCore Function 2007, MegaCore Function Version This document addresses known errata documentation issues 8B10B Encoder/Decoder MegaCore Function version 7.1. Errata functional defects errors, which cause 8B10B Encoder/Decoder MegaCore Function deviate from published specific Abstract: .. 8B10B Encoder/Decoder MegaCore Function. This document addresses known errata and documentation issues for the 8B10B Encoder/Decoder MegaCore Function version 7.1. Errata are functional .. Tags: Encoder/Decoder datasheet abstract.. |
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First line: 8B10B Encoder/Decoder MegaCore Function February 2006, MegaCore Function Version 1.6.0 This document addresses known errata documentation issues Altera® 8B10B Encoder/Decoder MegaCore® function version 1.6.0. Errata functional defects errors, which cause 8B10B Encoder/Decoder MegaCore functi Abstract: .. Altera Corporation 1. ES-8B10B-1.2 Preliminary. Errata Sheet. 8B10B Encoder/Decoder MegaCore Function. This document addresses known errata and documentation issues for the Altera ® 8B10B Encoder .. Tags: encoder / decoder 8B10B* 8B10B Encoder Decoder MegaCore Function v1 6 0 Errata Sheet |
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First line: 8B10B Encoder/Decoder MegaCore Function 2007, Version Release Notes These release notes 8B10B Encoder/Decoder MegaCore® function v7.1 contain following information: Abstract: .. 8B10B Encoder/Decoder MegaCore Function. These release notes for the 8B10B Encoder/Decoder MegaCore ® function v7.1 contain the following information: â– New Features & Enhancements â– Errata .. Tags: datasheet abstract.. |
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First line: 8b10b Macro Gigabit Ethernet 8b10b Function Operation Transmit Receive Function Disparity Illegal Code Error Checking Connects directly industry-standard Gigabit Ethernet Transceiver devices. Supports either single dual channel transceiver single device. Abstract: .. 8b10b Macro Product Summary. • Gigabit Ethernet 8b10b Function. 125 MHz Operation. Transmit and Receive Function. Disparity and Illegal Code Error Checking. Connects directly to industry-standard .. Tags: 8B10B MHz 8B10B data sheet 8B10B datasheet abstract.. |
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First line: 8B10B Encoder/Decoder MegaCore Function December 2006, Version Release Notes Abstract: .. 8B10B Encoder/Decoder MegaCore Function. Introduction These release notes for the 8B10B Encoder/Decoder MegaCore ® function v6.1 contain the following information: â– New Features & Enhancements .. Tags: datasheet abstract.. |
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First line: 8B10B Encoder/Decoder MegaCore Function Release Notes Abstract: .. 8B10B Encoder/Decoder MegaCore Function. Introduction These release notes for the 8B10B Encoder/Decoder MegaCore ® function v7.0 contain the following information: â– New Features & Enhancements .. Tags: datasheet abstract.. |
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First line: Velio Communications 3.125 Gbps Eight-Lane CMOS SerDes (Serializer Deserializer) Abstract: .. Mux 8b10b FIFO TX ASIC I/F Mux 8b10b FIFO TX ASIC I/F. Mux 8b10b FIFO TX ASIC I/F Mux 8b10b FIFO TX ASIC I/F. Clock Multiplier. Mux 8b10b FIFO TX ASIC I/F Mux 8b10b FIFO TX ASIC I/F. Mux 8b10b FIFO TX ASIC I .. Tags: Velio Communications Lanes* 8B10B in serial communication 8B10B asic 8B10B datasheet abstract.. |
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First line: 8B10B Encoder/Decoder MegaCore Function User Guide Software Version: Document Date: November 2009 Abstract: .. 101 Innovation Drive San Jose, CA 95134 www.altera.com. 8B10B Encoder/Decoder MegaCore. Function User Guide. Software Version: 9.1. Document Date: November 2009. Copyright © 2009 Altera Corporation .. Tags: kerr EP3C80F780C6 EP2S30F484C3 encoder / decoder Altera 8b10b 8B10B MHz 8B10B in serial communication 8b10b decoder 8B10B datasheet abstract.. |
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First line: 3.125 Gbps Four-Lane CMOS SerDes (Serializer Deserializer) Abstract: .. Mux 8b10b FIFO TX ASIC I/F Mux 8b10b FIFO TX ASIC I/F. Mux 8b10b FIFO TX ASIC I/F Mux 8b10b TX ASIC. I/F. Clock Multiplier Termination. Reference. CDR CDR CDR. Demux 10b8b 10b8b FIFO. CDR. Demux 10b8b 10b8b FIFO. CDR. RX .. Tags: Velio Communications 8B10B in serial communication 8B10B asic 8B10B datasheet abstract.. |
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First line: Gigabit Ethernet XGXS Intellectual Property Core Gigabit ethernet eXtender Sublayer (XGXS) Intellectual Property (IP) Core enables creation system solutions Gigabit Ethernet applications defined IEEE 802.3ae. This Core targets programmable array section ORCA® ORT82G5 FPSC provides bridging funct Abstract: .. Each XAUI interface is comprised of 4 self-timed 8b10b encoded serial lanes, each operating at 3.125 Gbits/s. The IP core from Lattice Semiconductor is provided with all implementation scripts .. Tags: XGXS xaui 8B10B MHz 8b10b 10Gb Ethernet XGXS Core ORT82G5 |
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First line: 8b10b Encoder/Decoder MegaCore Function (ED8B10B) July 2001; ver. 1.01 Data Sheet Encoders decoders used physical layer coding Gigabit Ethernet, Fibre Channel, other applications. 8b/10b encoder takes byte inputs, generates direct current (DC) balanced stream (equal number with maximum length Some i Abstract: .. Altera Corporation 1. 8b10b Encoder/Decoder MegaCore Function ED8B10B July 2001; ver. 1.01 Data Sheet. A-DS-IPED8B10B-1.01. Introduction Encoders and decoders are used for physical layer .. Tags: Altera 8b10b 8B10B MHz 8b10b 8 bit data encoder ED8B10B |
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First line: 8b10b Encoder/Decoder MegaCore Function (ED8B10B) November 2001; ver. 1.02 Data Sheet Encoders decoders used physical layer coding Gigabit Ethernet, Fibre Channel, other applications. 8b/10b encoder takes byte inputs, generates direct current (DC) balanced stream (equal number with maximum length So Abstract: .. Altera Corporation 1. 8b10b Encoder/Decoder MegaCore Function ED8B10B November 2001; ver. 1.02 Data Sheet. A-DS-IPED8B10B-1.02. Introduction Encoders and decoders are used for physical .. Tags: Altera 8b10b 8B10B MHz 8b10b decoder 8B10B 8 bit data encoder ED8B10B |
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First line: TC260 SD10 1.6/3.2Gb/s Dual Mode SerDes Macros TC260 SD10 macros enable building high speed interfaces while consuming limited number pins between integrated circuits (ICs) implemented standard cell embedded array Toshiba's TC260 technology. More specifically, SD10 dual mode serial `SerDes' interfac Abstract: .. The transmitter accepts a 10-bit 10-bit wide 8b10b encoded data on its 10 parallel inputs and serial-izes this data to a 1-bit wide 3.2Gb/s NRZ signal. The transmitter driver outputs this signal as a .. Tags: 8B10B TC260 |
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First line: 8b/10b scrambler PM5397 ARROW-2xGE Channel Gigabit Ethernet SONET Mapping Device Abstract: .. Rx Protect 2.488 Mbps or 4 x 622 Mbps SONET Scrambled or 4 x 622 Mbps / 8B10B Encoded. Rx Working 2.488 Mbps or 4 x 622 Mbps SONET Scrambled or 4 x 622 Mbps / 8B10B Encoded. Tx Protect 2.488 Mbps or 4 x 622 Mbps .. Tags: 8b/10b scrambler gigabit ethernet over sdh ethernet over sdh 8B10B MHz 8b10b PM5397 |
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First line: PM5397 ARROW-2xGE Channel Gigabit Ethernet SONET Mapping Device Abstract: .. Rx Protect 2.488 Mbps or 4 x 622 Mbps SONET Scrambled or 4 x 622 Mbps / 8B10B Encoded. Rx Working 2.488 Mbps or 4 x 622 Mbps SONET Scrambled or 4 x 622 Mbps / 8B10B Encoded. Tx Protect 2.488 Mbps or 4 x 622 Mbps .. Tags: gigabit ethernet over sdh ethernet over sdh 8B10B MHz 8B10B PM5397 |
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First line: LatticeECP2M PRBS SERDES Demo User's Guide June 2010 Technical Note TN1153 This demo illustrates SERDES/PCS abilities LatticeECP2MTM FPGA family. does this embedding simple pseudo-random pattern into 8b10b-encoded payload, then looping back payload, checking correctness. this demo, user will need: L Abstract: .. It does this by embedding a simple pseudo-random pattern into an 8b10b-encoded PCS payload, then looping back the payload, and checking it for correctness. For this demo, the user will need: .. Tags: TN1153 |
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First line: LatticeECP2M PRBS SERDES Demo User's Guide August 2009 Technical Note TN1153 This demo illustrates SERDES/PCS abilities LatticeECP2MTM FPGA family. does this embedding simple pseudo-random pattern into 8b10b-encoded payload, then looping back payload, checking correctness. this demo, user will need: Abstract: .. It does this by embedding a simple pseudo-random pattern into an 8b10b-encoded PCS payload, then looping back the payload, and checking it for correctness. For this demo, the user will need: .. Tags: verilog code 16 bit LFSR in PRBS verilog code 16 bit LFSR prbs using lfsr prbs pattern generator M25P64 8b10b 8b/10b-Serializer Coding Example TN1153 |
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First line: Stratix FPGA October 2009 ES-STXGX-1.7 This document addresses transceiver-related known errata Stratix FPGA family production devices. more information Stratix device errata, refer "Stratix Family Issues" section Stratix FPGA Family Errata Sheet. Abstract: .. 8B10B Decoder Serializer. J. Page 2 Receiver Phase Compensation FIFO. Stratix GX FPGA © October 2009 Altera Corporation. From Figure 1, the recovered clock rx_clkout[0] is fed to both the read and .. Tags: datasheet abstract.. |
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First line: IC link MC92610 QUAD MC92610 Quad high-speed, full-duplex, serializer/deserializer (SERDES) data interface that used transmit data between chips across board, through backplane, through cabling. Four transceivers XMIT_x_[7:0] XMIT_x_K XMIT_x_IDLE_B XMIT_x_CLK XCVR_x_DISABLE XCVR_x_RSLE RECV_x_[7:0] Abstract: .. 8B10B Decoder. 8B10B Decoder Transmit Interface Unit. RECV_x_CLK. RECV_x_[7:0] RECV_x_K RECV_x_9 RECV_x_IDLE. RECV_x_ERR. XMIT_x_[7:0] XMIT_x_K XMIT_x_IDLE_B. XCVR_x_DISABLE XCVR_x_RSLE .. Tags: IC link 8b10b MC92610 |
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First line: Fact Sheet MC92602FS/D Rev. 3/2003 Quad 1.25 Gbaud Reduced Interface SERDES High-density board applications chip-to-chip intra system communications utilizing Ethernet protocol Blade applications with high number Ethernet ports High-speed data transfer applications high-bandwidth backplane chassis-t Abstract: .. 8B10B Decoder. CLK GEN. Re c e. iv e r. System Configuration Unit. System PLL. RECV_x_CLK. XMIT_x _[3:0 .. Tags: 8B10B MC92602FS |
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First line: PM5317 SPECTRA-9953 SONET/SDH Payload Extractor/Aligner 9953 Mbit/s Abstract: .. Provides a 16-bit 16-bit 622 Mbit/s 8B10B encoded 777.7 MHz ADD and DROP serial TelecomBus interface for grooming a single STS-192 STS-192 /STM-64 STM-64 stream. Provides four 4-bit 622 Mbit/s 8B10B encoded 777 .. Tags: stm-16 Payload Processor spectra CRSU-4X2488 8B10B MHz 8b10b PM5317 |
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First line: MC92610 WarpLinkTM Quad SERDES Transceiver WarpLinkTM Quad high-speed, full-duplex, serializer/deserializer (SERDES) data interface that used transmit data between chips across board, through backplane, through cabling. Four transceivers transmit receive coded data rate gigabit second (Gbps) through Abstract: .. 8B10B Decoder. Transmitter Receiver. JTAG BIST. System PLL. Typical for each of 4 channels n=A, B .. Tags: 8B10B MC92610 |
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First line: giga Ethernet PHY RGMII Dual Gigabit Ethernet SerDes Transceiver MC92604 MC92604 Dual Gigabit Ethernet transceiver 1.25 giga-baud, full-duplex, interface device that used transmit data between chips across board, through backplane, through cabling, well interface GBIC/SFP modules. designed with inte Abstract: .. 8B10B Decoder. XMIT_x_ENABLE XMIT_x_DATA [7:0] XMIT_x_K/ERR. XMIT_x_CLK. RESET. CONFIG_INPUTS. MD_DATA. MD_CLK. BIST. Two Transceivers x = A & B. MD_ADR [4:2] MD_ENABLE. RECV_x_DATA [7:0] RECV_x_K .. Tags: giga Ethernet PHY RGMII MC92604 |
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First line: 3.125 Gbaud SERDES Transceiver MC92610 QUAD MC92610 Quad high-speed, full-duplex, serializer/deserializer (SERDES) data interface that used transmit data between chips across board, through backplane, through cabling. Four transceivers transmit receive coded data rate gigabit second (Gbps) through e Abstract: .. 8B10B Decoder. 8B10B Decoder Transmit Interface Unit. RECV_x_CLK. RECV_x_[7:0] RECV_x_K RECV_x_9 RECV_x_IDLE. RECV_x_ERR. XMIT_x_[7:0] XMIT_x_K XMIT_x_IDLE_B. XCVR_x_DISABLE XCVR_x_RSLE .. Tags: MC92610 |
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First line: MC92600 Quad Gigabit Ethernet SerDes Transceiver MC92603 MC92603 Quad Gigabit Ethernet transceiver 1.25 giga-baud, full-duplex, interface device that used transmit data between chips across board, through backplane, through cabling, well interface GBIC/SFP modules. designed with intent meet requirem Abstract: .. 8B10B Decoder. XMIT_x_ENABLE XMIT_x_DATA [7:0] XMIT_x_K/ERR. XMIT_x_CLK. RESET. CONFIG_INPUTS. MD_DATA. MD_CLK. BIST. Four Transceivers x = A, B, C, D. MD_ADR [4:2] MD_ENABLE. RECV_x_DATA [7:0] RECV_x_K .. Tags: MC92600 MPC8560 MPC8540 |
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First line: PM5317 SPECTRA-9953 SONET/SDH Payload Extractor/Aligner 9953 Mbit/s Abstract: .. Provides a 16-bit 16-bit 622 Mbit/s 8B10B. encoded 777.7 MHz ADD and DROP serial TelecomBus interface for grooming a single STS-192 STS-192 /STM-64 STM-64 stream. Provides four 4-bit 622 Mbit/s 8B10B. encoded 777 .. Tags: stm-16 Payload Processor 8B10B MHz PM5317 |
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First line: PM7390 S/UNI®-MACH48 Provides standard five signal IEEE 1149.1 JTAG test port boundary scan board test purposes. Provides generic 16-bit microprocessor interface configuration, control, status monitoring. power CMOS device with compatible digital inputs CMOS/TTL compatible digital outputs. Ultra Abstract: .. Tx Timeslot Interchange & 8B10B Encoder. Tx LVDS Interface. Tx Timeslot Interchange. Tx TelecomBus System Interface. Rx Timeslot Interchange & 8B10B Decoder. Rx LVDS Interface. Rx TelecomBus System .. Tags: STM-1 Physical interface PHY POS-PHY pmc 8B10B MHz 8b10b PM7390 |
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First line: MC92600FACT/D Rev. 3/2003 Quad 1.25 Gbaud SERDES Transceiver Abstract: .. 8B10B Decoder. CLK GEN. Receiver. System Configuration Unit. System PLL. TECHNICAL .. Tags: PBGA 23X23 MC92600FACT |
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First line: 8B10B LMH0341, LMH0041, LMH0071, LMH0051 DVB-ASI Deserializer with Loopthrough LVDS Interface LMH0341, LMH0041, LMH0071, LMH0051 DVB-ASI Deserializer with Loopthrough LVDS Interface Abstract: .. ternal framer and 8b10b decoder is engaged such that the data appearing on RX0-RX3 will represent a nibble of the de-coded 8b10b data. RX4 is an Idle character detect and can be used as an enable to .. Tags: LMH0041 8b10b LMH0341 LMH0041 LMH0071 LMH0051 |
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First line: Advanced Communications ACS406CS E1/T1 Fiber Abstract: .. 8B10B CODER. TX CONTROL PING PONG ENGINE. TX FIFO. S2P LINE DEC. S2P. LINE DEC. MODE CONTROL / STATUS. S2P. PLL. ISO9001 ISO9001 CERTIFIED. Semtech reserves the right to change specifications on catalog devices without .. Tags: 8b10b 2748 ACS406CS |
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First line: Advanced Communications ACS411CS E1/T1 Fiber Abstract: .. 8B10B CODER. TX CONTROL. TX FIFO. S2P LINE DEC. S2P LINE DEC. uP / MEMORY INTERFACE. MODE CONTROL .. 8B10B DEC. S2P. RX AND LOCK CONTROL. RX FIFO. P2S LINE CODER. PLL. DATA SLICE. XTAL OSC. MULT PLL CLOCK .. Tags: 8b10b 2748 ACS411CS |
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First line: SAS/SATA Design Verification Test Tools U3053A U3054A BusMod Error Injector BIST Generator Micro Series SAS/SATA Analyzers ERROR INJECTION Connect Disconnect link CRC, 8b10b encoding, Running Disparity (RD+/-), Invalid Symbol encoding error generation Replace/substitute primitives Replace frame valu Abstract: .. CRC, 8b10b encoding, Running Disparity RD+/- , and Invalid Symbol encoding. error generation. Replace/substitute primitives. Replace frame values with or. without CRC regeneration Insert .. Tags: injector 8b10b U3053A U3054A |
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First line: ACS4060 Advanced Communications ACS406CS E1/T1 Fiber Abstract: .. 8B10B CODER. TX CONTROL PING PONG ENGINE. TX FIFO. S2P LINE DEC. S2P. LINE DEC. MODE CONTROL / STATUS. S2P. PLL. ISO9001 ISO9001 CERTIFIED. Semtech reserves the right to change specifications on catalog devices without .. Tags: ACS4060 8b10b 2748 ACS406CS |
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First line: PE-GMAC0TM Gigabit Ethernet InventraTM Soft Core (RTL Major Product Features: Abstract: .. 8B10B Assembler / Dis-assembler blocks. On the system side, the MAC provides two 32-bit 32-bit parallel. data streams, one for transmit and one for receive. There are. also several control signals associated .. Tags: 8B10B asic 8b10b 10-bit-serdes datasheet abstract.. |
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First line: 8101/8104 Gigabit Ethernet Controller Abstract: .. 2.11 8B10B PCS 2-25. 2.11.1 8B10B Encoder 2-26. 2.11.2 8B10B Decoder 2-28. 2.11.3 Start of Packet 2-29. 2.11.4 End Of Packet 2-30. 2.11.5 Idle 2-30. 2.11.6 Receive Word Synchronization 2-31. 2.11.7 AutoNegotiation .. Tags: sony rxd7 r5 t85 LHi 103 8B10B datasheet abstract.. |
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First line: 8101 8101 Gigabit Ethernet Controller 99110 This document Logic document. reference SEEQ Technology should considered Logic. Abstract: .. â– Combined Ethernet MAC and 8B10B PCS. â– Data Rate - 1000 Mbps. â– 64-Bit 64-Bit @ 66 Mhz Interface to External Bus - 4 Gbps Bandwidth. â– 10-Bit 10-Bit Interface to External PHY or SerDes Chip. â– 16-Bit 16-Bit Interface to Internal .. Tags: sony rxd7 sony 175 4k Seeq Technology - M57C73 Seeq Technology diode T-71 8B10B datasheet abstract.. |
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First line: ECP3-35 LatticeECP3 SERDES/PCS Usage Guide February 2010 Technical Note TN1176 LatticeECP3TM FPGA family combines high-performance FPGA fabric, high-performance I/Os channels embedded SERDES with associated Physical Coding Sublayer (PCS) logic. logic configured support numerous industry-standard, hi Abstract: .. Features Up to 16 Channels of High-Speed SERDES – 150 Mbps to 3.2 Gbps for Generic 8b10b, 10-bit 10-bit SERDES and 8-bit SERDES modes. Refer to Table 8-1. – 230 Mbps to 3.2 Gbps per channel for all other protocols .. Tags: ECP3-35 xaui top 245p IPEX HD-SDI over sdh Aldec 3G-SDI serializer 10-bit-serdes TN1176 |
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First line: LatticeECP3 SERDES/PCS Usage Guide June 2010 Technical Note TN1176 LatticeECP3TM FPGA family combines high-performance FPGA fabric, high-performance I/Os channels embedded SERDES with associated Physical Coding Sublayer (PCS) logic. logic configured support numerous industry-standard, high-speed ser Abstract: .. Features Up to 16 Channels of High-Speed SERDES – 150 Mbps to 3.2 Gbps for Generic 8b10b, 10-bit 10-bit SERDES and 8-bit SERDES modes. Refer to Table 8-1. – 230 Mbps to 3.2 Gbps per channel for all other protocols .. Tags: TN1176 |
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First line: Stratix FPGA July 2007, ver. Abstract: .. 8b10b dec.. Place comp FIFO and byte deser. Place comp FIFO and byte ser. rx_clkout[0] coreclk out[0] Stratix GX GXB Duplex. recouch. J. inclk[0] Ser. coreclk TX PLL. tx_coreclk[0] Deser. RX PLL. Word .. Tags: xaui datasheet abstract.. |
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First line: 13007 X1 LatticeSC/M Family flexiPCS Data Sheet DS1005 Version 01.9, LatticeSC/M Family flexiPCS Data Sheet Table Contents Abstract: .. Generic 8b10b Mode .. Generic 8b10b Register Settings .. Tags: 13007 X1 DS1005 |
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First line: LatticeECP2M SERDES/PCS Usage Guide February 2010 Technical Note TN1124 Introduction LatticeECP2MTM family FPGAs combines high-performance FPGA fabric, high-performance I/Os large embedded single industry leading architecture. LatticeECP2M devices also feature channels embedded SERDES with associate Abstract: .. multiple other standards – Supports user specified generic 8b10b mode – Beacon support for PCI Express – Out-of-band signal interface for low speed inputs video application Multiple Clock .. Tags: top 245p 3G-SDI serializer 10-bit-serdes TN1124 |
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First line: LatticeECP2M SERDES/PCS Usage Guide June 2010 Technical Note TN1124 Introduction LatticeECP2MTM FPGA family combines high-performance FPGA fabric, high-performance I/Os large embedded single industry-leading architecture. LatticeECP2M devices also feature channels embedded SERDES with associated Phy Abstract: .. multiple other standards – Supports user specified generic 8b10b mode – Beacon support for PCI Express – Out-of-band signal interface for low speed inputs video application Multiple Clock .. Tags: TN1124 |
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First line: VSC7166 Abstract: .. • Converts 16 LVDS Inputs at 622Mb 622Mb /s into 12 8B10B Encoded LVDS Outputs at 1.244Gb 244Gb /s. • Converts 12 LVDS Inputs at 1.244Gb 244Gb /s into 16 LVDS Outputs at 622Mb 622Mb /s. • Conforms to OIF99 OIF99 .120. • 8b/10b Encoder .. Tags: 8b10b 8b/10b encoder VSC7166 |
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First line: xaui Marvell 8001 LatticeECP2M Marvell XAUI Gbps Physical Layer Interoperability November 2008 Technical Note TN1191 This technical note describes physical layer Gigabit Ethernet XAUI Gbps) interoperability test between LatticeECP2MTM FPGA Marvell Alaska 88X2040 device. test limited physical layer Abstract: .. • 8b10b encoding. Receive Path Functionality From Line to LatticeECP2M Device • Word alignment based on IEEE 802.3-2002-defined 3-2002-defined alignment characters. • 8b10b decoding. • Link State Machine .. Tags: Marvell 8001 xaui Marvell fibre copper marvell ethernet switch 88X2040-BAN 88X2040* TN1191 |
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First line: 10GbE XGXS Home Products Intellectual Property Lattice Cores 10GbE XGXS 10GbE XGXS Abstract: .. Eight channels of 3.125 Gbits/s serializer/deserializer with 8b10b encoding/decoding four SERDES channels are used in this application . XAUI compliant lane-by-lane synchronization .. Tags: XAUI 10Gb Ethernet XGXS Core datasheet abstract.. |
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