EIE/AN93017 8XC552 80C552 ESG89001 VREF/1024 OM4136 OM4142 OM4120S OM1092 - Datasheet Archive

 

EIE/AN93017 Using the analog-to-digital converter of the 8XC552 microcontroller Theo van Daele, Philips Semiconductors Product

 

INTEGRATED CIRCUITS EIE/AN93017 EIE/AN93017 Using the analog-to-digital converter of the 8XC552 8XC552 microcontroller Theo van Daele, Philips Semiconductors Product Concept & Application Laboratory Eindhoven, the Netherlands Philips Semiconductors 1994 Jun 28 Philips Semiconductors Application note Using the analog-to-digital converter of the 8XC552 8XC552 microcontroller EIE/AN93017 EIE/AN93017 Author: Theo van Daele, Philips Semiconductors Product Concept & Application Laboratory Eindhoven, the Netherlands SUMMARY 2.0 INTERNAL OPERATION OF THE ADC On the 80C552 80C552 microcontroller, an 8-input 10-bit ADC is available. To get correct results from the ADC, the slew-rate of the input signal during sampling must be limited. 10 Bit accuracy will be obtained if the layout of the 80C552 80C552 application is done correctly. EMC measures must be taken into account. Some software examples are given on how to use the ADC. 2.1 General Description Figure 1 shows a general block diagram of the ADC. The inputs of P5 are connected to a multiplexer and an input buffer with Schmitt-trigger inputs. When the digital value on P5 must be read (e.g., with a MOV A,P5 instruction), the output of the Schmitt-trigger is taken. This output can be used for further processing. 1.0 INTRODUCTION The 80C552 80C552 microcontroller has an on-chip ADC. The converter consists of an 8 input analog multiplexer, and a 10-bit binary successive approximation ADC. A conversion takes 50 machine cycles (is 20µs at 30MHz oscillator frequency). The ADC has dedicated analog supply and reference voltages to minimize influence form digital circuitry. The DAC of the successive approximation ADC is a resistor ladder network. This ensures that there no missing codes. An analog input signal on P5 that must be converted is selected by the input multiplexer. The bits ADCON.0 . . ADCON.2 of the ADCON special function register select the input signal. The output of the multiplexer is connected to the input of a comparator. The sampling capacitor is included in the comparator. The ADC control block of the ADC controls the timing of the sampling and conversion. After the input signal is sampled, the actual analog-to-digital conversion starts. The comparator compares the input signal VIN with the output of the 10-bit DAC VDAC. The output voltage of the DAC is determined by the output of the successive approximation register (SAR). The range of the DAC signal varies between AVREF­ and AVREF_. These two signal levels also define the voltage range of the input signal. To obtain the 10-bit accuracy, it is important to pay attention to the design of the application. First the operation of the ADC will be described. Then design and layout subjects are described that can influence the accuracy of the conversion result. References: 1. 80C51-based 8-bit microcontrollers (Data Handbook IC20 1994) 2. Electro Magnetic Compatibility and Printed Circuit Board (PCB) Constraints (ESG89001 ESG89001) SELECT RESET/SAMPLE MUX 1 OF 8 P5 ADC CONTROL VIN START/STOP 8 COMPARATOR AVref+ VDAC DAC SAR 10 ADC RESULT AVref­ 10 SCHMITT TRIGGER P5 VALUE 8 Figure 1. 1994 Jun 28 2663 Philips Semiconductors Application note Using the analog-to-digital converter of the 8XC552 8XC552 microcontroller EIE/AN93017 EIE/AN93017 for the subsequent SAR output bits. At the end of the conversion, VDAC has converged to a value of VIN±1/2LSB. 2.2 Conversion Process Figure 2 shows an example of the conversion principle with 3 bit resolution. Example: VIN is 11/16*VREF. The conversion sequence is shown in Table 1. The SAR will make its output bits SAR2 . . SAR0 successively high from MSB to LSB. Every time a SAR-line is made HIGH, a DA-conversion will take place. If the output of the DAC (VDAC) is higher than the input voltage (VIN), the SAR output bit that was made HIGH the last time will be made LOW. If VDAC is smaller than VIN, the SAR output bit will remain HIGH. The process will proceed After STEP 3 the conversion is finished. The SAR register contains the result of the AD-conversion. The ADC in the 80C552 80C552 has 10 bits resolution. The conversion in this ADC will take 10 conversion steps. Table 1. SAR Value (SAR2.SAR1.SAR0) VDAC (*VREF) Output Comparator Action by SAR START 000 0 0 SAR2=1 STEP 1 100 4/8 0 SAR1=1 STEP 2 110 6/8 1 SAR1=0, SAR0=1 STEP 3 101 5/8 0 VDAC 7/8 VREF 6/8 VREF 5/8 VREF 4/8 VREF 3/8 VREF 2/8 VREF 1/8 VREF t CLOCK SAR2 SAR1 SAR0 RESULT: 101 100 110 Figure 2. 1994 Jun 28 2664 101 Philips Semiconductors Application note Using the analog-to-digital converter of the 8XC552 8XC552 microcontroller EIE/AN93017 EIE/AN93017 inverting input. Using a ladder-network guarantees a monotonic characteristic of the DAC. This in turn will result in an ADC-characteristic without missing codes. The relative deviations of the resistor values result in a non-linear transfer characteristic. 2.3 The ADC in the 80C552 80C552 Figure 3 shows a block diagram of the implementation of the ADC in an 80C552 80C552 microcontroller. The analog input signal VIN is connected to the non-inverting input of the comparator via switch S1 during the sampling interval. Internally the comparator consists of 3 serially connected sampled-data-comparator stages A1 . . A3. The stages are capacitively coupled. The coupling capacitor of the first comparator that is connected to S1 will also act as sample capacitor for VIN. The following three phases in the ADC conversion can be determined and will be described in more detail: ­ Start phase ­ Sampling phase ­ Conversion phase. Sampled-data-comparators are used to minimize the effect of offsets and temperature drive. During the sampling interval, the value of the offset voltage of the comparator stages are stored on the coupling capacitors. This voltage will have the opposite sign of the comparators stages' offset, so it will cancel this offset voltage. This process is called auto-zeroing, and will be explained in 2.3.2. Timing of these phases is shown in Figure 4. 2.3.1 Start Detection Phase An ADC conversion can be started by software or by a hardware trigger on the STADC pin. Software start When an ADC start is initiated by software (set ADCS in ADCON register), the internal start signal will immediately be active at S6P2 (for state timing, see [Reference ]). The value of ADCS can be read by software. However, there is a delay of 2 machine cycles between the internal start signal and the ability of reading a `1' from ADCS. The non-inverting input of the comparator is connected to 1/2VREF via switch S2. S2 consists of 2 parallel switches. There is always 1 switch closed, so the voltage on this input is always 1/2VREF. Although S2 looks superfluous from a functional point of view, it assures that, for instance, switching glitches of S1 and S2 appear on both inputs of the comparator and will cancel each other. Hardware start A hardware start of an ADC conversion is initiated by a rising edge on STADC. The 80C552 80C552 samples STADC every machine cycle during S6P2. When a valid edge is detected, the internal start signal will be active at S1P2 in the subsequent machine cycle. To ensure that the edge is detected, the high and low time should be at least 1 machine cycle each. When a valid edge is detected, `ADCS' is set. When the sampling is finished, the actual conversion will start. S1 will connect the inverting input of the comparator with the output of the DAC. At this moment, the output of the DAC is connected to the center tap of the resistor network. The voltage on the inverting input of the comparator will be 1/2VREF (VREF is defined as 1/ [V 2 ref+ ­ Vref­]). During conversion, the output of the SAR will determine which tap of the ladder-network will be connected to the SAMPLE RESET1 RESET2 RESET3 S1 VIN A1 A1 A1 COMPARATOR SAMPLE S2 VREF+ ­ VREF­)/2 SAMPLE R/2 R R R R R VREF+ R R R R/2 VREF­ 10 SAR DECODER VDAC DAC START/STOP Figure 3. 1994 Jun 28 2665 Philips Semiconductors Application note Using the analog-to-digital converter of the 8XC552 8XC552 microcontroller START EIE/AN93017 EIE/AN93017 SAMPLING CONVERSION END BIT9 MACHINE CYCLES 0 1 2 3 4 5 6 7 8 9 10 11 12 BIT0 13 14 15 45 46 47 48 49 50 51 `ADCS' SAMPLE RESET1 RESET2 RESET3 ADCI `ADCS': INTERNAL SIGNAL. SET BY EITHER SOFTWARE START (ADCON.3=1), OR HARDWARE START ( ON STADC AND ADCON.5=1) Figure 4. The switches are opened when RESET1=0. The differential voltage on the comparator inputs is still VIL because of the stored charge on the coupling capacitors. 2.3.2 Sample Phase The 8 machine cycles following the start detection is the sample interval (Figure 4). In this time interval, the input signal is sampled and the 3 comparator stages are auto-zeroed. The resulting offset voltage VOS1,I seen on the input of the comparator stage is obtained by adding this differential voltage VIL to the input offset voltage VOS1. The actual sampling of the analog input signal on the input capacitor starts at machine cycle `2' (Figure 4). The sample capacitor is connected between VIN and the output of the first comparator state (Figure 3). The sampling is finished at the end of machine cycle `5'. After this machine cycle, the sample capacitor is connected between VIN and the input of the first comparator stage. Since this is a very high impedance input, no extra charge will be stored in the sampling capacitor. V OS1,I + V OS1 ) V IL + V OS1 V O,3 + A 3 V OS,I + The differential voltage (error voltage) on the inputs of the first comparator stage will be: 1994 Jun 28 V OS3 1 ) A3 This voltage can be translated to an effective input offset voltage by dividing it by the total gain of the comparator: When the RESET1=1, switches will connect the outputs of the individual comparator stages to their inputs. The outputs will settle to the unity-gain output voltage VUG. = = = = = The auto-zeroing procedure described above will be repeated successively for the following 2 stages. After auto-zeroing the third comparator stage, the differential output voltage of the total comparator (all 3 comparators in series will be: Figure 5 shows the sampling and auto-zeroing of the first comparator stage. VIN VIL VOL VOS1 A1 A1 1 ) A1 The effective offset voltage at the input of the comparator stage is reduced with a factor (1+A1). At the start of the sample phase, the inverting input of the comparator is connected to VIN via a coupling capacitor. This coupling capacitor also serves as sampling capacitor. The non-inverting input is connected to the DAC via a coupling capacitor to a voltage of 1/2VREF. V IL + V OL + * V OS1 A1 V OS3 A 2 (1 ) A 3) If auto-zeroing was not used, and all comparator stages were DC-coupled, the differential output voltage of the comparator would be: A1 A1 ) 1 VO3 = A1 × A2 × A3 × VOS1 + A2 × A3 × VOS2 + A3 × VOS3 Input voltage of ADC Differential input voltage of first comparator stage Differential output voltage of first comparator stage Offset voltage of first comparator stage Open loop gain of first comparator stage The effective input offset voltage in this case is: V OS,I + V OS1 ) V OS3 V OS2 ) A1 A1 A2 As can be seen, the auto-zeroing reduces the effect of the individual comparator stages considerably. 2666 Philips Semiconductors Application note Using the analog-to-digital converter of the 8XC552 8XC552 microcontroller EIE/AN93017 EIE/AN93017 RESET1 = 1 RESET1 = 0 RESET1 RESET1 VIN VIN VI1 VOS1 ­VOS1 VO1 ­A1 VREF/2 VOS1 VO1 ­A1 VREF/2 RESET1 V I1 +V O1 + *V OS1 RESET1 A1 X*V OS1 (1 ) A1) Figure 5. BEFORE CONVERSION DURING CONVERSION V­ = VDAC ­ (VIN ­ VUG) VIN ­ VUG VIN ­ VUG S1 VIN S1 VIN VUG VUG A1 VUG VUG VREF/2 VDAC A1 VREF/2 DAC VDAC DAC Figure 6. The following voltages are present on the input of the first comparator stage: 2.3.3 Conversion Phase Just before the sampling phase is finished, the following voltages are present over the coupling capacitors of the first comparator stage: Capacitor on inverting input: VIN ­ VUG Capacitor on non-inverting input; 1/ V 2 REF Inverting input: VUG The comparator stage amplifies the differential voltage between its inputs. The output voltage of the first comparator stage will be: ­ VUG For clarity, the offset voltages are neglected. VOL = A1 × (VUG ­ (VDAC ­ VI + VUG) = A1 × (VI ­ VDAC) When the conversion phase is started, S1 (Figure 6) will connect the coupling capacitor of the inverting input to the output of the DAC. The effective voltage on the comparator input is the voltage applied to the coupling capacitor minus the voltage that was stored on the capacitor during the sampling phase. 1994 Jun 28 VDAC ­ VIN + VUG Non-inverting input: After amplification by the 3 comparator stages the input signal for the SAR is |A1 × A2 × A3 × (VIN ­ VDAC)|. Depending on the sign of this signal, the SAR will set or clear the MSB. In the following cycles of the conversion, the other bits of the SAR will be updated. At the end of the conversion VDAC will have a value of VIN±0.5LSB. The contents of the SAR that generates this VDAC is the result of the AD-conversion. 2667 Philips Semiconductors Application note Using the analog-to-digital converter of the 8XC552 8XC552 microcontroller EIE/AN93017 EIE/AN93017 3.0 APPLICATION INFORMATION MAXIMUM SLEW RATE Although the ADC in the 80C552 80C552 has a resolution of 10 bits, the user must be careful in the design of the application to really get this resolution. The constraints can be divided in 2 categories: ­ Constraints on the analog input signal and the input signal source ­ Layout constraints of the design. 1.2 3.1.1 Range of Analog Input Signal The value of the analog input signal must be between VREF+ and VREF­. The span of the analog input signal is VREF = (VREF+ ­ VREF­). There is a minimum limit to the span. This limit depends on the gain of the comparators. A differential voltage of 1LSB (1LSB = VREF/1024 VREF/1024) on the inputs of the comparator should be able to generate a logic `1' or `0' level on the input of the SAR. If not, the resolution of 10 bits for the ADC will not be met. SLEW RATE (V/msec) 3.1 Analog Input Signal Constraints VREF = 4 Volt 0.8 0.6 0.4 VREF = 5 Volt 0.2 0 0 the comparator in the 80C552 80C552 needs a minimum differential input voltage of 0.3mV to generate a valid logic output level. For the 10-bits ADC in the 80C552 80C552, this means that VREF should be at lease 1024*0.3mV=0.31V to get 10-bit resolution. The absolute values of VREF+ and VREF­ that determine this span may not exceed AVSS and AVDD. 6 12 20 FREQUENCY (MHz) 24 30 2: If the slew-rate exceeds a certain value, the accuracy of the conversion will decrease rapidly. The result of the conversion will not have any result anymore with the analog input signal. Tests have shown that the most probable conversion result is 0x3ff (result bits ADS.0 . . ADC.9 are `1'). 3.1.2 Slew Rate of Analog Input Signal A distinction must be made between 2 different slew-rate constraints. The first slew-rate constraint deals with the required accuracy during sampling. The second constraint to prevent wrong readings deals with a limitation on the slew rate that may otherwise lead to a conversion result that has no relation at all with the analog input signal. This error situation will occur when the slew rate is too high in the time frame from machine cycle `2' to machine cycle `9' of the conversion. In this time frame, the comparators are auto-zeroing their offsets. For proper auto-zeroing, the comparator stages must work in their linear region. If the input signal is changing rapidly, the voltage change may couple through the coupling capacitors to the input of the comparator stage. If this voltage change is sufficiently high, it may saturate the comparator stage. The comparator stage is not working in its linear region anymore, and the saturation voltage (equal to about the supply voltage) is stored on the coupling capacitors. 1: To obtain a stable reading from the ADC, the analog input signal should be stable during the sampling time. The sampling may be triggered by an external event (via ADEX pin). From this trigger point until machine cycle `5' (see Figure ), the input signal is sampled and should not change more than the desired accuracy. The ADC has the highest sensitivity to these high slew-rate signals in the time frame from machine cycle `8' to machine cycle `9'. In this time frame the RESET switches of comparator stage 1 and 2 are open; the RESET switch of comparator stage 3 is closed for auto-zeroing. An analog input signal with sufficient slew rate may couple through to comparator stage 3 via the coupling capacitors of stage 1 and 2. The high sensitivity comes from the fact that the signal is amplified by comparator stages 1 and 2 before it reaches the input of comparator stage 3. Example: If a stability of 0.5LSB is required, then the analog input signal should not change more than 0.5LSB in 6 machine cycles. In that situation the maximum slew-rate of the analog input signal is: dV + 0.5LSB dt 6T where T is the machine cycle time. The following graph gives the maximum slew-rate as function of the operating frequency for various values of VREF and a required stability of 1/2LSB for a 10-bit conversion. When the saturation voltage is stored on the coupling capacitors, the following comparator stage is not useful anymore to determine the sign of |VIN ­ VDAC|. Suppose the coupling capacitors on the input of the second comparator stage are charged to the saturation voltage VSAT. The differential output voltage of the first comparator stage will be A1 × (VIN ­ VDAC). This signal is fed to the input of the second comparator stage whose output signal will be A2 × [A1 × (VIN ­ VDAC) ± VSAT]. Since the differential output voltage of the comparator stages can never be higher than ±VSAT, the output of this comparator stage will stay at its saturation level, independent of the value of (VIN ­ VDAC). When the slew-rate of the input signal is more than the maximum slew-rate as determined above, the read-out stability will decrease. The conversion result will be the digital value of the input signal somewhere between machine cycle `0' and machine cycle `5'. Consecutive conversions of a signal that consists of a DC-value with an AC-component that has high slew-rates as mentioned above, and that has the same amplitude between machine cycle `0' and machine cycle `1', may give different read-outs. However, the accuracy of the sampled signal will not be affected. 1994 Jun 28 VREF = 5 Volt 1 2668 Philips Semiconductors Application note Using the analog-to-digital converter of the 8XC552 8XC552 microcontroller EIE/AN93017 EIE/AN93017 Figure 7 shows the input circuit. The leakage current comes mainly from circuitry directly connected to the P5.x pin. Compared with this leakage current, the input current of the comparator can be neglected. CS represents the contribution of the stray capacitances; CC represents the sampling capacitor. Before the sampling capacitor, there is the series resistance RM of the analog multiplexer. The only way to avoid the error mentioned above is to limit the slew rate during the sampling interval (machine cycle 2 to 9). For the ADC in the 80C552 80C552 the slew rate of the analog input signal must be lower than 10V/ms. From the discussion above, it becomes evident that it is essential that the slew-rate of the input signal is limited to 10V/ms. Although `clean' DC signals may be applied to the ADC, noise spikes or crosstalk from neighboring signals may still result in signal components with a slew-rate >10V/ms on the DC signal during the sampling interval. The output resistance RS of the input signal source will cause a voltage drop due to the input leakage current. The voltage that will be converted is the voltage on the sampling capacitor. This voltage is the input voltage VIN minus the voltage drop over RS. This voltage drop will give an error contribution in the conversion result of VIN. The following measures can be taken to reduce the slew rate on analog input signals: When an accuracy of 1/2LSB is required, the maximum source resistance RS is: · Supply the analog signal from a source with low output R S t 0.5LSB II impedance. This will reduce the sensitivity to cross-talk. · Keep the analog input signal lines away from digital signal lines. Example: If VREF = 5.12V and II = 1µA, the source resistor should be less than 2.5k. Analog signals may be screened from digital signal lines with a grounded guard ring on the PCB. · Do not mix analog and digital signals on P5 pins. · Connect an RC filter to the analog inputs. The time constant When this constraint on output resistance of the signal source cannot be met, the analog signal should be buffered with a buffer of sufficiently low output resistance. this buffer should be placed as close as possible to the analog source. the longer leads from buffer to the ADC input will be less sensitive to cross-talk (low impedance source resistance) than long leads from signal source to buffer (high impedance source resistance). Filtering may be included in the buffer stage to limit the slew-rate of the signal to >6); /* Store result */ if (ADC_channel!=7) { /* Prepare conversion of next channel */ ADCON=+ADC_channel; ADCON+ADCON|ADCS; } else { /* ADC0.ADC7 is converted. Send results to UART */ write_UART(&result_ADC,conversion+); if (conversion=10000) conversion=0; ADC_channel=0; ADCON=0; /* Prepare next scan */ ADCON=ADEX; } conversion_finished=FALSE; } } } interrupt 10 using 1 void ADC(void) { ADCON=ADCON&ADCIn; conversion_finished=TRUE; } 1994 Jun 28 /* Clear ADCI flag */ 2676 Philips Semiconductors Application note Using the analog-to-digital converter of the 8XC552 8XC552 microcontroller EIE/AN93017 EIE/AN93017 output.c /* * *0* MODULE : output.c * *0* FILENAME : output.c * *0* APPLICATION : Example program for 80C552 80C552 ADC * *0* PROGRAMMER : T. van Daele * *0* DESCRIPTION : The results of the conversion are written *0* to the 80C552 80C552 UART. * *0* FUNCTIONS : *0* write_UART entry point *0* send_byte trx byte *0* decode trx binary nibble *0* send_bin_byte trx binary byte *0* send_dec_int trx decimal integer *0* send_string trx aSCII string * */ rom rom rom rom rom rom char char char char char char string_0[] string_1[] string_2[] string_3[] string_4[] new_line[] = = = = = = "Conversion #"; ": (Ref is 5.12V)"; "ADC_Channel # "; "mV"; ": "; "\r\n"; /* * *1* FUNCTION : send_byte * *2* SYNOPSYS : send_byte(src_byte) * *3* ARGUMENTS : type name *3* char src_byte * *4* RETURNS : nothing * *5* MODIFIES : nothing * *6* DESCRIPTION : Send byte to terminal via UART *6* Wait till transmission is finished * *7* HISTORY : data who description *7* 05­02­93 tvd initial * */ void send_byte(char src_byte) { S0BUF = src_byte; /* Byte to transmit */ while (TI = 0); /* Wait till byte is transmitted */ TI = 0; /* Clear transmit flag */ } 1994 Jun 28 2677 Philips Semiconductors Application note Using the analog-to-digital converter of the 8XC552 8XC552 microcontroller EIE/AN93017 EIE/AN93017 /* * *1* FUNCTION : decode * *2* SYNOPSYS : decode(char src_nibble) * *3* ARGUMENTS : type name *3* char src_nibble * *4* RETURNS : nothing * *5* MODIFIES : nothing * *6* DESCRIPTION : Decode least significant nibble to *6* ASCII and transmit * *7* HISTORY : data who description *7* 05­02­93 tvd initial * */ void decode(char src_nibble) { if ( src_nibble < 0x0a) send_byte(src_nibble + 0x30); else send_byte(src_nibble + 0x41 ­ 0x0a); } /* * *1* FUNCTION : send_bin_byte * *2* SYNOPSYS : send_bin_byte(char src_byte) * *3* ARGUMENTS : type name *3* char src_byte * *4* RETURNS : nothing * *5* MODIFIES : nothing * *6* DESCRIPTION : Split a binary byte in nibbles, decode *6* to ASCII and transmit * *7* HISTORY : data who description *7* 05­02­93 tvd initial * */ void send_bin_byte(char src_byte) { decode(src_byte>>4) & 0x0f); /* Get ms_nibble */ decode(src_byte & 0x0f); /* Get ls_nibble */ } 1994 Jun 28 2678 Philips Semiconductors Application note Using the analog-to-digital converter of the 8XC552 8XC552 microcontroller EIE/AN93017 EIE/AN93017 /* * *1* FUNCTION : send_dec_int * *2* SYNOPSYS : send_dec_int(unsigned int src_wrd) * *3* ARGUMENTS : type name *3* unsigned src_wrd * *4* RETURNS : nothing * *5* MODIFIES : nothing * *6* DESCRIPTION : Decode binary integer to decimal and *6* transmit * *7* HISTORY : data who description *7* 07­07­93 tvd initial * */ void send_dec_int(unsigned int src_wrd) { unsigned char a,b,c,d,e; a=src_wrd/1000; b=(src_wrd%1000)/100); c=(src_wrd%100)/10; d=src_wrd%10; e=16*c+d; /* /* /* /* /* a=`thousands' */ b=`hundreds' */ c=`tens' */ d=`units' */ Print value for tens and units */ /* Print integer without leading zero's */ if (a=0) { send_byte(0x20); if (b=0) { send_byte(0x20); if (c=0) { send_byte(0x20); decode(d); } else send_bin_byte(e); } else { decode(b); send_bin_byte(e); } } else { send_bin_byte(16*a)+b); send_bin_byte(e); } } 1994 Jun 28 2679 Philips Semiconductors Application note Using the analog-to-digital converter of the 8XC552 8XC552 microcontroller EIE/AN93017 EIE/AN93017 /* * *1* FUNCTION : send_string * *2* SYNOPSYS : send_string(rom char *str_ptr) * *3* ARGUMENTS : type name *3* rom char * str_ptr * *4* RETURNS : nothing * *5* MODIFIES : nothing * *6* DESCRIPTION : Send a string of characters from ROM to *6* terminal. * *7* HISTORY : data who description *7* 05­02­93 tvd initial * */ void send_string(rom char *str_ptr) { while (*str_ptr != 0) send_byte(*(str_ptr+); /* Send byte */ } /* * *1* FUNCTION : write_UART * *2* SYNOPSYS : write_UART(unsigned int *ADC_result, * unsigned int conversion_cnt) * *3* ARGUMENTS : type name *3* unsigned int * src_ptr *3* unsigned int msg_ptr * *4* RETURNS : nothing * *5* MODIFIES : nothing * *6* DESCRIPTION : Decode results to correct format and send *6* to UART * *7* HISTORY : data who description *7* 30­06­93 tvd initial * */ void write_UART(unsigned int *result_ptr, unsigned int conversion_cnt) { unsigned char cnt; send_string(new_line); send_string(new_line); send_string(string_0); send_dec_int(conversion_cnt); send_string(string_1); for (cnt=0;cnt