8XC251SB 87C251SB/83C251SB 83C251SB 80C251SB 80C251SB-16 AP-125 AP-155 AP-709 - Datasheet Archive

 

Embedded Microcontroller User's Manual 8XC251SB Embedded Microcontroller User's Manual February 1995 Order Number 272617-001

 

8XC251SB 8XC251SB Embedded Microcontroller User's Manual 8XC251SB 8XC251SB Embedded Microcontroller User's Manual February 1995 Order Number 272617-001 Information in this document is provided solely to enable use of Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products. Intel Corporation makes no warranty for the use of its products and assumes no responsibility for any errors which may appear in this document nor does it make a commitment to update the information contained herein. Intel retains the right to make changes to these specifications at any time, without notice. Contact your local Intel sales office or your distributor to obtain the latest specifications before placing your product order. MDS is an ordering code only and is not used as a product name or trademark of Intel Corporation. Intel Corporation and Intel's FASTPATH are not affiliated with Kinetics, a division of Excelan, Inc. or its FASTPATH trademark or products. *Other brands and names are the property of their respective owners. Additional copies of this document or other Intel literature may be obtained from: Intel Corporation Literature Sales P.O. Box 7641 Mt. Prospect, IL 60056-7641 or call 1-800-879-4683 © INTEL CORPORATION, 2/26/96 ii CONTENTS CHAPTER 1 GUIDE TO THIS MANUAL 1.1 MANUAL CONTENTS . 1-1 1.2 NOTATIONAL CONVENTIONS AND TERMINOLOGY . 1-3 1.3 RELATED DOCUMENTS . 1-5 1.3.1 Data Sheet .1-6 1.3.2 Application Notes .1-6 1.4 CUSTOMER SERVICE. 1-7 1.4.1 How to Use Intel's FaxBack Service .1-7 1.4.2 How to Use Intel's Application BBS .1-8 1.4.3 How to Find the Latest ApBUILDER Files and Hypertext Manuals and Data Sheets on the BBS .1-9 CHAPTER 2 ARCHITECTURAL OVERVIEW 2.1 8XC251SB 8XC251SB CORE. 2-4 2.1.1 CPU .2-4 2.1.2 Clock and Reset Unit .2-5 2.1.3 Interrupt Handler .2-6 2.1.4 On-chip Code Memory .2-6 2.1.5 On-chip RAM .2-7 2.2 ON-CHIP PERIPHERALS. 2-7 2.2.1 Timer/Counters and Watchdog Timer .2-7 2.2.2 Programmable Counter Array (PCA) .2-7 2.2.3 Serial I/O Port .2-8 CHAPTER 3 ADDRESS SPACES 3.1 ADDRESS SPACES FOR MCS® 251 MICROCONTROLLERS . 3-1 3.1.1 Compatibility with the MCS® 51 Architecture .3-2 3.2 THE 8XC251SB 8XC251SB MEMORY SPACE. 3-5 3.2.1 On-chip General-purpose Data RAM .3-6 3.2.2 On-chip Code Memory (87C251SB/83C251SB 87C251SB/83C251SB) .3-6 3.2.2.1 Accessing On-chip Code Memory in Region 00: .3-6 3.2.3 External Memory .3-8 3.3 THE 8XC251SB 8XC251SB REGISTER FILE . 3-8 3.3.1 Byte, Word, and Dword Registers .3-8 3.3.2 Dedicated Registers .3-10 iii CONTENTS 3.3.2.1 Accumulator and B Register .3-10 3.3.2.2 Extended Data Pointer, DPX .3-10 3.3.2.3 Extended Stack Pointer, SPX .3-11 3.4 SPECIAL FUNCTION REGISTERS (SFRS) . 3-12 CHAPTER 4 PROGRAMMING 4.1 BINARY MODE AND SOURCE MODE CONFIGURATIONS . 4-1 4.1.1 Selecting Binary Mode or Source Mode .4-2 4.2 PROGRAMMING FEATURES OF THE MCS® 251 ARCHITECTURE . 4-4 4.2.1 Data Types .4-4 4.2.2 Register Notation .4-4 4.2.3 Address Notation .4-5 4.2.4 Addressing Modes .4-5 4.3 DATA INSTRUCTIONS . 4-6 4.3.1 Data Addressing Modes .4-6 4.3.1.1 Register Addressing .4-8 4.3.1.2 Immediate .4-8 4.3.1.3 Direct .4-8 4.3.1.4 Indirect .4-9 4.3.1.5 Displacement .4-9 4.3.2 Arithmetic Instructions .4-10 4.3.3 Logical Instructions .4-11 4.3.4 Data Transfer Instructions .4-11 4.4 BIT INSTRUCTIONS . 4-12 4.4.1 Bit Addressing .4-12 4.5 CONTROL INSTRUCTIONS . 4-14 4.5.1 Addressing Modes for Control Instructions .4-14 4.5.2 Conditional Jumps .4-15 4.5.3 Unconditional Jumps .4-16 4.5.4 Calls and Returns .4-16 4.6 PROGRAM STATUS WORDS . 4-17 CHAPTER 5 INTERRUPT SYSTEM 5.1 OVERVIEW . 5-1 5.2 8XC251SB 8XC251SB INTERRUPT SOURCES. 5-3 5.2.1 External Interrupts .5-3 5.2.2 Timer Interrupts .5-4 5.3 PROGRAMMABLE COUNTER ARRAY (PCA) INTERRUPT. 5-5 5.4 SERIAL PORT INTERRUPT. 5-5 5.5 INTERRUPT ENABLE . 5-5 5.6 INTERRUPT PRIORITIES . 5-6 iv CONTENTS 5.7 INTERRUPT PROCESSING . 5-9 5.7.1 Minimum Fixed Interrupt Time .5-10 5.7.2 Variable Interrupt Parameters .5-10 5.7.2.1 Response Time Variables .5-10 5.7.2.2 Computation of Worst-case Latency With Variables .5-12 5.7.2.3 Latency Calculations .5-13 5.7.2.4 Blocking Conditions .5-14 5.7.2.5 Interrupt Vector Cycle .5-14 5.7.3 ISRs in Process .5-15 CHAPTER 6 INPUT/OUTPUT PORTS 6.1 INPUT/OUTPUT PORT OVERVIEW . 6-1 6.2 I/O CONFIGURATIONS. 6-2 6.3 PORT 1 AND PORT 3 . 6-2 6.4 PORT 0 AND PORT 2 . 6-2 6.5 READ-MODIFY-WRITE INSTRUCTIONS . 6-5 6.6 QUASI-BIDIRECTIONAL PORT OPERATION. 6-5 6.7 PORT LOADING. 6-7 6.8 EXTERNAL MEMORY ACCESS . 6-7 CHAPTER 7 TIMER/COUNTERS AND WATCHDOG TIMER 7.1 TIMER/COUNTER OVERVIEW. 7-1 7.2 TIMER/COUNTER OPERATION. 7-1 7.3 TIMER 0. 7-4 7.3.1 Mode 0 (13-bit Timer) .7-4 7.3.2 Mode 1 (16-bit Timer) .7-5 7.3.3 Mode 2 (8-bit Timer With Auto-reload) .7-5 7.3.4 Mode 3 (Two 8-bit Timers) .7-5 7.4 TIMER 1. 7-6 7.4.1 Mode 0 (13-bit Timer) .7-9 7.4.2 Mode 1 (16-bit Timer) .7-9 7.4.3 Mode 2 (8-bit Timer with Auto-reload) .7-9 7.4.4 Mode 3 (Halt) .7-9 7.5 TIMER 0/1 APPLICATIONS. 7-9 7.5.1 Auto-load Setup Example .7-9 7.5.2 Pulse Width Measurements .7-10 7.6 TIMER 2. 7-10 7.6.1 Capture Mode .7-11 7.6.2 Auto-reload Mode .7-12 7.6.2.1 Up Counter Operation .7-12 7.6.2.2 Up/Down Counter Operation .7-13 v CONTENTS 7.6.3 Baud Rate Generator Mode .7-14 7.6.4 Clock-out Mode .7-14 7.7 WATCHDOG TIMER . 7-16 7.7.1 Description .7-16 7.7.2 Using the WDT .7-18 7.7.3 WDT During Idle Mode .7-18 7.7.4 WDT During PowerDown .7-18 CHAPTER 8 PROGRAMMABLE COUNTER ARRAY 8.1 PCA DESCRIPTION . 8-1 8.2 PCA TIMER/COUNTER. 8-2 8.3 PCA COMPARE/CAPTURE MODULES . 8-5 8.3.1 16-bit Capture Mode .8-5 8.3.2 Compare Modes .8-7 8.3.3 16-bit Software Timer Mode .8-7 8.3.4 High-speed Output Mode .8-8 8.3.5 PCA Watchdog Timer Mode .8-9 8.3.6 Pulse Width Modulation Mode .8-11 CHAPTER 9 SERIAL I/O PORT 9.1 OVERVIEW . 9-1 9.2 MODES OF OPERATION. 9-4 9.2.1 Synchronous Mode (Mode 0) .9-4 9.2.1.1 Transmission (Mode 0) .9-4 9.2.1.2 Reception (Mode 0) .9-5 9.2.2 Asynchronous Modes (Modes 1, 2, and 3) .9-6 9.2.2.1 Transmission (Modes 1, 2, 3) .9-6 9.2.2.2 Reception (Modes 1, 2, 3) .9-6 9.3 FRAMING BIT ERROR DETECTION (MODES 1, 2, AND 3). 9-7 9.4 MULTIPROCESSOR COMMUNICATION (MODES 2 AND 3). 9-7 9.5 AUTOMATIC ADDRESS RECOGNITION . 9-7 9.5.1 Given Address .9-8 9.5.2 Broadcast Address .9-9 9.5.3 Reset Addresses .9-10 9.6 BAUD RATES . 9-10 9.6.1 Baud Rate for Mode 0 .9-10 9.6.2 Baud Rates for Mode 2 .9-10 9.6.3 Baud Rates for Modes 1 and 3 .9-10 9.6.3.1 Timer 1 Generated Baud Rates (Modes 1 and 3) .9-11 9.6.3.2 Selecting Timer 1 as the Baud Rate Generator .9-11 9.6.3.3 Timer 2 Generated Baud Rates (Modes 1 and 3) .9-12 9.6.3.4 Selecting Timer 2 as the Baud Rate Generator .9-12 vi CONTENTS CHAPTER 10 MINIMUM HARDWARE SETUP 10.1 MINIMUM HARDWARE SETUP. 10-1 10.2 ELECTRICAL ENVIRONMENT . 10-2 10.2.1 Power and Ground Pins .10-2 10.2.2 Unused Pins .10-2 10.2.3 Noise Considerations .10-2 10.3 CLOCK SOURCES. 10-3 10.3.1 On-chip Oscillator (Crystal) .10-3 10.3.2 On-chip Oscillator (Ceramic Resonator) .10-4 10.3.3 External Clock .10-4 10.4 RESET . 10-5 10.4.1 Externally Initiated Resets .10-6 10.4.2 WDT Initiated Resets .10-6 10.4.3 Reset Operation .10-6 10.4.4 Power-on Reset .10-7 CHAPTER 11 SPECIAL OPERATING MODES 11.1 GENERAL. 11-1 11.2 POWER CONTROL REGISTER . 11-1 11.2.1 Serial I/O Control Bits .11-1 11.2.2 Power Off Flag .11-1 11.3 IDLE MODE . 11-4 11.3.1 Entering Idle Mode .11-4 11.3.2 Exiting Idle Mode .11-5 11.4 POWERDOWN MODE . 11-5 11.4.1 Entering Powerdown Mode .11-6 11.4.2 Exiting Powerdown Mode .11-6 11.5 ON-CIRCUIT EMULATION (ONCE) MODE . 11-7 11.5.1 Entering ONCE Mode .11-7 11.5.2 Exiting ONCE Mode .11-7 CHAPTER 12 EXTERNAL MEMORY INTERFACE 12.1 EXTERNAL MEMORY INTERFACE SIGNALS. 12-1 12.2 CONFIGURING THE EXTERNAL MEMORY INTERFACE. 12-2 12.2.1 Page Mode and Nonpage Mode (PAGE Bit) .12-3 12.2.2 RD#, PSEN#, and the Number of External Address Pins (Bits RD1:0) .12-3 12.2.2.1 Sixteen External Address Bits and a Single Read Signal (RD1 = 1, RD0 = 0) .12-4 12.2.2.2 Seventeen External Address Bits and a Single Read Signal (RD1 = 0, RD0 = 1) .12-4 vii CONTENTS 12.2.2.3 Sixteen External Address Bits and Two Read Signals (RD1 = 1, RD0 = 1) .12-5 12.2.3 Wait States (WSA, WSB, XALE) .12-6 12.2.4 Mapping On-chip Code Memory to Data Memory (87C251SB/83C251SB 87C251SB/83C251SB) .12-7 12.3 EXTERNAL BUS CYCLES . 12-7 12.3.1 Inactive External Bus .12-7 12.3.2 Bus Cycle Definitions .12-8 12.3.3 Nonpage Mode Bus Cycles .12-8 12.3.4 Page Mode Bus Cycles .12-10 12.4 WAIT STATES . 12-13 12.4.1 Extending PSEN#/RD#/WR# .12-13 12.4.2 Extending ALE .12-14 12.5 PORT 0 AND PORT 2 STATUS . 12-15 12.5.1 Port 0 and Port 2 Pin Status in Nonpage Mode .12-15 12.5.2 Port 0 and Port 2 Pin Status in Page Mode .12-16 12.6 EXTERNAL MEMORY DESIGN EXAMPLES. 12-16 12.6.1 Nonpage Mode, 64 Kbytes External EPROM, 64 Kbytes External RAM .12-16 12.6.1.1 An Application Requiring Fast Access to the Stack .12-16 12.6.1.2 An Application Requiring Fast Access to Data .12-17 12.6.2 Nonpage Mode, 128 Kbytes External RAM .12-19 12.6.3 Page Mode, 128 Kbytes External Flash .12-21 12.6.4 Page Mode, 64 Kbytes External EPROM, 64 Kbytes External RAM .12-21 12.6.5 Page Mode, 64 Kbytes External Flash, 32 Kbytes External RAM .12-22 12.7 EXTERNAL BUS AC TIMING SPECIFICATIONS . 12-24 12.7.1 Explanation of AC Symbols .12-28 12.7.2 AC Timing Definitions .12-28 CHAPTER 13 PROGRAMMING AND VERIFYING NONVOLATILE MEMORY 13.1 GENERAL. 13-1 13.2 PROGRAMMING AND VERIFYING MODES. 13-2 13.3 GENERAL SETUP. 13-3 13.4 OTPROM PROGRAMMING ALGORITHM. 13-4 13.5 VERIFY ALGORITHM. 13-5 13.6 PROGRAMMABLE FUNCTIONS . 13-5 13.6.1 On-chip Code Memory .13-5 13.6.2 Configuration Bytes .13-6 13.6.3 Lock Bit System .13-9 13.6.4 Encryption Array .13-10 13.6.5 Signature Bytes .13-10 13.7 VERIFYING THE 83C251SB 83C251SB (ROM) . 13-10 13.8 VERIFYING THE 80C251SB 80C251SB (ROMLESS) . 13-11 viii CONTENTS APPENDIX A INSTRUCTION SET REFERENCE A.1 NOTATION FOR INSTRUCTION OPERANDS . A-2 A.2 OPCODE MAP AND SUPPORTING TABLES . A-4 A.3 INSTRUCTION SET SUMMARY . A-11 A.3.1 Execution Times for Instructions that Access the Port SFRs . A-11 A.3.2 Instruction Summaries . A-14 A.4 INSTRUCTION DESCRIPTIONS . A-26 APPENDIX B SIGNAL DESCRIPTIONS APPENDIX C REGISTERS GLOSSARY INDEX ix CONTENTS FIGURES Figure 2-1 2-2 2-3 3-1 3-2 3-3 3-4 3-5 3-6 4-1 4-2 4-3 4-4 5-1 5-2 5-3 5-4 5-5 5-6 5-7 6-1 6-2 6-3 6-4 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 7-9 7-10 7-11 7-12 8-1 8-2 8-3 8-4 8-5 8-6 8-7 8-8 x Page Functional Block Diagram of the 8XC251SB 8XC251SB.2-2 The CPU.2-5 8XC251SB 8XC251SB Timing .2-6 Address Spaces for MCS® 251 Microcontrollers.3-1 Address Spaces for the MCS® 51 Architecture.3-3 Address Space Mappings MCS® 51 Architecture to MCS® 251 Architecture .3-4 8XC251SB 8XC251SB Memory Space .3-7 The Register File .3-9 Dedicated Registers in the Register File and their Corresponding SFRs.3-11 Binary Mode Opcode Map.4-3 Source Mode Opcode Map .4-3 Program Status Word Register.4-19 Program Status Word 1 Register.4-20 Interrupt Control System .5-2 Interrupt Enable Register .5-6 Interrupt Priority High Register .5-8 Interrupt Priority Low Register .5-8 The Interrupt Process .5-9 Response Time Example #1 .5-11 Response Time Example #2 .5-12 Port 1 and Port 3 Structure.6-3 Port 0 Structure .6-3 Port 2 Structure .6-4 Internal Pullup Configurations .6-6 Basic Logic of the Timer/Counters .7-2 Timer 0/1 in Mode 0 and Mode 1 .7-4 Timer 0/1 in Mode 2, Auto-Reload.7-5 Timer 0 in Mode 3, Two 8-bit Timers.7-6 TMOD: Timer/Counter Mode Control Register .7-7 TCON: Timer/Counter Control Register .7-8 Timer 2: Capture Mode .7-11 Timer 2: Auto Reload Mode (DCEN = 0) .7-12 Timer 2: Auto Reload Mode (DCEN = 1) .7-13 Timer 2: Clock Out Mode.7-15 T2MOD: Timer 2 Mode Control Register.7-16 T2CON: Timer 2 Control Register .7-17 Programmable Counter Array.8-3 PCA 16-bit Capture Mode .8-6 PCA Software Timer and High-speed Output Modes.8-8 PCA Watchdog Timer Mode.8-10 PCA 8-bit PWM Mode .8-11 PWM Variable Duty Cycle .8-12 CMOD: PCA Timer/Counter Mode Register.8-13 CCON: PCA Timer/Counter Control Register.8-14 CONTENTS FIGURES Figure 8-9 9-1 9-2 9-3 9-4 9-5 10-1 10-2 10-3 10-4 10-5 11-1 11-2 12-1 12-2 12-3 12-4 12-5 12-6 12-7 12-8 12-9 12-10 12-11 12-12 12-13 12-14 12-15 12-16 12-17 12-18 12-19 12-20 12-21 12-22 12-23 13-1 13-2 13-3 13-4 13-5 Page CCAPMx: PCA Compare/Capture Module Mode Registers.8-16 Serial Port Block Diagram .9-2 Serial Port Special Function Register.9-3 Mode 0 Timing.9-5 Data Frame (Modes 1, 2, and 3) .9-6 Timer 2 in Baud Rate Generator Mode .9-13 Minimum Setup .10-1 CHMOS On-chip Oscillator.10-3 External Clock Connection .10-4 External Clock Drive Waveforms.10-5 Reset Timing Sequence .10-8 Power Control (PCON) Register.11-2 Idle and Powerdown Clock Control .11-3 Internal and External Memory Spaces for RD1 = 1, RD0 = 0.12-4 Internal and External Memory Spaces for RD1 = 0, RD0 = 1.12-5 Internal and External Memory Spaces for RD1 = 1, RD0 = 1.12-6 External Code Fetch or Data Read Bus Cycle (Nonpage Mode) .12-9 External Write Bus Cycle (Nonpage Mode).12-9 Bus Structure in Nonpage Mode and Page Mode .12-10 External Code Fetch Bus Cycle (Page Mode).12-11 External Data Read Bus Cycle (Page Mode) .12-12 External Write Bus Cycle (Page Mode) .12-12 External Code Fetch or Data Read Bus Cycle with One PSEN#/RD# Wait State (Nonpage Mode) .12-13 External Write Bus Cycle with One WR# Wait State (Nonpage Mode) .12-14 External Code Fetch or Data Read Bus Cycle with One ALE Wait State (Nonpage Mode) .12-14 80C251SB 80C251SB in Nonpage Mode with External EPROM and RAM .12-17 The Memory Space for the Systems of Figure 12-13 and Figure 12-18 .12-18 87C251SB/83C251SB 87C251SB/83C251SB in Nonpage Mode with 128 Kbytes of External RAM.12-19 The Memory Space for the System of Figure 12-15.12-20 80C251SB 80C251SB in Page Mode with External Flash.12-21 80C251SB 80C251SB in Page Mode with External EPROM and RAM .12-22 80C251SB 80C251SB in Page Mode with External Flash and RAM.12-23 The Memory Space for the System of Figure 12-19.12-24 External Bus Cycles for Data/Instruction Read and Data Write in Nonpage Mode .12-25 External Bus Cycles for Data Read and Data Write in Page Mode.12-26 External Bus Cycles for Instruction Read in Page Mode.12-27 Setup for Programming and Verifying .13-3 OTPROM Programming Waveforms .13-4 Configuration Byte 0 .13-7 Configuration Byte 1 .13-8 OTPROM Timing .13-11 xi CONTENTS TABLES Table 2-1 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 3-9 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 4-10 4-11 5-1 5-2 5-3 5-4 5-5 5-6 5-7 6-1 6-2 7-1 7-2 7-3 8-1 8-2 8-3 9-1 9-2 9-3 9-4 9-5 9-6 11-1 12-1 xii Page Summary of 8XC251SB 8XC251SB Features .2-4 Address Mappings.3-4 Register Bank Selection .3-8 Dedicated Registers in the Register File and their Corresponding SFRs.3-12 8XC251SB 8XC251SB SFR Map and Reset Values .3-13 Core SFRs.3-14 I/O Port SFRs .3-14 Serial I/O SFRs .3-15 Timer/Counter and Watchdog Timer SFRs .3-15 Programmable Counter Array (PCA) SFRs.3-15 Examples of Opcodes in Binary and Source Modes .4-2 Data Types .4-4 Notation for Byte Registers, Word Registers, and Dword Registers .4-5 Addressing Modes for Data Instructions in the MCS® 51 Architecture .4-6 Addressing Modes for Data Instructions in the MCS® 251 Architecture .4-7 Bit-addressable Locations .4-13 Addressing Two Sample Bits.4-13 Addressing Modes for Bit Instructions .4-14 Addressing Modes for Control Instructions.4-15 Compare-conditional Jump Instructions .4-16 The Effects of Instructions on the PSW and PSW1 Flags.4-18 Interrupt System Pin Signals .5-1 Interrupt System Special Function Registers .5-3 Interrupt Control Matrix.5-4 Level of Priority.5-7 Interrupt Priority Within Level .5-7 Interrupt Latency Variables .5-13 Actual vs. Predicted Latency Calculations.5-13 Input/Output Port Pin Descriptions .6-1 Instructions for External Data Moves.6-8 Timer/Counter and Watchdog Timer SFRs .7-2 External Signals .7-3 Timer 2 Modes of Operation.7-15 PCA Special Function Registers (SFRs) .8-4 External Signals .8-4 PCA Module Modes .8-15 Serial Port Signals .9-1 Serial Port Special Function Registers .9-2 Summary of Baud Rates .9-10 Timer 1 Generated Baud Rates for Serial I/O Modes 1 and 3.9-12 Selecting the Baud Rate Generator(s) .9-13 Timer 2 Generated Baud Rates .9-14 Pin Conditions in Various Modes.11-3 External Memory Interface Signals.12-1 CONTENTS TABLES Table 12-2 12-3 12-4 12-5 12-6 12-7 12-8 13-1 13-2 13-3 13-4 13-5 A-1 A-2 A-3 A-4 A-5 A-6 A-7 A-8 A-9 A-10 A-11 A-12 A-13 A-14 A-15 A-16 A-17 A-18 A-19 A-20 A-21 A-22 A-23 A-24 A-25 A-26 A-27 A-28 B-1 B-2 B-3 C-1 Page Configuration Bits RD1:0 .12-3 Wait State Selection .12-6 Bus Cycle Definitions (No Wait States) .12-8 Port 0 and Port 2 Pin Status In Normal Operating Mode.12-15 AC Timing Symbol Definitions .12-28 AC Timing Definitions for Specifications on the 8XC251SB 8XC251SB.12-29 AC Timing Definitions for Specifications on the Memory System.12-30 Programming and Verifying Modes .13-2 Configuration Byte Values for 80C251SB 80C251SB and 80C251SB-16 80C251SB-16.13-9 Lock Bit Function .13-9 Contents of the Signature Bytes.13-10 OTPROM Timing Definitions .13-12 Notation for Register Operands. A-2 Notation for Direct Addresses. A-3 Notation for Immediate Addressing . A-3 Notation for Bit Addressing. A-3 Notation for Destinations in Control Instructions . A-3 Instructions for MCS® 51 Microcontrollers . A-4 New Instructions for the MCS® 251 Architecture . A-5 Data Instructions . A-6 High Nibble, Byte 0 of Data Instructions. A-6 Bit Instructions. A-7 Byte 1 (High Nibble) for Bit Instructions. A-7 PUSH/POP Instructions . A-8 Control Instructions . A-8 Displacement/Extended MOVs. A-9 INC/DEC. A-10 Encoding for INC/DEC . A-10 Shifts . A-10 State Times to Access the Port SFRs . A-12 Summary of Add and Subtract Instructions. A-14 Summary of Compare Instructions . A-15 Summary of Increment and Decrement Instructions . A-16 Summary of Multiply, Divide, and Decimal-adjust Instructions. A-16 Summary of Logical Instructions . A-17 Summary of Move Instructions . A-19 Summary of Exchange, Push, and Pop Instructions . A-22 Summary of Bit Instructions. A-23 Summary of Control Instructions . A-24 Flag Symbols. A-26 Signals Arranged by Functional Categories . B-1 Description of Columns of Table B-3. B-2 Signal Descriptions. B-2 8XC251SB 8XC251SB Special Function Registers (SFRs). C-1 xiii CONTENTS TABLES Table xiv Page 1 Guide to This Manual CHAPTER 1 GUIDE TO THIS MANUAL This manual describes the 8XC251SB 8XC251SB embedded microcontroller which is the first member of the MCS® 251 microcontroller family. It is intended for use by both software and hardware designers familiar with the principles of microcontrollers. 1.1 MANUAL CONTENTS This manual contains 13 chapters and 3 appendixes. This chapter, Chapter 1, provides an overview of the manual. This section summarizes the contents of the remaining chapters and appendixes. The remainder of this chapter describes notational conventions and terminology used throughout the manual and provides references to related documentation. Chapter 2 - Architectural Overview - provides an overview of device hardware. It covers core functions (pipelined CPU, clock and reset unit, and on-chip memory) and on-chip peripherals (timer/counters, watchdog timer, programmable counter array, and serial I/O port.) Chapter 3 - Address Spaces - describes the three address spaces of the MCS 251 microcontroller: memory address space, special function register (SFR) space, and the register file. It also provides a map of the SFR space showing the location of the SFRs and their reset values and explains the mapping of the address spaces of the MCS® 51 architecture into the address spaces of the MCS 251 architecture. Chapter 4 - Programming - provides an overview of the instruction set. It describes each instruction type (control, arithmetic, and logical, etc.) and lists the instructions in tabular form. This chapter also discusses the binary mode and source mode configurations, addressing modes, bit instructions, and the program status words. For additional information about the instruction set, see Appendix A. Chapter 5 - Interrupts - describes the 8XC251SB 8XC251SB interrupt circuitry which provides a TRAP instruction interrupt and seven maskable interrupts: two external interrupts, three timer interrupts, a PCA interrupt, and a serial port interrupt. This chapter also discusses the interrupt priority scheme, interrupt enable, interrupt processing, and interrupt response time. Chapter 6- Input/Output Ports - describes the four 8-bit I/O ports (ports 0­3) and explains how to configure them for general-purpose I/O and alternate special functions. It also describes the use of ports 2 and 4 as the external address/data bus. Chapter 7- Timer/Counters and WDT - describes the three on-chip timer/counters and discusses their application. This chapter also provides instructions for using the hardware watchdog timer (WDT) and describes the operation of the WDT during the idle and powerdown modes. 1-1 GUIDE TO THIS MANUAL Chapter 8 - Programmable Counter Array (PCA) - describes the PCA on-chip peripheral and explains how to configure it for general-purpose applications (timers and counters) and special applications (programmable WDT and pulse-width modulator). Chapter 9 - Serial I/O Port - describes the full-duplex serial I/O port and explains how to program it to communicate with external peripherals. This chapter also discusses baud rate generation, framing error detection, multiprocessor communications, and automatic address recognition. Chapter 10 - Minimum Hardware Considerations - describes the basic requirements for operating the 8XC251SB 8XC251SB in a system. It also discusses on-chip and external clock sources and describes device resets, including power-on reset. Chapter 11 - Special Operating Modes - provides an overview of the idle, powerdown, and on-circuit emulation (ONCE) modes and describes how to enter and exit each mode. This chapter also describes the (PCON) register and lists the status of the device pins during the special modes and reset (Table 11-1). Chapter 12 - External Memory Interface - discusses the options available for configuring the external memory interface for a variety of applications. These options include page mode (for accelerated external code fetches), the number of external address bits (16 or 17), the number of external wait states, the regions of memory for strobing PSEN# and RD#, and making a portion of the on-chip code memory accessible as data. This chapter also discusses external memory signals, control registers, and external bus cycles and their timing, and provides several examples of external memory designs. Chapter 13 - Programming and Verifying Nonvolatile Memory - provides instructions for programming and verifying on-chip code memory, configuration bytes, signature bytes, lock bits and the encryption array. This chapter provides the bit definitions of the configuration bytes. Appendix A - Instruction Set Reference - provides reference information for the instruction set. It describes each instruction; defines the bits in the program status word registers (PSW, PSW1); shows the relationships between instructions and PSW flags; and lists hexadecimal opcodes, instruction lengths, and execution times. For additional information about the instruction set, see Chapter 4, "Programming." Appendix B - Signal Descriptions - describes the function(s) of each device pin. Descriptions are listed alphabetically by signal name. This appendix also provides a list of the signals grouped by functional category. Appendix C - Registers - provides for convenient reference a copy of the register definition figures that appear throughout the manual. 1-2 GUIDE TO THIS MANUAL 1.2 NOTATIONAL CONVENTIONS AND TERMINOLOGY The following notations and terminology are used in this manual. The Glossary defines other terms with special meanings. # The pound symbol (#) has either of two meanings, depending on the context. When used with a signal name, the symbol means that the signal is active low. When used in an instruction, the symbol prefixes an immediate value in immediate addressing mode. italics Italics identify variables and introduce new terminology. The context in which italics are used distinguishes between the two possible meanings. Variables in registers and signal names are commonly represented by x and y, where x represents the first variable and y represents the second variable. For example, in register Px.y, x represents the variable [1­4] that identifies the specific port, and y represents the register bit variable [7:0]. Variables must be replaced with the correct values when configuring or programming registers or identifying signals. XXXX Uppercase X (no italics) represents an unknown value or a "don't care" state or condition. The value may be either binary or hexadecimal, depending on the context. For example, 2XAFH (hex) indicates that bits 11:8 are unknown; 10XX in binary context indicates that the two LSBs are unknown. Assert and Deassert The terms assert and deassert refer to the act of making a signal active (enabled) and inactive (disabled), respectively. The active polarity (high/low) is defined by the signal name. Active-low signals are designated by a pound symbol (#) suffix; active-high signals have no suffix. To assert RD# is to drive it low; to assert ALE is to drive it high; to deassert RD# is to drive it high; to deassert ALE is to drive it low. Instructions Instruction mnemonics are shown in upper case to avoid confusion. You may use either upper case or lower case. Logic 0 (Low) An input voltage level equal to or less than the maximum value of VIL or an output voltage level equal to or less than the maximum value of VOL. See data sheet for values. Logic 1 (High) An input voltage level equal to or greater than the minimum value of VIH or an output voltage level equal to or greater than the minimum value of VOH . See data sheet for values. 1-3 GUIDE TO THIS MANUAL Numbers Hexadecimal numbers are represented by a string of hexadecimal digits followed by the character H. Decimal and binary numbers are represented by their customary notations. (That is, 255 is a decimal number and 1111 1111 is a binary number. In some cases, the letter B is added for clarity.) Register Bits Bit locations are indexed by 7:0 for byte registers, 15:0 for word registers, ands 31:0 for double-word (dword) registers, where bit 0 is the least-significant bit and 7, 15, or 31 is the most-significant bit. An individual bit is represented by the register name, followed by a period and the bit number. For example, PCON.4 is bit 4 of the power control register. In some discussions, bit names are used. For example, the name of PCON.4 is POF, the power off flag. Register Names Register names are shown in upper case. For example, PCON is the power control register. If a register name contains a lowercase character, it represents more than one register. For example, CCAPMx represents the five registers: CCAPM0 through CCAPM4. Reserved Bits Some registers contain reserved bits. These bits are not used in this device, but they may be used in future implementations. Do not write a "1" to a reserved bit. The value read from a reserved bit is indeterminate. Set and Clear The terms set and clear refer to the value of a bit or the act of giving it a value. If a bit is set, its value is "1"; setting a bit gives it a "1" value. If a bit is clear, its value is "0"; clearing a bit gives it a "0" value. Signal Names Signal names are shown in upper case. When several signals share a common name, an individual signal is represented by the signal name followed by a number. Port pins are represented by the port abbreviation, a period, and the pin number (e.g., P0.0, P0.1). A pound symbol (#) appended to a signal name identifies an active-low signal. Units of Measure The following abbreviations are used to represent units of measure: A DCV direct current volts Kbyte kilobytes K kilo-ohms mA milliamps, milliamperes Mbyte megabytes MHz 1-4 amps, amperes megahertz GUIDE TO THIS MANUAL ms mW milliwatts ns nanoseconds pF picofarads W watts V volts µA microamps, microamperes µF microfarads µs microseconds µW 1.3 milliseconds microwatts RELATED DOCUMENTS The following documents contain additional information that is useful in designing systems that incorporate the 8XC251SB 8XC251SB microcontroller. To order documents, please call Intel Literature Fulfillment (1-800-548-4725 in the U.S. and Canada; +44(0) 793-431155 in Europe). Embedded Microcontrollers Order Number 270646 Embedded Processors Order Number 272396 Embedded Applications Order Number 270648 Packaging Order Number 240800 1-5 GUIDE TO THIS MANUAL 1.3.1 Data Sheet The data sheet is included in Embedded Microcontrollers and is also available individually. 8XC251SB 8XC251SB CHMOS Single-Chip 8-bit Microcontroller (Commercial/Express) 1.3.2 Order Number 272459 Application Notes The following application notes apply to the MCS 251 microcontroller. AP-125 AP-125, Designing Microcontroller Systems for Electrically Noisy Environments Order Number 210313 AP-155 AP-155, Oscillators for Microcontrollers Order Number 230659 AP-709 AP-709, Maximizing Performance Using MCS 251 Microcontroller -Programming the 8XC251SB 8XC251SB Order Number 272671 The following MCS 51 microcontroller application notes also apply to the MCS 251 microcontroller. AP70, Using the Intel MCS 51 Boolean Processing Capabilities Order Number 203830 AP-223 AP-223, 8051 Based CRT Terminal Controller Order Number 270032 AP-252 AP-252, Designing With the 80C51BH 80C51BH Order Number 270068 AP-425 AP-425, Small DC Motor Control Order Number 270622 AP-410 AP-410, Enhanced Serial Port on the 83C51FA 83C51FA Order Number 270490 AP-415 AP-415, 83C51FA/FB 83C51FA/FB PCA Cookbook Order Number 270609 AP-476 AP-476, How to Implement I2C Serial Communication Using Intel MCS 51 Microcontrollers Order Number 272319 1-6 GUIDE TO THIS MANUAL 1.4 CUSTOMER SERVICE This section provides telephone numbers and describes various customer services. · Customer Support (U.S. and Canada) 800-628-8686 · Customer Training (U.S. and Canada) 800-234-8806 · Literature Fulfillment - 800-468-8118 (U.S. and Canada) - +44(0)793-431155 (Europe) · FaxBack* Service - 800-628-2283 (U.S. and Canada) - +44(0)793-496646 (Europe) - 916-356-3105 (worldwide) · Application Bulletin Board System - 800-897-2536 (U.S. and Canada) - 916-356-3600 (worldwide, up to 14.4-Kbaud line) - 916-356-7209 (worldwide, dedicated 2400-baud line) - +44(0)793-496340 (Europe) Intel provides 24-hour automated technical support through our FaxBack service and our centralized Intel Application Bulletin Board System (BBS). The FaxBack service is a simple-to-use information system that lets you order technical documents by phone for immediate delivery to your fax machine. The BBS is a centralized computer bulletin board system that provides updated application-specific information about Intel products. 1.4.1 How to Use Intel's FaxBack Service Think of the FaxBack service as a library of technical documents that you can access with your phone. Just dial the telephone number (see page 1-7) and respond to the system prompts. After you select a document, the system sends a copy to your fax machine. Each document is assigned an order number and is listed in a subject catalog. First-time users should order the appropriate subject catalogs to get a complete listing of document order numbers. 1-7 GUIDE TO THIS MANUAL The following catalogs and information packets are available: 1. Microcontroller, Flash, and iPLD catalog 2. Development Tools Handbook 3. System catalog 4. DVI and multimedia catalog 5. BBS catalog 6. Microprocessor and peripheral catalog 7. Quality and reliability catalog 8. Technical questionnaire 1.4.2 How to Use Intel's Application BBS The Application Bulletin Board System (BBS) provides centralized access to information, software drivers, firmware upgrades, and revised software. Any user with a modem and computer can access the BBS. Use the following modem settings. · 14400, N, 8, 1 If your modem does not support 14.4K baud, the system provides auto configuration support for 1200- through 14.4K-baud modems. To access the BBS, just dial the telephone number (see page 1-7) and respond to the system prompts. During your first session, the system asks you to register with the system operator by entering your name and location. The system operator will then set up your access account within 24 hours. At that time, you can access the files on the BBS. For a listing of files, call the FaxBack service and order catalog #6 (the BBS catalog). If you encounter any difficulty accessing our high-speed modem, try our dedicated 2400-baud modem (see page 1-7). Use the following modem settings. · 2400 baud, N, 8, 1 1-8 GUIDE TO THIS MANUAL 1.4.3 How to Find the Latest ApBUILDER Files and Hypertext Manuals and Data Sheets on the BBS The latest ApBUILDER files and hypertext manuals and data sheets are available first from the BBS. To access the files: 1. Select [F] from the BBS Main menu. 2. Select [L] from the Intel Apps Files menu. 3. The BBS displays the list of all area levels and prompts for the area number. 4. Select [25] to choose the ApBUILDER / Hypertext area. 5. Area level 25 has four sublevels: (1) General, (2) 196 Files, (3) 186 Files, and (4) 8051 Files. 6. Select [1] to find the latest ApBUILDER files or the number of the appropriate productfamily sublevel to find the hypertext manuals and data sheets. 7. Enter the file number to tag the files you wish to download. The BBS displays the approximate download time for tagged files. 1-9 GUIDE TO THIS MANUAL 1-10 2 Architectural Overview CHAPTER 2 ARCHITECTURAL OVERVIEW The 8XC251SB 8XC251SB is the first microcontroller in Intel's family of MCS® 251 microcontrollers. This family of 8-bit microcontrollers extends the features and performance of the widely-used MCS 51 microcontrollers, while providing binary-code compatibility. Pin compatible with the 8XC51FX 8XC51FX, the 8XC251SB 8XC251SB provides a high-performance upgrade with minimal impact on existing hardware and software. Typical control applications for the 8XC251SB 8XC251SB include copiers, scanners, and CD ROM and tape drives. It is also well suited for communications applications, such as phone terminals, business/feature phones, and phone switching and transmission systems. All MCS 251 microcontrollers share a set of common features: · · · · · · · 24-bit linear addressing and up to 16 Mbytes of memory a register-based CPU with registers accessible as bytes, words, and double words. a page mode for accelerating external instruction fetches an instruction pipeline an enriched instruction set, including 16-bit arithmetic and logic instructions a 64-Kbyte extended stack space a minimum instruction-execution time of two clocks (vs. 12 clocks for MCS 51 microcontrollers) · binary-code compatibility with MCS 51 microcontrollers Several benefits are derived from these features: · preservation of code written for MCS 51 microcontrollers · a significant increase in core execution speed in comparison with MCS 51 microcontrollers at the same clock rate · support for larger programs and more data · increased efficiency for code written in C Figure 2-1 is a functional block diagram of the 8XC251SB 8XC251SB. The core, which is common to all MCS 251 microcontrollers, is described in "8XC251SB 8XC251SB Core" on page 2-4. A specific microcontroller in the family has its own on-chip peripherals, I/O ports, external system bus, size of onchip RAM, and type and size of on-chip program memory. 2-1 ARCHITECTURAL OVERVIEW System Bus & I/O Ports P2 P0 8 8 Code OTPROM/ROM (16 Kbytes) System Bus I/O Ports Memory Data 16 Memory Address Data RAM (1 Kbyte) 16 Bus Interface Code Bus 16 Watchdog Timer Code Address 24 Interrupt Handler Instruction Sequencer SRC1 Timer/ Counters 8 SRC2 Peripherals Peripheral Interface 8 8 Data Bus 24 8 Data Address IB Bus PCA Register File ALU DST Data Memory Interface Clock & Reset 16 Serial I/O MCS® 251 Microcontroller Core 8 P1 Clock & Reset 8 P3 Peripheral Signals & I/O Ports A4109-01 A4109-01 Figure 2-1. Functional Block Diagram of the 8XC251SB 8XC251SB 2-2 ARCHITECTURAL OVERVIEW The 8XC251SB 8XC251SB peripherals include a dedicated watchdog timer, a timer/counter unit, a programmable counter array (PCA), and a serial I/O unit. The 8XC251SB 8XC251SB has four 8-bit I/O ports, P0­P4. Each port pin can be individually programmed as a general I/O signal or a special-function signal that supports the external bus or one of the on-chip peripherals. Ports P0 and P2 comprise the external bus, which has 16 lines that are multiplexed for a 16-bit address and 8-bit data. (You can also configure the 8XC251SB 8XC251SB to have a 17th external address bit. See Chapter 12, "External Memory Interface.") Ports P1 and P3 comprise bus-control and peripheral signals. The 8XC251SB 8XC251SB has two power-saving modes. In idle mode, the CPU clock is stopped, while clocks to the peripherals continue to run. In powerdown mode, the on-chip oscillator is stopped, and the chip enters a static state. An enabled interrupt or a hardware reset can bring the chip back to its normal operating mode from idle or powerdown. See Chapter 11, "Special Operating Modes" for details on the power-saving modes. MCS 251 microcontrollers use an instruction set that has been expanded to include new operations, addressing modes, and operands. Many instructions can operate on 8-, 16-, or 32-bit operands, providing easier and more efficient programming in high-level languages such as C. Additional new features include the TRAP instruction, a new displacement addressing mode, and several conditional jump instructions. Chapter 4, "Programming," describes the instruction set and compares it with the instruction set for MCS 51 microcontrollers. You can configure the 8XC251SB 8XC251SB to run in binary mode or source mode. In either mode, the 8XC251SB 8XC251SB can execute all instructions in the MCS 51 architecture and the MCS 251 architecture. However, source mode is more efficient for MCS 251 architecture instructions, and binary mode is more efficient for MCS 51 architecture instructions. In binary mode, object code for an MCS 51 microcontroller can run on the 8XC251SB 8XC251SB without recompiling. If a system was originally developed using an MCS 51 microcontroller, and if the new 8XC251SB-based system will run code written for the MCS 51 microcontroller, performance will be better with the 8XC251SB 8XC251SB running in binary mode. Object code written for the MCS 51 microcontroller runs faster on the 8XC251SB 8XC251SB. However, if most of the code is rewritten using the new instruction set, performance will be better with the 8XC251SB 8XC251SB running in source mode. In this case the 8XC251SB 8XC251SB can run significantly faster than the MCS 51 microcontroller. See Chapter 4, "Programming" for a discussion of binary mode and source mode. MCS 251 microcontrollers store both code and data in a single, linear 16-Mbyte memory space. The 8XC251SB 8XC251SB can address up to 128 Kbytes of external memory. The special function registers (SFRs) and the register file have separate address spaces. See Chapter 3, "Address Spaces" for a description of the address spaces. 2-3 ARCHITECTURAL OVERVIEW Table 2-1 summarizes some features of the 8XC251SB 8XC251SB. Table 2-1. Summary of 8XC251SB 8XC251SB Features Address Space Register File Code Memory Data RAM I/O Lines External Bus Interrupt Sources 256 Kbytes 40 bytes 83C251SB 83C251SB: 16 Kbytes ROM 87C251SB 87C251SB: 16 Kbytes OTPROM 80C251SB 80C251SB: 0 Kbytes 1 Kbyte 32 Multiplexed: 16/17 Address Bits 8 Data Bits 11 2.1 8XC251SB 8XC251SB CORE The 8XC251SB 8XC251SB core architecture contains the clock and reset unit, the interrupt handler, the bus interface, the peripheral interface, and the CPU. The CPU contains the instruction sequencer, ALU, register file, and data memory interface. 2.1.1 CPU Figure 2-2 is a functional block diagram of the CPU (central processor unit). The 8XC251SB 8XC251SB fetches instructions from on-chip code memory two bytes at a time or from external memory in single bytes. The instructions are sent over the 16-bit code bus to the execution unit. You can configure the 8XC251SB 8XC251SB to operate in page mode for accelerated instruction fetches from external memory. In page mode, if an instruction fetch is to the same 256-byte "page" as the previous fetch, the fetch requires one state (two clocks) rather than two states (four clocks). The 8XC251SB 8XC251SB register file has forty registers, which can be accessed as bytes, words, and double words. As in the MCS 51 architecture, registers 0­7 consist of four banks of eight registers each, where the active bank is selected by the program status word (PSW) for fast context switches. The 8XC251SB 8XC251SB is a single-pipeline machine. When the pipeline is full and code is executing from on-chip code memory, an instruction is completed every state time. When the pipeline is full and code is executing from external memory (with no wait states and no extension of the ALE signal) an instruction is completed every two state times. 2-4 ARCHITECTURAL OVERVIEW 16 Code Bus 24 Code Address Instruction Sequencer Interrupt Handler SRC1 8 SRC2 8 8 Register File ALU Data Memory Interface Data Bus 24 Data Address DST 16 Figure 2-2. The CPU 2.1.2 Clock and Reset Unit The timing source for the 8XC251SB 8XC251SB can be an external oscillator or an internal oscillator with an external crystal/resonator (see Chapter 10, "Minimum Hardware Setup"). The basic unit of time in MCS 251 microcontrollers is the state time (or state), which is two oscillator periods (see Figure 2-3). The state time is divided into phase 1 and phase 2. The 8XC251SB 8XC251SB peripherals operate on a peripheral cycle, which is six state times. (This peripheral cycle is particular to the 8XC251SB 8XC251SB and not a characteristic of the MCS 251 architecture.) A one-clock interval in a peripheral cycle is denoted by its state and phase. For example, the PCA timer is incremented once each peripheral cycle in phase 2 of state 5 (denoted as S5P2). The reset unit places the 8XC251SB 8XC251SB into a known state. A chip reset is initiated by asserting the RST pin or allowing the watchdog timer to time out (see Chapter 10, "Minimum Hardware Setup"). 2-5 ARCHITECTURAL OVERVIEW P1 P2 XTAL1 TOSC 2 TOSC = State Time State 1 P1 P2 State 2 P1 P2 State 3 P1 P2 State 4 P1 P2 State 5 P1 P2 State 6 P1 P2 XTAL1 Peripheral Cycle A2604-01 A2604-01 Figure 2-3. 8XC251SB 8XC251SB Timing 2.1.3 Interrupt Handler The interrupt handler can receive interrupt requests from eleven sources: seven maskable sources and the TRAP instruction. When the interrupt handler grants an interrupt request, the CPU discontinues the normal flow of instructions and branches to a routine that services the source that requested the interrupt. You can enable or disable the interrupts individually (except for TRAP) and you can assign one of four priority levels to each interrupt. See Chapter 5, "Interrupt System" for a detailed description. 2.1.4 On-chip Code Memory For the 83C251SB 83C251SB and the 87C251SB 87C251SB, memory locations FF:0000H 0000H­FF:3FFFH are implemented with 16-Kbytes of on-chip code memory (ROM in the 83C251SB 83C251SB and EPROM in the 87C251SB 87C251SB). Following a reset, the first instruction is fetched from location FF:0000H 0000H. For the 80C251SB 80C251SB location FF:0000H 0000H is always in external memory. 2-6 ARCHITECTURAL OVERVIEW 2.1.5 On-chip RAM The 8XC251SB 8XC251SB has 1-Kbyte of on-chip data RAM (locations 20H­41FH) which can be accessed with direct, indirect, and displacement addressing. Ninety-six of these locations (20H­7FH) are bit addressable. An additional 32 bytes of on-chip RAM (00H­1FH) provide storage for the four banks of registers R0­R7. 2.2 ON-CHIP PERIPHERALS The on-chip peripherals, which lie outside the core, perform specialized functions. Software accesses the peripherals via their special function registers (SFRs). The 8XC251SB 8XC251SB has four peripherals: the watchdog timer, the timer/counters, the programmable counter array (PCA), and the serial I/O port. 2.2.1 Timer/Counters and Watchdog Timer The timer/counter unit has three timer/counters, which can be clocked by the oscillator (for timer operation) or by an external input (for counter operation). You can set up an 8-bit, 13-bit, or 16bit timer/counter, and you can program them for special applications, such as capturing the time of an event on an external pin, outputting a programmable clock signal on an external pin, or generating a baud rate for the serial I/O port. Timer/counter events can generate interrupt requests. The watchdog timer is a circuit that automatically resets the 8XC251SB 8XC251SB in the event of a hardware or software upset. When enabled by software, the watchdog timer begins running, and unless software intervenes, the timer reaches a maximum count and initiates a chip reset. In normal operation, software periodically clears the timer register to prevent the reset. If an upset occurs and software fails to clear the timer, the resulting chip reset disables the timer and returns the system to a known state. The watchdog and the timer/counters are described in Chapter 7, "Timer/Counters and WatchDog Timer." 2.2.2 Programmable Counter Array (PCA) The programmable counter array (PCA) has its own timer and five capture/compare modules that perform several functions: capturing (storing) the timer value in response to a transition on an input pin; generating an interrupt request when the timer matches a stored value; toggling an output pin when the timer matches a stored value; generating a programmable PWM (pulse width modulator) signal on an output pin; and serving as a software watchdog timer. Chapter 8, "Programmable Counter Array" describes this peripheral in detail. 2-7 ARCHITECTURAL OVERVIEW 2.2.3 Serial I/O Port The serial I/O port provides one synchronous and three asynchronous communication modes. The synchronous mode (mode 0) is half-duplex: the serial port outputs a clock signal on one pin and transmits or receives data on another pin. The asynchronous modes (modes 1­3) are full-duplex (i.e., the port can send and receive simultaneously). Mode 1 uses a serial frame of 10 bits: a start bit, 8 data bits, and a stop bit. The baud rate is generated by overflow of timer 1 or timer 2. Modes 2 and 3 use a serial frame of 11 bits: a start bit, eight data bits, a programmable ninth data bit, and a stop bit. The ninth bit can be used for parity checking or to specify that the frame contains an address and data. In mode 2, you can use a baud rate of 1/32 or 1/64 of the oscillator frequency. In mode 3, you can use the overflow from timer 1 or timer 2 to determine the baud rate. In its synchronous modes (modes 1­3) the serial port can operate as a slave in an environment where multiple slaves share a single serial line. It can accept a message intended for itself or a message that is being broadcast to all of the slaves, and it can ignore a message sent to another slave. 2-8 3 Address Spaces CHAPTER 3 ADDRESS SPACES MCS® 251 microcontrollers have three address spaces: a memory space, a special function register (SFR) space, and a register file. This chapter describes these address spaces as they apply to all MCS 251 microcontrollers and to the 8XC251SB 8XC251SB in particular. It also discusses the compatibility of the MCS 251 architecture and the MCS 51 architecture in terms of their address spaces. 3.1 ADDRESS SPACES FOR MCS® 251 MICROCONTROLLERS Figure 3-1 shows the memory space, the SFR space, and the register file for MCS 251 microcontrollers. (The address spaces are depicted as being eight bytes wide with addresses increasing from left to right.) Memory Address Space 16 Mbytes FF:FFFFH SFR Space 512 Bytes S:1FFH S:007H S:000H Register File 64 Bytes 63 00:0000H 0000H 00:0007H 0007H 0 7 A4100-01 A4100-01 Figure 3-1. Address Spaces for MCS® 251 Microcontrollers 3-1 ADDRESS SPACES It is convenient to view the unsegmented, 16-Mbyte memory space as consisting of 256 64-Kbyte regions, numbered 00: to FF:. NOTE The memory space in the MCS 251 architecture is unsegmented. The 64Kbyte "regions" 00:, 01:, ., FF: are introduced only as a convenience for discussions. Addressing in the MCS 251 architecture is linear; there are no segment registers. MCS 251 microcontrollers can have up to 64 Kbytes of on-chip code memory in region FF:. Onchip data RAM begins at location 00:0000H 0000H. The first 32 bytes (00:0000H 0000H­00:001FH 001FH) provide storage for a part of the register file. On-chip, general-purpose data RAM begins at 00:0020H 0020H. The sizes of the on-chip code memory and on-chip RAM depend on the particular device. The register file has its own address space (Figure 3-1). The 64 locations in the register file are numbered decimally from 0 to 63. Locations 0­7 represent one of four, switchable register banks, each having 8 registers (see "The 8XC251SB 8XC251SB Register File" on page 3-8). The 32 bytes required for these banks occupy locations 00:0000H 0000H­00:001FH 001FH in the memory space. Register file locations 8­63 do not appear in the memory space. The SFR space can accommodate up to 512 8-bit special function registers with addresses S:000H­S:1FFH. Some of these locations may be unimplemented in a particular device. In the MCS 251 architecture, the prefix "S:" is used with SFR addresses to distinguish them addresses from the memory space addresses 00:0000H 0000H­00:01FFH 01FFH. 3.1.1 Compatibility with the MCS ® 51 Architecture The address spaces in the MCS 51 architecture are mapped into the address spaces in the MCS 251 architecture. This mapping allows code written for MCS 51 microcontrollers to run on MCS 251 microcontrollers. (Chapter 4, "Programming," discusses the compatibility of the two instruction sets.) Figure 3-2 shows the address spaces for the MCS 51 architecture. Internal data memory locations 00H­7FH can be addressed directly and indirectly. Internal data locations 80H­FFH can only be addressed indirectly. Directly addressing these locations accesses the Special Function Registers (SFRs). The register file (registers R0­R7) comprises four, switchable register banks, each having 8 registers. The 32 bytes required for the four banks occupy locations 00H­1FH in the on-chip data memory. MCS® 51 3-2 Microcontroller Family User's Manual (Order Number: 272383) ADDRESS SPACES The 64-Kbyte code memory has a separate memory space. Data in the code memory can be accessed only with the MOVC instruction. Similarly, the 64-Kbyte external data memory can be accessed only with the MOVX instruction. Figure 3-3 shows how the address spaces in the MCS 51 architecture map into the address spaces in the MCS 251 architecture; details are listed in Table 3-1. FFFFH Code (MOVC) 0000H 0000H FFFFH Register File R0 R7 External Data (MOVX) 0000H 0000H FFH FFH Internal Data (indirect) SFRs (direct) 80H 80H 7FH Internal Data (direct, indirect) 00H A4139-01 A4139-01 Figure 3-2. Address Spaces for the MCS® 51 Architecture 3-3 ADDRESS SPACES Memory Address Space 16 Mbytes FFFFH SFR Space 512 Bytes MCS® 51 Architecture Code Memory S:1FFH FF:0000H 0000H 0000H 0000H S:100H FFH 80H MCS 51 Architecture SFRs S:07FH 02:0000H 0000H S:000H FFFFH MCS 51 Architecture External Data Memory 01:0000H 0000H 0000H 0000H Register File 64 Bytes 63 00:0000H 0000H 00H MCS 51 Architecture Internal Data Memory FFH 8 0 0 MCS 51 Architecture R. F. 7 A4133-01 A4133-01 Figure 3-3. Address Space Mappings MCS® 51 Architecture to MCS® 251 Architecture Table 3-1. Address Mappings MCS ® 51 Architecture Memory Type Size Location MCS® 251 Architecture Data Addressing Location Code 64 Kbytes 0000H 0000H­FFFFH Indirect using MOVC instr. FF:0000H 0000H­FF:FFFFH External Data 64 Kbytes 0000H 0000H­FFFFH Indirect using MOVX instr. 01:0000H 0000H­01:FFFFH 128 bytes 00H­7FH Direct, Indirect 00:0000H 0000H­00:007FH 007FH 128 bytes 80H­FFH Indirect 00:0080H 0080H­00:00FFH 00FFH SFRs 128 bytes S:80H­S:FFH Direct S:080H­S:0FFH Register File 8 bytes R0­R7 Register R0­R7 Internal Data 3-4 ADDRESS SPACES The 64-Kbyte code memory for MCS 51 microcontrollers maps into region FF: of the memory space for MCS 251 microcontrollers. Assemblers for MCS 251 microcontrollers assemble code for MCS 51 microcontrollers into region FF:, and data accesses to code memory are directed to this region. The assembler also maps the interrupt vectors to region FF:. This mapping is transparent to the user; code executes just as before without modification. The 64-Kbyte external data memory for MCS 51 microcontrollers is mapped into the memory region specified by bits 16­23 of the data pointer DPX, i.e., DPXL, which is accessible as register file location 57 and also as the SFR at S:084H (see "Dedicated Registers" on page 3-10). The reset value of DPXL is 01H, which maps the external memory to region 01: as shown in Figure 3-3. You can change this mapping by writing a different value to DPXL. A mapping of the MCS 51 microcontroller external data memory into any 64-Kbyte memory region in the MCS 251 architecture provides complete run-time compatibility because the lower 16 address bits are identical in the two address spaces. The on-chip data memory for MCS 51 microcontrollers is mapped to region 00: to ensure complete run-time compatibility. From location 00H to 7FH, the internal data memory is the same in the two architectures. In the MCS 251 architecture, the data memory extends beyond these 128 bytes to allow enhanced data and stack access using new instructions. The 128-byte SFR space for MCS 51 microcontrollers is mapped into the 512-byte SFR space of the MCS 251 architecture starting at address S:080H, as shown in Figure 3-3. This provides complete compatibility with direct addressing of MCS 51 microcontroller SFRs (including bit addressing). The SFR addresses are unchanged in the new architecture. In the MCS 251 architecture, SFRs A, B, DPL, DPH, and SP (as well as the new SFRs DPXL and SPH) reside in the register file for high performance. However, to maintain compatibility, they are also mapped into the SFR space at the same addresses as in the MCS 51 architecture. 3.2 THE 8XC251SB 8XC251SB MEMORY SPACE The logical memory space for the 8XC251SB 8XC251SB microcontroller is shown in Figure 3-4. The arrows on the left side indicate the addressing modes that apply to the partitions of the memory space. (Chapter 4, "Programming," discusses addressing modes.) The right side of the figure shows the hardware implementation of the different areas of the memory space. For the 8XC251SB 8XC251SB, the usable memory space consists of four 64-Kbyte regions: 00:, 01:, FE:, and FF:. Code can execute from all four regions. Regions 02:­FD: are reserved. Reading a location in the reserved area returns an unspecified value. Software can execute a write to the reserved area, but nothing is actually written. 3-5 ADDRESS SPACES 3.2.1 On-chip General-purpose Data RAM Memory locations 00:0020H 0020H­00:041FH 041FH are implemented as 1 Kbyte of on-chip RAM, which can be used for general data storage. Instructions cannot execute from on-chip data RAM. The data is accessible by direct, indirect, and displacement addressing. Locations 00:0020H 0020H­00:007FH 007FH are also bit addressable. 3.2.2 On-chip Code Memory (87C251SB/83C251SB 87C251SB/83C251SB) The 87C251SB/83C251SB 87C251SB/83C251SB has 16-Kbytes of on-chip OTPROM/ROM at locations FF:0000H 0000H­ FF:3FFFH. This memory is intended primarily for code storage, although its contents can also be read as data with the indirect and displacement addressing modes. Following a chip reset, program execution begins at FF:0000H 0000H. Chapter 13, "Programming and Verifying Nonvolatile Memory," describes programming and verification of the OTPROM/ROM. NOTE Beware of executing code from the upper eight bytes of the on-chip OTPROM/ROM (FF:3FFF8H­FF:3FFFFH). The 8XC251SB 8XC251SB may attempt to prefetch code from external memory (at an address above FF:3FFFH) and thereby disrupt I/O ports 0 and 2. Fetching code constants from these eight bytes does not affect ports 0 and 2. A code fetch in the range FF:0000H 0000H­FF:3FFFH accesses the on-chip OTPROM/ROM only if EA# = 1. For EA# = 0, a code fetch in this address range accesses external memory. The value of EA# is latched when the chip leaves the reset state. 3.2.2.1 Accessing On-chip Code Memory in Region 00: The 87C251SB/83C251SB 87C251SB/83C251SB can be configured so that the upper 8 Kbytes of the on-chip code memory can be read as data in region 00: (see "Configuration Bytes" on page 13-6). This is useful for accessing code constants stored in OTPROM/ROM. Specifically, the upper 8 Kbytes of code memory are mapped to locations 00:E000H E000H­00:FFFFH (as well as to locations FF:E000H E000H­ FF:FFFFH) if the following three conditions hold: · The 87C251SB/83C251SB 87C251SB/83C251SB is configured with EMAP = 0 in the CONFIG1 register (Chapter 13, "Programming and Verifying Nonvolatile Memory"). · EA# = 1. · The access is a data read, not a code fetch. If one or more of these conditions do not hold, accesses to locations 00:E000H E000H­00:FFFFH are referred to external memory. 3-6 ADDRESS SPACES Memory Address Space FF:FFFFH Implementation External Memory FE:4000H-FF 4000H-FF:FFFFH 16-Kbyte On-chip OTPROM/ROM FF:0000H-FF 0000H-FF:3FFFH FF:0000H 0000H FE:FFFFH External Memory FE:0000H-FE 0000H-FE:FFFFH FE:0000H 0000H Indirect and Displacement Addressing (16 Mbytes) Pages 02:­FD: are Reserved 01:FFFFH External Memory 01:0000H-01 0000H-01:FFFFH 01:0000H 0000H 00 FFFFH Direct Addressing (64 Kbytes) Bit Addressing (96 Bytes) Register Addressing (32 Bytes) External Memory 00:0420H-00 0420H-00:FFFFH 00:007FH 007FH 1-Kbyte On-chip RAM 00:0020H-00 0020H-00:041FH 041FH 00:0020H 0020H 00:001FH 001FH 00:0000H 0000H Register File 00:0000H-00 0000H-00:001FH 001FH A4101-01 A4101-01 Figure 3-4. 8XC251SB 8XC251SB Memory Space 3-7 ADDRESS SPACES 3.2.3 External Memory Regions 01: and FE: and portions of regions 00: and FF: of the memory space are implemented as external memory (Figure 3-4). External memory is described in Chapter 12, "External Memory Interface." 3.3 THE 8XC251SB 8XC251SB REGISTER FILE The 8XC251SB 8XC251SB register file consists of 40 locations: 0­31 and 56­63, as shown in Figure 3-5. Locations 0­7 are in the on-chip RAM. The other locations are in the CPU. Registers 0­7 actually consist of four switchable banks of eight registers each. These 32 bytes are stored in locations 00:0000H 0000H­00:001FH 001FH in the memory space and are implemented in the on-chip RAM. However, because these locations are dedicated to the register file, they are not considered a part of the general-purpose, 1-Kbyte on-chip RAM (locations 00:0020H 0020H­00:041FH 041FH). Bits RS1 and RS0 in the PSW register select one of the four register banks to be active, i.e., to currently serve as register file locations 0­7, as shown in Table 3-2. (The PSW is described in "Program Status Words" on page 4-17.) This bank selection can be used for fast context switches. The inactive banks are inaccessible via the register file; however, registers in both the active and inactive banks can be addressed as locations in the memory space. Register file locations 32­55 are reserved and cannot be accessed. Table 3-2. Register Bank Selection PSW Selection Bits Bank Address Range RS1 RS0 Bank 0 0 0 08H­0FH 0 1 Bank 2 10H-17H 10H-17H 1 0 Bank 3 3.3.1 00H­07H Bank 1 18H-1FH 18H-1FH 1 1 Byte, Word, and Dword Registers Depending on its location in the register file, a register is addressable as a byte, a word, and/or a dword, as shown in the right side of Figure 3-5. A register is named for its least-significant byte. For example: R4 is the byte register consisting of location 4. WR4 is the word register consisting of registers 4 and 5. DR4 is the dword register consisting of registers 4­7. 3-8 ADDRESS SPACES Locations R0­R15 are addressable as bytes, words, or dwords. Locations 16­31 are addressable only as words or dwords. Locations 56­63 are addressable only as dwords. Registers are addressed only by the names shown in Figure 3-5 - except for the 32 registers that comprise the four banks of registers R0­R7, which can also be accessed as locations 00:0000H 0000H­00:001FH 001FH in the memory space. Byte Registers Note: R10 = B R11 = ACC R8 R9 R10 R11 R12 R13 R14 R15 R0 R1 R2 R3 R4 R5 R6 R7 Register File 56 57 58 59 60 Word Registers 61 62 63 Locations 32-55 are Reserved 24 16 8 25 17 9 26 18 10 27 19 11 28 20 12 29 21 13 30 22 14 31 23 15 0 1 2 3 4 5 6 7 WR24 WR16 WR26 WR18 WR28 WR20 WR30 WR22 WR8 WR0 WR10 WR2 WR12 WR4 WR14 WR6 Dword Registers DR56 = DPX 0 1 2 3 4 5 DR24 DR16 DR28 DR20 DR8 DR0 6 DR60 = SPX DR12 DR4 7 Banks 0-3 A4099-01 A4099-01 Figure 3-5. The Register File 3-9 ADDRESS SPACES 3.3.2 Dedicated Registers The register file has four dedicated registers: · · · · R10 is the B-register R11 is the accumulator (ACC) DR56 is the extended data pointer, DPX DR60 is the extended stack pointer, SPX These registers are located in the register file; however, R10, R11, and some bytes of DR56 and DR60 are also accessible as SFRs. The bytes of DPX and SPX can be accessed in the register file only by addressing the dword registers. The dedicated registers in the register file and their corresponding SFRs are illustrated in Figure 3-6 and listed in Table 3-3 on page 3-12. 3.3.2.1 Accumulator and B Register The 8-bit accumulator (ACC) is byte register R11, which is also accessible in the SFR space as ACC at S:0E0H (Figure 3-6). The B register, used in multiplies and divides, is register R10, which is also accessible in the SFR space as B at S:0F0H. Accessing ACC or B as a register is one state faster than accessing them as SFRs. Instructions in the MCS 51 architecture use the accumulator as the primary register for data moves and calculations. However, in the MCS 251 architecture, any of registers R1­R15 can serve for these tasks. As a result, the accumulator does not play the central role that it has in MCS 51 microcontrollers. 3.3.2.2 Extended Data Pointer, DPX Dword register DR56 is the extended data pointer, DPX (Figure 3-6). The lower three bytes of DPX (DPL, DPH, and DPXL) are accessible as SFRs. DPL and DPH comprise the 16-bit data pointer DPTR. While instructions in the MCS 51 architecture always use DPTR as the data pointer, instructions in the MCS 251 architecture can use any word or dword register as a data pointer. DPXL, the byte in location 58, specifies the region of memory (00:­FF:) that maps into the 64Kbyte external data memory space in the MCS 51 architecture. In other words, the MOVX instruction addresses the region specified by DPXL when it moves data to and from external memory. The reset value of DPXL is 01H. Bits in the PSW and PSW1 registers reflect the status of the accumulator. There are no equivalent status indicators for the other registers. 3-10 ADDRESS SPACES 3.3.2.3 Extended Stack Pointer, SPX Dword register DR60 is the stack pointer, SPX (Figure 3-6). The low byte (location 60) is the 8bit stack pointer, SP, in the MCS 51 architecture. The byte at location 61 is the stack pointer high, SPH. The two bytes allow the stack to extend to the top of memory region 00:. SP and SPH can be accessed as SFRs. Two instructions, PUSH and POP directly address the stack pointer. Subroutine calls (ACALL, ECALL, LCALL) and returns (ERET, RET, RETI) also use the stack pointer. To preserve the stack, do not use DR60 as a general-purpose register. Register File SFRs Stack Pointer, High Stack Pointer SPH SPH S:0BDH SP S:081H SP 60 62 63 61 DR60 = Extended Stack Pointer, SPX Data Pointer Extended, Low Data Pointer, High Data Pointer, Low DPXL 56 DPH 58 DPH S:83H DPL S:82H DPL 57 DPXL S:84H 59 DR56 = Extended Data Pointer, DPX B ACC B S:0F0H S:0E0H ACC R10, B Register R11, Accumulator, ACC A4152-01 A4152-01 Figure 3-6. Dedicated Registers in the Register File and their Corresponding SFRs 3-11 ADDRESS SPACES Table 3-3. Dedicated Registers in the Register File and their Corresponding SFRs Register File Name Mnemonic - Stack Pointer (SPX) SFRs - - Mnemonic Address - - 61 - - 62 SPH S:BDH SP 63 SP S:81H - 56 - - 57 DPXL S:84H 58 DPH S:83H Stack Pointer, High SPH Data Pointer, Extended High Data Pointer, Extended Low DPXL Data Pointer, High DPH Data Pointer, Low DR60 DPL DPTR Location 60 - Stack Pointer, Low Data Pointer (DPX) Reg. DR56 59 DPL S:82H Accumulator (A Register) A R11 11 ACC S:E0H B Register B R10 10 B S:F0H 3.4 SPECIAL FUNCTION REGISTERS (SFRS) The special function registers (SFRs) reside in the their associated on-chip peripherals or in the core. Table 3-4 shows the SFR address space with the SFR mnemonics and reset values. SFR addresses are preceded by "S:" to differentiate them from addresses in the memory space. Unoccupied locations in the SFR space (the shaded locations in Table 3-4) are unimplemented, i.e., no register exists. If an instruction attempts to write to an unimplemented SFR location, the instruction executes, but nothing is actually written. If an unimplemented SFR location is read, it returns an unspecified value. NOTE SFRs may be accessed only as bytes; they may not be accessed as words or dwords. 3-12 ADDRESS SPACES Table 3-4. 8XC251SB 8XC251SB SFR Map and Reset Values 0/8 1/9 F0 D8 D0 C8 4/C 5/D 6/E CH CCAP0H CCAP1H CCAP2H CCAP3H CCAP4H xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 7/F xxxxxxxx FF B F7 00000000 CL CCAP0L CCAP1L CCAP2L CCAP3L CCAP4L 00000000 E8 E0 3/B 00000000 F8 2/A xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx EF ACC E7 00000000 CCON CMOD CCAPM0 CCAPM1 CCAPM2 CCAPM3 CCAPM4 00x00000 00xxx000 x0000000 x0000000 x0000000 x0000000 x0000000 PSW PSW1 00000000 DF 00000000 D7 T2CON T2MOD RCAP2L RCAP2H TL2 TH2 00000000 xxxxxx00 00000000 00000000 00000000 00000000 CF C0 B8 B0 A8 A0 98 90 88 80 C7 IPL0 SADEN SPH x0000000 00000000 00000000 BF P3 IPH0 11111111 x0000000 IE0 SADDR 00000000 00000000 AF P2 WDTRST 11111111 xxxxxxxx SCON A7 SBUF 00000000 xxxxxxxx 9F P1 97 11111111 TCON TMOD TL0 TL1 TH0 TH1 00000000 00000000 00000000 00000000 00000000 00000000 8F P0 SP DPL DPH DPXL PCON 11111111 00000111 00000000 00000000 00000001 00xx0000 0/8 1/9 2/A 3/B 4/C NOTE: B7 5/D 6/E 87 7/F Shade