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8XC196KC instruction set

Catalog Datasheet MFG & Type PDF Document Tags

8096 MICROCONTROLLER ADDRESSING MODES

Abstract: 8XC196KC instruction set software portion provides an overview of the MCS®-96 instruction set. It discusses differences between the 8XC196KC/KD instruction set and that of the 8096BH and offers guidelines for program development. (For detailed information about the 8XC196KC/KD instruction set, see Appendix A.) Chapter 3 â'" Data Types and , '" 8XC196KC/KD Instruction Set Reference â'" provides reference information for the 8XC196KC/KD instruction , additional information about the instruction set, see Chapter 2 and Appendix A.) Chapter 4 â'" Memory
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8XC196KC/KD AP-125 8096 MICROCONTROLLER ADDRESSING MODES 8XC196KC instruction set IC-96 MCS-96 architecture overview MCS-96 Macro Assembler guide 8XC196KC chapter 5 interrupts MCS-96 PL/M-96 8XC196KD AP-406

8XC196KC instruction set

Abstract: 80C196KC instruction set 8XC196KC/KD A Instruction Set Reference APPENDIX A 8XC196KC/KD INSTRUCTION SET REFERENCE This appendix provides reference information for the 8XC196KC/KD instruction set. It describes each instruction , times, for PTS cycles. A-1 « 8XC196KC/KD INSTRUCTION SET REFERENCE Table A-1. Operand Variables , . inte! A-2 inte! « 8XC196KC/KD INSTRUCTION SET REFERENCE Table A-2. Instruction Set Mnemonic Operation , breg, baop (011100aa) (baop) (breg) A-3 inte! « 8XC196KC/KD INSTRUCTION SET REFERENCE Table A
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80C196KC instruction set 8096 instruction set 8XC196KC/KD instructions 8XC196KC/272238-001 110000AA 8XC196KC/KD+complete+users+manual

mcs-96 instruction set

Abstract: MCS-96 architecture overview the 8XC196KC/KD instruction set and that of the 8096BH, and offers guidelines for program development. Appendix A provides reference information for the 8XC196KC/KD instruction set. It includes descriptions of , been added to the standard MCS-96 instruction set to form the 8XC196KC/KD instruction set. Please refer , . Instruction Set Differences For many instructions, execution times are shorter on the 8XC196KC/KD than on the , (I/O) operations. They share a common architecture and instruction set with other members of the MCS
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mcs-96 instruction set 8XC196KC Users manual register file 8XC196KD users manual mcs96 instruction set mcs 96 programming

80C196KC instruction set

Abstract: 80C196KC 8xC196KC Commercial Application Specification Update November 2001 Notice: The 8xC196KC may , incompatibilities arising from future changes to them. The 8xC196KC may contain design defects or errors known as , *Other brands and names are the property of their respective owners. 8xC196KC Commercial Application , 40 8xC196KC Commercial Application Specification Update 3 Revision History This , 8XC196KC and 8E196KC devices. Date Version Description 11/20/01 008 Added Erratum 35. 2
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80C196KC 80C196KC guide 80C196KC 270704 87C196KC 80C196KC application MCS-96 "evaluation board" Rev. 3.1 C196KC

80C196KC

Abstract: 80C196KC instruction set 8xC196KC Commercial Application Specification Update February 2001 Notice: The 8xC196KC may , incompatibilities arising from future changes to them. The 8xC196KC may contain design defects or errors known as , *Other brands and names are the property of their respective owners. 8xC196KC Commercial Application , 40 8xC196KC Commercial Application Specification Update 3 Revision History This , 8XC196KC and 8E196KC devices. Date Version 2/14/01 007 Description Added Documentation Change
Intel
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80C196KC user manual 80C196KC users guide 87C196kc users guide 80C196KC users guide 270704 272238-001 80C196KC circuit

80C196Kc

Abstract: 270646 8XC196KC SPECIFICATION UPDATE Release Date: January, 1999 Notice: The 8XC196KC microcontroller , whatsoever for conflicts or incompatibilities arising from future changes to them. The 8XC196KC , the property of their respective owners. January, 1999 272834-005 8XC196KC SPECIFICATION , .42 272834-005 January, 1999 iii 8XC196KC SPECIFICATION UPDATE REVISION HISTORY This , 8XC196KC and 8E196KC devices. Rev. Date Version 07/01/96 001 11/13/96 002 03/12/97
Intel
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270646 A4355-01 p648 272238 8XC196KC user manual 8XC196KC instructions

80C196KC users guide

Abstract: 80C196KC 8XC196KC SPECIFICATION UPDATE Release Date: May, 1997 Order Number: 272834-004 The 8XC196KC , 8XC196KC's behavior to deviate from published specifications are documented in this specification update , 708-296-9333 Copyright © 1996, INTEL CORPORATION May, 1997 272834-004 8XC196KC SPECIFICATION UPDATE , .39 272834-004 May, 1997 iii 8XC196KC SPECIFICATION UPDATE REVISION HISTORY This , 8XC196KC and 8E196KC devices. Rev. Date Version 07/01/96 001 11/13/96 002 03/12/97 003
Intel
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8XC196KC/KD complete users manual 74HC14 oscillator application note ApBUILDER 8XC196KC/kd users manual

80C196KC

Abstract: 80C196KC instruction set 8XC196KC SPECIFICATION UPDATE Release Date: November, 1996 Order Number: 272834-002 The 8XC196KC may contain design defects or errors known as errata. Characterized errata that may cause the 8XC196KC's behavior to deviate from published specifications are documented in this specification update , 708-296-9333 Copyright © 1996, INTEL CORPORATION ii November, 1996 272834-002 8XC196KC , .39 272834-002 November, 1996 iii 8XC196KC SPECIFICATION UPDATE REVISION HISTORY
Intel
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87C196* End of Life 80C196KC FPO 272834 intel DOC intel 80C196kc instruction set 8XC196KC manual

mcs-96 instruction set

Abstract: 272238-001 .2-9 2.6.1. Overview of the MCS®-96 Instruction Instruction Instruction Set Differences , 8XC196KC/8XC196KD User's Manual 1992 Order Number: 272238-001 Intel. 8X196KC/KD USER , .1 -6 CHAPTER 2 INTRODUCTION TO THE 8XC196KC/KD 2.1. COMPARISON OF THE 8XC196KC AND
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196kd 8X196KC intel HSO rapidcad intel 8231 intel RapidCAD 8XC196KC/8XC196KD RMX/80

8XC196KC

Abstract: 8XC196KC chapter 5 interrupts configurations, two or more pins are set or cleared simultaneously. C-22 irrte1 © 8XC196KC/KD REGISTERS HSO Time , 8XC196KC/KD C Registers APPENDIX C 8XC196KC/KD REGISTERS This appendix provides reference information about the registers of the 8XC196KC/KD. Table C-l lists the modules and major components of the 8XC196KC/KD with their related configuration and status registers. Table C-2 lists the horizontal windows , . Table C-4 lists the interrupts of the 8XC196KC/KD, the vector locations for both normal and PTS
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80C196KB A0146 8067H IOPORT34 01E0H 0200H 0220H 0240H 0260H

8XC196KB

Abstract: 80c196kb-compatible (HSIO) operations. Though they share a common architecture and instruction set, there are a few design , the PTS globally. This is achieved by using the instruction EPTS to enable the PTS (set the PSE bit , . 12 7. PTS Control Blocks for 8XC196KC , . 1 Multiplexed Pin Assignment Differences Between the 8XC196KB and 8XC196KC . 2 3. Address Map Differences Between the 8XC196KB and 8XC196KC
Intel
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AP-754 8XC196KB16 8XC196KC20 80c196kb-compatible 8XC196KB Instruction Set intel 80C196kb 80C196Kb compatible

270646

Abstract: 8XC196KC instructions . 30 of 55 July, 1996 272834-001 8XC196KC SPECIFICATION UPDATE The FIFO_FULL bit, when set , 8XC196KC SPECIFICATION UPDATE Release Date: July, 1996 Order Number: 272834-001 The 8XC196KC , 8XC196KC's behavior to deviate from published specifications are documented in this specification update. 8XC196KC SPECIFICATION UPDATE Information in this document is provided in connection with Intel products , 8XC196KC may contain design defects or errors known as errata. Current characterized errata are available
Intel
Original
270704 8EC196K 8ec196kc MC3191 8xC196 8XC196kb/kc/kd programming support

8XC196KC instruction set

Abstract: 8XC196KC chapter 5 interrupts HLDA# signal :If set, execute /protected instruction ORB WSR,#80H EI /Enable hold requests :Enable , Interfacing with 13 External Memory CHAPTER 13 INTERFACING WITH EXTERNAL MEMORY The 8XC196KC , active, the pin acts as a standard input (not quasi-bidirectional). INST 0 Instruction Fetch. The signal is valid only during external memory read cycles. When high, INST indicates that an instruction is , , we recommend that location 2019H be loaded with 20H. Under these conditions, the 8XC196KC/KD will
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A0164-AO 74AC373 WRL 1323 8xc196kc memory internal AD8-AD15 AD8-15

register file

Abstract: 2019H space within the 8XC196KC and 8XC196KD. Both devices have 64 Kbytes of addressable memory space, most of , One-Time-Programmable Read-Only Memory (OTPROM, a version of EPROM) space as the 8XC196KC. 8XC196KC Addresses 8XC196KD , . A0024-B0 Figure 4-1. Top-Level Memory Map 4-1 Intel. MEMORY PARTITIONS Table 4-1 compares the 8XC196KC , Addresses Description 8XC196KC Address Range 8XC196KD Address Range Hexadecimal Decimal Hexadecimal , Register File are always assigned to external memory or I/O (see Figure 4-1 or Table 4-1). The 8XC196KC/KD
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0A000H-0FFFFH 8XC196KC chapter 4 memory partitions memory interface 8255 0H17H 8216 INTEL 40956 8xC196KC index 6000H 0A000H 2080H 207FH 2000H 6000H-0FFFFH

8XC196KC

Abstract: 8XC196KC instruction set Special Operating 12 Modes CHAPTER 12 SPECIAL OPERATING MODES The 8XC196KC/KD supports three , . Entering Idle Mode To enter Idle mode, execute the IDLPD #1 instruction. 12.1.2. Exiting Idle Mode , completing the interrupt service routine, the CPU fetches and then executes the instruction that follows the IDLPD #1 instruction. 12-1 irrtel. SPECIAL OPERATING MODES 12.2. POWERDOWN MODE Powerdown mode places the 8XC196KC/KD into a very low power state. If Vcc is maintained, the Special Function Registers
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8XC196KC chapter 5 interrupts

Abstract: PCCB and decimal. (Chapter 4, "Memory Partitions," contains a complete set of 8XC196KC/KD memory maps and , execution. For this reason, an instruction located after 5FFAH (8XC196KC) or 9FFAH (8XC196KD) may not access , 8XC196KC/KD contains One-Time-Programmable Read-Only Memory (OTPROM), a version of EPROM. The 8XC196KC has , . PROGRAMMING MODES The 8XC196KC/KD supports three methods of programming the OTPROM program memory: Auto , 8XC196KC/KD to program itself from an external EPROM, without a specialized programmer. This mode allows
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PCCB a0156 intel 8216 2000H-5FFFH 2000H-9FFFH

MCS-96 architecture overview

Abstract: MCS-96 8XC196KC/KD," provides an overview of the MCS-96 instruction set. It discusses differences between the 8XC196KC/KD instruction set and that of the 8096BH and offers guidelines for program development. Appendix A provides reference information for the 8XC196KC/KD instruction set. It includes descriptions of the instructions, hexadecimal opcodes, instruction lengths, execution times, and the relationships , any type. The following data types are available on the 8XC196KC/KD: â'¢ BIT â'¢ BYTE â
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PLM-96 mcs-96 software mcs96 MCS-96 development 80c196KC programmers reference MCS-51

8XC196KC/KD

Abstract: 8XC196KC instructions APPENDIX C 8XC196KC/KD REGISTERS This appendix provides reference information about the registers of the 8XC196KC/KD. Table C-l lists the modules and major components of the 8XC196KC/KD with their , interrupts of the 8XC196KC/KD, the vector locations for both normal and PTS interrupt vectors, and interrupt , ZERO_REG C-1 4fl2bl75 Zero 3 Tb 8XC196KC/KD REGISTERS Table C-2. Special Function Register , i 8XC196KC/KD REGISTERS Table C-2. Special Function Register (SFR) HWindows (Continued) Hex
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0300H 0320H 0340H 0360H 0380H 03A0H

AP-125

Abstract: 8XC196KC chapter 5 interrupts the Reset (RST) Instruction The RST instruction (opcode FFH) resets the 8XC196KC/KD by pulling RESET , Minimum Hardware il Considerations CHAPTER 11 MINIMUM HARDWARE CONSIDERATIONS The 8XC196KC/KD , 8XC196KC/KD flows through several pins. Vcc supplies the positive voltage to the digital portion of the , .5-P2.7 P2.1-P2.4 P2.0 P0.0-P0.7 ANGND HSI.0-HSI.3 HSO.O-HSO.3 P1.0-P1.7 AD0-AD15 8XC196KC/KD VCC y NC â'" NC â'" NC I y 4.7 llF NC = No Connection A0123-B0 Figure 11-1. 8XC196KC/KD
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kd 116 transistor A0030-D0 0000H

8XC196KC chapter 5 interrupts

Abstract: 8XC196KC/KD microcontroller interrupt before executing the next instruction. An internal peripheral, an external signal, or an instruction can request an interrupt. In the simplest case, the 8XC196KC/KD receives the request, performs the , interrupt programming and control. 5.1. INTERRUPT PROCESSING The 8XC196KC/KD provides two interrupt , stack or the PSW, and it allows normal instruction flow to continue. For these reasons, the PTS can service an interrupt in the time required to execute a single instruction. The PTS operates in five
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8XC196KC/KD microcontroller
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