NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Catalog Datasheet Results | Type | Document Tags |
| Abstract: help ensure signal integrity at multi-gigabit speeds. TX FIFO 8b10b Mux TX ASIC FIFO 8b10b Mux TX ASIC FIFO I/F Mux 8b10b TX ASIC I/F FIFO 8b10b Mux TX ASIC FIFO I/F 8b10b Mux TX I/F ASIC FIFO 8b10b Mux TX I/F FIFO 8b10b Mux TXASIC ASIC I/F Mux 8b10b ASIC I/F , /O Popular I/O standard for flexible ASIC design Adjustable Pre-Emphasis on Serial Outputs , , 10, or 20 bit/Lane ASIC Interface (10-bit mode) 4, 8, or 16 bit/Lane ASIC Interface (8-bit/10-bit ... | Original |
2 pages, |
Velio Velio Communications VC1003 8B10B in serial communication 8B10B asic 10B8B 8B10B ic datasheet abstract |
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| Abstract: TX TX ASIC FIFO FIFO FIFO TX I/F TXASIC ASIC I/F ASIC I/F I/F 8b10b , Inter-Symbol Interference (ISI), and help ensure signal integrity at multi-gigabit speeds. 8b10b Mux Mux 8b10b 8b10b Mux Mux Programmable Pre-Emphasis FIFO FIFO FIFO FIFO RX RX ASIC RX ASIC , /O Popular I/O standard for flexible ASIC design Adjustable Pre-Emphasis on Serial Outputs , User-selectable 8 or 10 bit/Lane ASIC Interface Multiple bit/Lane modes support 8b/10b and SONET data streams ... | Original |
2 pages, |
VC1013 8B10B in serial communication 8B10B asic Velio datasheet abstract |
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| Abstract: Auto-Negotiation process support for information data exchange with a link partner 8B-10B Data Encoder/Decoder , The MAC-1G PCS has been developed for reuse in ASIC and FPGA implementations. The design is strictly , /deencapsulation Auto Negotiation Possibility for FPGA implementation with 8B-10B Data Encoder/Decoder , in a variety of technologies. The following is a sample result using optimization for speed. ASIC , ASIC implementations. The following options may be ordered according to the user's requirements ... | Original |
3 pages, |
MAC-1G FF1152 1000BASE-X RTL code for ethernet datasheet abstract |
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| Abstract: ISSP/150 ISSP/150 nm ASIC Technology ISSP1 - High-Speed Interface Family Product Letter , ) family, is a new class of ASIC device that features built-in, highspeed Serializer/Deserializer (SerDes , takes to design a complex ASIC is becoming longer all the time, due to the need to insert and verify , Cell-Based ASIC 10K - 100K ISSP 100 - 1K FPGA Life Cycle Product Features Features Metal , SRAM Embedded Clock SRAM Test Circuits BSCAN Multi-SCAN BIST TestBus 8B10B FIFO ... | Original |
6 pages, |
Cell-based ASIC 8B10B nec 928 8B10B asic a1698 ISSP/150 ISSP/150 abstract |
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| Abstract: Integrated Circuits (ASIC) and FPGA with Embedded high speed transceivers. This paper outlines some of the , interface to either an ASIC or FPGA for data processing, so as mainstream ASIC or FPGA embraces the , highlighted above. ASIC for high speed design ASIC has generally been viewed as a good single chip solution for high speed design. ASIC allows the user to fully customize the design to meet their , around the transceiver for a particular application or protocol. ASIC enables the user to develop a full ... | Original |
11 pages, |
stub backplane Layout power supply AN249 8B10B 84HP GETEK FR4 datasheet abstract |
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| Abstract: ASIC - including higher-level functions ยท Meets IEEE 802.3z and VSIA's specification for a , a 1 Gbps Ethernet Media Access Controller (MAC) for incorporation in a customer's own ASIC design. , supporting I / O functions are provided by the 8B10B Assembler / Dis-assembler blocks. On the system side , (as shown in the adjacent diagram). The sub-modules can be 8B10B Assembler/ Dis-assembler blocks ... | Original |
2 pages, |
8B10B datasheet abstract |
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| Abstract: Auto-Negotiation process support for information data exchange with a link partner 8B-10B Data Encoder/Decoder , The MAC-1G PCS has been developed for reuse in ASIC and FPGA implementations. The design is strictly , /deencapsulation Auto Negotiation Possibility for FPGA implementation with 8B-10B Data Encoder/Decoder , the core is delivered as HDL source code for ASIC implementations. The following options may be ... | Original |
3 pages, |
FF1152 1000BASE-X datasheet abstract |
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| Abstract: Auto-Negotiation process support for information data exchange with a link partner 8B-10B Data Encoder/Decoder , (STA). The MAC-1G PCS has been developed for reuse in ASIC and FPGA implementations. The design is , /deencapsulation Auto Negotiation Possibility for FPGA implementation with 8B-10B Data Encoder/Decoder , enable/disable Typically the megafunction is delivered as HDL source code for ASIC implementations. ... | Original |
3 pages, |
FF1152 EP3C20 1000BASE-X datasheet abstract |
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| Abstract: logic, called flexiPCS, which is implemented in ASIC technology. These embedded cores are integrated , rich and programmable the block is, supporting packet-based 8b10b and SONET-based protocols as well as , The ASIC portion of the LatticeSC offers performance and power advantages for the "fixed" portion of , well suited for a programmable platform that combines high performance, low power embedded ASIC , Lattice Semiconductor also offers a family of devices that, when coupled with available embedded ASIC and ... | Original |
18 pages, |
obsai datasheet abstract |
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| Abstract: BCM8228 BCM8228 Application Diagram BCM8228 BCM8228 Optical Module Optical Module BCM8228 BCM8228 Framer or ASIC Framer or ASIC BCM8228 BCM8228 Optical Module Optical Module BCM8228 BCM8228 OVERVIEW RCK4O Div4 , par Div 4 ser to par Div 10 8b10b Error Detect The BCM8228 BCM8228 VariRateTM device is a highly ... | Original |
2 pages, |
STM-16 BCM8228 BCM8228 abstract |
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| Abstract | Saved from | Date Saved | File Size | Type | Download |
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| ATM, PPP, 8b10b, HDLC, SDLC, TCP/IP, UTOPIA (Level I & II), Ethernet, PCI, VME Wireless structure, implemented in a Xilinx Virtex 300. Design included 8b10b encoding, packet and frame system design, chip and board specification, FPGA and ASIC design and verification, evaluation board integration testing. Our specialty is FPGA and ASIC development and we provide a full turnkey www.datasheetarchive.com/files/xilinx/docs/rp00027/rp0271d.htm |
Xilinx | 06/03/2000 | 9.75 Kb | HTM | rp0271d.htm |
| optionally encoded using the standard 8B/10B encoder, serialized, and sent out on the differential CML, XAUI of the sync pattern, and de-serializes the data. The data is then optionally 8B/10B decoded and fed , XGMII, and MDC/MDIO interfaces 8B/10B Encoder/Decoder per channel with selectable parallel input source-centered or source synchronous timing formats for ASIC-friendly timing. If the Built www.datasheetarchive.com/files/intersil/device_pages/device_bbt3420.html |
Intersil | 07/09/2006 | 20.64 Kb | HTML | device_bbt3420.html |
| for low power operation Interfaces to back plane, copper cables or optical converters On Chip 8B/10B encoding/decoding, Comma and synch On-chip PLL provides clock synthesis from low speed for CMOS ASICs > Breakthrough CMOS Transceiver Technology from TI Boosts Data www.datasheetarchive.com/files/texas-instruments/data/www.ti.com/sc/docs/products/msp/intrface/serdes/2p5gig/index.htm |
Texas Instruments | 18/01/2000 | 8.53 Kb | HTM | index.htm |
| for low power operation Interfaces to back plane, copper cables or optical converters On Chip 8B/10B encoding/decoding, Comma and synch On-chip PLL provides clock synthesis from low speed for CMOS ASICs > Breakthrough CMOS Transceiver Technology from TI Boosts Data www.datasheetarchive.com/files/texas-instruments/data/wwwti~1.com/sc/docs/products/msp/intrface/serdes/2p5gig/index.htm |
Texas Instruments | 17/01/2000 | 8.53 Kb | HTM | index.htm |
| programmable through a register accessible via the JTAG port. The device also includes as an option the 8b10b an embeddable macrocell in SGS-THOMSON's 0.35um ASIC library and design flow, so it can be integated www.datasheetarchive.com/files/stmicroelectronics/stonline/press/news/k292p-v1.htm |
STMicroelectronics | 14/06/1999 | 2.93 Kb | HTM | k292p-v1.htm |
| programmable through a register accessible via the JTAG port. The device also includes as an option the 8b10b an embeddable macrocell in SGS-THOMSON's 0.35um ASIC library and design flow, so it can be integated www.datasheetarchive.com/files/stmicroelectronics/stonline/press/news/year1998/k292p-v1.htm |
STMicroelectronics | 31/05/2000 | 2.96 Kb | HTM | k292p-v1.htm |
| JTAG port. The device also includes as an option the 8b10b encoding mechanism specified for the -THOMSON's 0.35um ASIC library and design flow, so it can be integated with other functions for customers www.datasheetarchive.com/files/stmicroelectronics/stonline/press/news/year1998/k292p.htm |
STMicroelectronics | 20/10/2000 | 3.01 Kb | HTM | k292p.htm |
| programmable through a register accessible via the JTAG port. The device also includes as an option the 8b10b an embeddable macrocell in SGS-THOMSON's 0.35um ASIC library and design flow, so it can be integated www.datasheetarchive.com/files/stmicroelectronics/stonline/press/news/k292p.htm |
STMicroelectronics | 18/03/1998 | 2.88 Kb | HTM | k292p.htm |
| includes as an option the 8b10b encoding mechanism specified for the Physical Coding Sublayer (PCS .35u CB45000 CB45000 CB45000 CB45000 ASIC technology for super-integrated applications . Product samples are available 1394 PHY port is also available as an embeddable microcell in SGS-THOMSON's 0.35um ASIC library and -THOMSON's 0.35um ASIC library and design flow, so it can be integated with other functions for customers Ethernet SerDes is also available as an embeddable macrocell in ST's 0.35um ASIC library and design flow www.datasheetarchive.com/files/stmicroelectronics/stonline/prodpres/spd/spd-v1.htm |
STMicroelectronics | 20/10/2000 | 11 Kb | HTM | spd-v1.htm |
| option the 8b10b encoding mechanism specified for the Physical Coding Sublayer (PCS). The device offer these hi-speed serial links as both standard products and macrocells in 0.35u CB45000 CB45000 CB45000 CB45000 ASIC -THOMSON's 0.35um ASIC library and design flow, so it can be integrated with other functions for customers -THOMSON's 0.35um ASIC library and design flow, so it can be integated with other functions for customers Des is also available as an embeddable macrocell in ST's 0.35um ASIC library and design flow, so it www.datasheetarchive.com/files/stmicroelectronics/stonline/prodpres/spd/spd-v2.htm |
STMicroelectronics | 14/06/1999 | 10.74 Kb | HTM | spd-v2.htm |