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EL5420CRZ-T7A Intersil Corporation EL5420CRZ PB-FREE12 MHZ QUAD, RAIL TO RAIL INPUT-OUTPUT OP A ri Buy
BSP61 T/R NXP Semiconductors PNP Darlington transistors - Complement: BSP51 ; fT min: 200 typ. MHz; hFE max:>2000 ; hFE min: 2000 ; IC max: 500 mA; Polarity: PNP ; Ptot max: 1250 mW; toff: 1500 ns; VCES max: 60 V ri Buy
BSP60 T/R NXP Semiconductors PNP Darlington transistors - Complement: BSP50 ; fT min: 200 typ. MHz; hFE max:>2000 ; hFE min: 2000 ; IC max: 500 mA; Polarity: PNP ; Ptot max: 1250 mW; toff: 1500 ns; VCES max: 45 V ri Buy

8B10B MHz

Catalog Datasheet Results Type PDF Document Tags
Abstract: v 2. 0 8b10b Macro P r o d uc t S u m m a r y · Gigabit Ethernet 8b10b Function · 125 MHz , the 8b10b macro. G e n er a l D e sc r i p ti on The 8b10b macro implements the function for the physical coding sublayer for Gigabit Ethernet as defined in the IEEE 802.3z specification. The 8b10b is a , 8b10b macro is designed to work with a variety of standard transceiver devices. A set of generic , describing the use of the 8b10b macro is shown in Figure 1. The 8b10b macro provides a user interface and a ... Original
datasheet

12 pages,
110.28 Kb

sx08a CLK125 A54SX32A A54SX16A A54SX08A 8B10B MHz A54SX-A 3b4b A54SXA datasheet abstract
datasheet frame
Abstract: CODEC, 8B10B CODEC, 3.125G SERDES, CDR, and PLL. These functions provide data conversion between the , serial interface service Internal TX and RX elastic FIFOs 8B10B and 64B66B 64B66B encoders and decoders Flexible clock scheme; 644.53-MHz VCXO or external reference clocks On-chip phase-locked loop (PLL) providing clock synthesis from 156.25-MHz or 644.53-MHz reference clock MDIO interface Lock detect Comma detection ... Original
datasheet

2 pages,
64.75 Kb

M69850 10G serdes IEEE802 64B66B 8B10B 3125G M69850 abstract
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Abstract: Ethernet MACs. XGMII is a 156 MHz double data rate, parallel short-reach (typically less than 2 inches , self-timed 8b10b encoded serial lanes, each operating at 3.125 Gbits/s. The IP core from Lattice , the ORT82G5 ORT82G5 includes: · Eight channels of 3.125 Gbps serializer/deserializer with 8b10b encoding , /s per lane with a 156.25 MHz clock. The data and control lines are sampled on both the rising and , Figure 2, is the data path from the XAUI to the XGMII interface. It maps 8b10b decoded XAUI data to ... Original
datasheet

4 pages,
147.15 Kb

ORT82G5 8B10B 8B10B MHz XGXS ORT82G5 abstract
datasheet frame
Abstract: 8B10B Encoder/Decoder MegaCore Function User Guide 101 Innovation Drive San Jose, CA 95134 , December 2002 Copyright 8B10B Encoder/Decoder MegaCore Function User Guide Copyright © 2002 , User Guide This user guide provides comprehensive information about the Altera® 8B10B Encoder , Contact Altera 8B10B Encoder/Decoder MegaCore Function User Guide For the most up-to-date , representative. Altera Corporation About this User Guide Typographic Conventions 8B10B Encoder ... Original
datasheet

32 pages,
238.56 Kb

8B10B Altera 8b10b EP1C20F400C6 EP1S25F780C5 EP20K keyboard encoder sun verilog code for fibre channel verilog hdl code for encoder encoder verilog coding 8B10B ansi encoder 8B10B abstract
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Abstract: designs with clock speeds above 100 MHz. Figure 1. Design Time Turnaround (RTL to Prototype) ISSP , System clock speeds up to 200 MHz · 1.5V core voltage · Low power dissipation · Complex multi-gate , Kb SRAM SRAM FIFO SRAM 8B10B FIFO FIFO Complex Multi Gates Test Circuits BSCAN Multi-SCAN BIST TestBus FIFO FIFO FIFO FIFO SerDes Core 8B10B Clock SerDes Core Embedded , the 8B10B firm core. Additional gates will be available if the 8B10B firm core is not used. ... Original
datasheet

6 pages,
364.73 Kb

datasheet abstract
datasheet frame
Abstract: 8b10b Encoder/Decoder MegaCore Function (ED8B10B ED8B10B) July 2001; ver. 1.01 Introduction Data , The Altera® 8b10b Encoder/Decoder MegaCore® Function (ED8B10B ED8B10B) is a compact, high performance core capable of encoding and decoding at Gigabit Ethernet rates (125 MHz: 1 Gbps). The ED8B10B ED8B10B is optimized , group F, G, H. Altera Corporation A-DS-IPED8B10B-1.01 1 8b10b Encoder/Decoder MegaCore , group f, g, h, j. Figure 1. 8b10b Conversion 7 6 5 4 3 2 1 0 H G F ... Original
datasheet

11 pages,
166.12 Kb

verilog code for fibre channel EPF10K30ETC144-1 ED8B10B encoder verilog coding 8B10B ansi encoder ED8B10B abstract
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Abstract: 8b10b Encoder/Decoder MegaCore Function (ED8B10B ED8B10B) November 2001; ver. 1.02 Introduction , The Altera® 8b10b Encoder/Decoder MegaCore® Function (ED8B10B ED8B10B) is a compact, high performance core capable of encoding and decoding at Gigabit Ethernet rates (125 MHz: 1 Gbps). The ED8B10B ED8B10B is optimized , , and the four-bit group f, g, h, j. Altera Corporation A-DS-IPED8B10B-1.02 1 8b10b Encoder/Decoder MegaCore Function (ED8B10B ED8B10B) Data Sheet Figure 1. 8b10b Conversion 7 6 5 4 3 2 ... Original
datasheet

11 pages,
464.22 Kb

EPF10K30ETC144-1 ED8B10B ED8B10B abstract
datasheet frame
Abstract: /10B Decoder (4) Rx Working 2.488 Mbps or 4 x 622 Mbps SONET Scrambled or 4 x 622 Mbps / 8B10B , Protect 2.488 Mbps or 4 x 622 Mbps SONET Scrambled or 4 x 622 Mbps / 8B10B Encoded SONET/SDH Time , Scrambled or 4 x 622 Mbps / 8B10B Encoded 8B/10B 8B/10B Encoder (4) Tx Working 2.488 Mbps or 4 x 622 Mbps SONET Scrambled or 4 x 622 Mbps / 8B10B Encoded Transmit Tail Trace Processor (4 , Ethernet Output Buffer (2) · Provides working and protect 4 x 777.6 MHz LVDS Serial TelecomBus, 4 x ... Original
datasheet

2 pages,
35.65 Kb

PM5372 PM5315 aly 3c 8B10B 896-pin pmc PM5397 gigabit ethernet over sdh 8b/10b scrambler 896-pin PM5397 abstract
datasheet frame
Abstract: DIAGRAM · Provides working and protect 4 x 777.6 MHz LVDS Serial TelecomBus, 4 x 622 Mbps LVDS SONET , Descrambler Rx Protect 2.488 Mbps or 4 x 622 Mbps SONET Scrambled or 4 x 622 Mbps / 8B10B Encoded 8B/10B 8B/10B Decoder (4) Rx Working 2.488 Mbps or 4 x 622 Mbps SONET Scrambled or 4 x 622 Mbps / 8B10B , Scrambled or 4 x 622 Mbps / 8B10B Encoded 8B/10B 8B/10B Encoder (4) Tx Working 2.488 Mbps or 4 x 622 Mbps SONET Scrambled or 4 x 622 Mbps / 8B10B Encoded Transmit Tail Trace Processor (4 ... Original
datasheet

2 pages,
34.78 Kb

PM5397 PM5315 arrow 2488 8B10B MHz 8B10B gigabit ethernet over sdh PM5397 abstract
datasheet frame
Abstract: I Transm it Clock Input. This 125 MHZ input clock is used by the 8B10B PCS Section and generates the , 8B10B Encoder/Decoder (MAC + 8B10B PCS) D ecem ber 1, 1997 DATA SHEET Note: Check for latest Data , 8B10B PCS Data Rate -1000 Mbps 32/16-Bit System Interface To External System Bus - 4 Gbps Bandwith , along with the 8B10B Encoder/Decoder (also known as 8B10B PCS), which is the digital coding block for , FIFO's, 32-bit System Interface, 8B10B encoder/ decoder, 10-bit P H Y Interface, and a 16-bit Register ... OCR Scan
datasheet

9 pages,
501.72 Kb

transmitter ARK 200 datasheet abstract
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Datasheet Content (non pdf)

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www.datasheetarchive.com/download/8809555-996045ZC/xapp762.zip (transceiver.v)
Xilinx 12/11/2004 2970.58 Kb ZIP xapp762.zip
ATM, PPP, 8b10b, HDLC, SDLC, TCP/IP, UTOPIA (Level I & II), Ethernet, PCI, VME Wireless - 20-bit datapaths at 125 MHz) for a combined 5 gigabit stream, carrying a proprietary frame structure, implemented in a Xilinx Virtex 300. Design included 8b10b encoding, packet and frame monitoring. Turnkey
www.datasheetarchive.com/files/xilinx/docs/wcd0000e/wcd00e5c-v1.htm
Xilinx 04/06/1999 9.82 Kb HTM wcd00e5c-v1.htm
ATM, PPP, 8b10b, HDLC, SDLC, TCP/IP, UTOPIA (Level I & II), Ethernet, PCI, VME Wireless - 20-bit datapaths at 125 MHz) for a combined 5 gigabit stream, carrying a proprietary frame structure, implemented in a Xilinx Virtex 300. Design included 8b10b encoding, packet and frame monitoring. Turnkey
www.datasheetarchive.com/files/xilinx/docs/rp00027/rp0271d.htm
Xilinx 06/03/2000 9.75 Kb HTM rp0271d.htm
EN_CDET [106.25 MHz] COM_DET transmitter T C K T R S T M S T D I T D O R S A T T E 8b10b encoding function is enabled. A loop-back-mode signal EWRAP is provided allowing internal dynamic , if the REFCLK used is 106.25 MHz, then the incoming data serial signaling rate must be 1.0625 + Typ Max Units F ref =1/T ref Reference clock frequency 100 106.25 110 MHz F tol Frequency guaranteed to be glitch free. 53.125 MHz Trbc1 RBC[1] frequency 1 53.125 MHz Trbc_skew RBC skew 8.9 -
www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/5990.htm
STMicroelectronics 20/10/2000 42.21 Kb HTM 5990.htm
[106.25 MHz] COM_DET transmitter T C K T R S T M S T D I T D O R S the code-group on the TX+, TX- pair, is 17.4 ns with an extra 9.4 ns if the 8b10b encoding function 106.25 MHz, then the incoming data serial signaling rate must be 1.0625 + 0.0001 Gb/s. The MHz F tol Frequency tolerance (dispersion between REFCLK of transmitter and receiver chips glitch free. 53.125 MHz Trbc1 RBC[1] frequency 1 53.125 MHz Trbc_skew RBC skew 8.9 - 9.9 ns
www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/5990-v3.htm
STMicroelectronics 25/05/2000 40.25 Kb HTM 5990-v3.htm
] REFCLK 10 RBC[0:1] RX[0:9] 10 2 EWRAP EN_CDET [106.25 MHz] COM_DET transmitter T C K T R S T M S T D I T 8b10b encoding function is enabled. A loop-back-mode signal EWRAP is provided allowing internal dynamic For FC106 FC106 FC106 FC106 Revision 1.2 11/32 September 98 example, if the REFCLK used is 106.25 MHz, then the MHz F tol Frequency tolerance (dispersion between REFCLK of transmitter and receiver chips) 100 - + 53.125 MHz Trbc1 RBC[1] frequency 1 53.125 MHz Trbc_skew RBC skew 8.9 - 9.9 ns RBC[0,1] Tr, Tf Receive
www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/5990-v1.htm
STMicroelectronics 02/04/1999 38.44 Kb HTM 5990-v1.htm
] REFCLK 10 RBC[0:1] RX[0:9] 10 2 EWRAP EN_CDET [106.25 MHz] COM_DET transmitter T C K T R S T M S T D I T 8b10b encoding function is enabled. A loop-back-mode signal EWRAP is provided allowing internal dynamic For FC106 FC106 FC106 FC106 Revision 1.2 11/32 September 98 example, if the REFCLK used is 106.25 MHz, then the MHz F tol Frequency tolerance (dispersion between REFCLK of transmitter and receiver chips) 100 - + 53.125 MHz Trbc1 RBC[1] frequency 1 53.125 MHz Trbc_skew RBC skew 8.9 - 9.9 ns RBC[0,1] Tr, Tf Receive
www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/5990-v2.htm
STMicroelectronics 14/06/1999 38.4 Kb HTM 5990-v2.htm