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8B10B MHz

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: v 2. 0 8b10b Macro P r o d uc t S u m m a r y · Gigabit Ethernet 8b10b Function · 125 MHz , the 8b10b macro. G e n er a l D e sc r i p ti on The 8b10b macro implements the function for the physical coding sublayer for Gigabit Ethernet as defined in the IEEE 802.3z specification. The 8b10b is a , 8b10b macro is designed to work with a variety of standard transceiver devices. A set of generic , describing the use of the 8b10b macro is shown in Figure 1. The 8b10b macro provides a user interface and a ... Actel
Original
datasheet

12 pages,
110.28 Kb

sx08a CLK125 A54SX32A A54SX16A A54SX08A 8B10B MHz A54SX-A 3b4b A54SXA TEXT
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Abstract: 8B10B Encoder/Decoder MegaCore Function User Guide 101 Innovation Drive San Jose, CA 95134 , December 2002 Copyright 8B10B Encoder/Decoder MegaCore Function User Guide Copyright © 2002 , User Guide This user guide provides comprehensive information about the Altera® 8B10B Encoder , 8B10B Encoder/Decoder MegaCore Function User Guide For the most up-to-date information about Altera , Corporation About this User Guide Typographic Conventions 8B10B Encoder/Decoder MegaCore Function ... Altera
Original
datasheet

32 pages,
238.56 Kb

3 to 8 line decoder vhdl IEEE format 8B10B EP1C20F400C6 EP1S25F780C5 EP20K keyboard encoder sun verilog code for fibre channel 6AF7 Altera 8b10b verilog hdl code for encoder encoder verilog coding 8B10B ansi encoder TEXT
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Abstract: Ethernet MACs. XGMII is a 156 MHz double data rate, parallel short-reach (typically less than 2 inches , self-timed 8b10b encoded serial lanes, each operating at 3.125 Gbits/s. The IP core from Lattice , the ORT82G5 ORT82G5 includes: · Eight channels of 3.125 Gbps serializer/deserializer with 8b10b encoding , per lane with a 156.25 MHz clock. The data and control lines are sampled on both the rising and , , is the data path from the XAUI to the XGMII interface. It maps 8b10b decoded XAUI data to XGMII data ... Lattice Semiconductor
Original
datasheet

4 pages,
147.15 Kb

ORT82G5 8B10B 8B10B MHz XGXS TEXT
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Abstract: 8B10B Encoder/Decoder MegaCore Function User Guide 8B10B Encoder/Decoder MegaCore Function User , products or services. 8B10B Encoder/Decoder MegaCore Function User Guide May 2011 Altera Corporation , 8B10B Encoder /Decoder Walkthrough . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , . . . . . . . . . . . . Info­2 May 2011 Altera Corporation 8B10B Encoder/Decoder MegaCore Function User Guide iv Contents 8B10B Encoder/Decoder MegaCore Function User Guide May 2011 ... Altera
Original
datasheet

32 pages,
873.92 Kb

EP3SE110F UG-IPED8B10B-1 8B10B TEXT
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Abstract: 8B10B Encoder/Decoder MegaCore Function User Guide 101 Innovation Drive San Jose, CA 95134 , . . . . . . . . . . . . . . . . . . . . . 2­1 8B10B Encoder /Decoder Walkthrough . . . . . . . . . , . Info­ii © November 2009 Altera Corporation 8B10B Encoder/Decoder MegaCore Function User Guide Preliminary iv Contents 8B10B Encoder/Decoder MegaCore Function User Guide , Table 1­1 provides information about this release of the Altera® 8B10B Encoder/Decoder MegaCore ... Altera
Original
datasheet

30 pages,
446.28 Kb

vhdl code for character display EP3C80F780C6 EP2S30F484C3 EP2C35F484C6 encoder/decoder 8B10B TEXT
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Abstract: 8b10b Encoder/Decoder MegaCore Function (ED8B10B ED8B10B) November 2001; ver. 1.02 Introduction , . The Altera® 8b10b Encoder/Decoder MegaCore® Function (ED8B10B ED8B10B) is a compact, high performance core capable of encoding and decoding at Gigabit Ethernet rates (125 MHz: 1 Gbps). The ED8B10B ED8B10B is optimized , , and the four-bit group f, g, h, j. Altera Corporation A-DS-IPED8B10B-1.02 1 8b10b Encoder/Decoder MegaCore Function (ED8B10B ED8B10B) Data Sheet Figure 1. 8b10b Conversion 7 6 5 4 3 2 ... Altera
Original
datasheet

11 pages,
464.22 Kb

EPF10K30ETC144-1 ED8B10B 3624-4 equivalent TEXT
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Abstract: designs with clock speeds above 100 MHz. Figure 1. Design Time Turnaround (RTL to Prototype) ISSP , System clock speeds up to 200 MHz · 1.5V core voltage · Low power dissipation · Complex multi-gate , Kb SRAM SRAM FIFO SRAM 8B10B FIFO FIFO Complex Multi Gates Test Circuits BSCAN Multi-SCAN BIST TestBus FIFO FIFO FIFO FIFO SerDes Core 8B10B Clock SerDes Core Embedded , 8B10B firm core. Additional gates will be available if the 8B10B firm core is not used. High-Speed ... NEC
Original
datasheet

6 pages,
364.73 Kb

50944 aircraft logic gates TEXT
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Abstract: 8b10b Encoder/Decoder MegaCore Function (ED8B10B ED8B10B) July 2001; ver. 1.01 Introduction Data , . The Altera® 8b10b Encoder/Decoder MegaCore® Function (ED8B10B ED8B10B) is a compact, high performance core capable of encoding and decoding at Gigabit Ethernet rates (125 MHz: 1 Gbps). The ED8B10B ED8B10B is optimized , group F, G, H. Altera Corporation A-DS-IPED8B10B-1.01 1 8b10b Encoder/Decoder MegaCore , group f, g, h, j. Figure 1. 8b10b Conversion 7 6 5 4 3 2 1 0 H G F ... Altera
Original
datasheet

11 pages,
166.12 Kb

verilog code for fibre channel ED8B10B EPF10K30ETC144-1 encoder verilog coding 8B10B ansi encoder TEXT
datasheet frame
Abstract: with the 125 MHz 8B10B PCS clock whenever a full packet has been loaded into the FIFO (an EOF is , 2.10.3 RX Underflow 8B10B PCS 2.11.1 8B10B Encoder 2.11.2 8B10B Decoder 2.11.3 Start of Packet 2.11.4 End , Multicast Address Filter Map Receive Maximum Packet Size Selection 8B10B Coding Table 10B Defined Ordered , Sublayer) (8B10B PCS) for 1000 Mbits/s Gigabit Ethernet systems. The 8104 is functionally the same as the , · · Pin-compatible upgrade of 8100 Combined Ethernet MAC and 8B10B PCS 1000 Mbits/s data rate 64 ... LSI Logic
Original
datasheet

172 pages,
523.09 Kb

8B10B ansi encoder R14017 TEXT
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Abstract: media. s Combined Ethernet MAC and 8B10B PCS s Data Rate - 1000 Mbps s 64-Bit @ 66 Mhz Interface to , Clock Input. This 125 MHZ input clock is used by the 8B10B PCS Section and generates the 125 MHZ , Interface, 8B10B encoder/ decoder, 10-bit PHY Interface, and a 16-bit Register Interface. s Independent , Overflow 3.6.4 RX Underflow 2.0 Block Diagram 3.0 Functional Description 3.7 8B10B PCS 3.7.1 Transmit 3.7.2 Receive 3.7.3 8B10B Encoder 3.7.4 8B10B Decoder 3.7.5 Start of Packet 3.7.6 End Of ... LSI Logic
Original
datasheet

102 pages,
847.53 Kb

RXD14 8B10B 3156 00010001 sony rxd7 TEXT
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Archived Files

Abstract Saved from Date Saved File Size Type Download
/E1, Cable Modem ATM, PPP, 8b10b, HDLC, SDLC, TCP/IP, UTOPIA (Level I & II), Ethernet, PCI Design Dual 2.5 gigabit transmit stream (two 20-bit datapaths at 125 MHz) for a combined 5 included 8b10b encoding, packet and frame monitoring. Turnkey design (Dec/98 - Mar/99). Contact
/datasheets/files/xilinx/docs/rp00027/rp0271d.htm
Xilinx 06/03/2000 9.75 Kb HTM rp0271d.htm
No abstract text available
/download/2709085-996018ZC/xapp660.zip ()
Xilinx 10/02/2004 165.48 Kb ZIP xapp660.zip
No abstract text available
/download/23037380-996044ZC/xapp759.zip ()
Xilinx 26/04/2004 2752.08 Kb ZIP xapp759.zip
] REFCLK 10 RBC[0:1] RX[0:9] 10 2 EWRAP EN_CDET [106.25 MHz] COM_DET transmitter T C K T R S T M S T D I T 8b10b encoding function is enabled. A loop-back-mode signal EWRAP is provided allowing internal dynamic For FC106 FC106 Revision 1.2 11/32 September 98 example, if the REFCLK used is 106.25 MHz, then the incoming MHz F tol Frequency tolerance (dispersion between REFCLK of transmitter and receiver chips) 100 - + 53.125 MHz Trbc1 RBC[1] frequency 1 53.125 MHz Trbc_skew RBC skew 8.9 - 9.9 ns RBC[0,1] Tr, Tf Receive
/datasheets/files/stmicroelectronics/stonline/books/ascii/docs/5990-v2.htm
STMicroelectronics 14/06/1999 38.4 Kb HTM 5990-v2.htm
No abstract text available
/download/58955026-996027ZC/xapp683.zip ()
Xilinx 15/03/2004 67.57 Kb ZIP xapp683.zip
] REFCLK 10 RBC[0:1] RX[0:9] 10 2 EWRAP EN_CDET [106.25 MHz] COM_DET transmitter T C K T R S T M S T D I T 8b10b encoding function is enabled. A loop-back-mode signal EWRAP is provided allowing internal dynamic For FC106 FC106 Revision 1.2 11/32 September 98 example, if the REFCLK used is 106.25 MHz, then the incoming MHz F tol Frequency tolerance (dispersion between REFCLK of transmitter and receiver chips) 100 - + 53.125 MHz Trbc1 RBC[1] frequency 1 53.125 MHz Trbc_skew RBC skew 8.9 - 9.9 ns RBC[0,1] Tr, Tf Receive
/datasheets/files/stmicroelectronics/stonline/books/ascii/docs/5990-v1.htm
STMicroelectronics 02/04/1999 38.44 Kb HTM 5990-v1.htm
[0:1] RX[0:9] 10 2 EWRAP EN_CDET [106.25 MHz] COM_DET transmitter T C K T R S T M S T D I T D O R S A bit of the code-group on the TX+, TX- pair, is 17.4 ns with an extra 9.4 ns if the 8b10b encoding September 98 example, if the REFCLK used is 106.25 MHz, then the incoming data serial signaling rate must be MHz F tol Frequency tolerance (dispersion between REFCLK of transmitter and receiver chips) 100 - + 53.125 MHz Trbc1 RBC[1] frequency 1 53.125 MHz Trbc_skew RBC skew 8.9 - 9.9 ns RBC[0,1] Tr, Tf Receive
/datasheets/files/stmicroelectronics/stonline/books/ascii/docs/5990.htm
STMicroelectronics 20/10/2000 42.21 Kb HTM 5990.htm
] RX[0:9] 10 2 EWRAP EN_CDET [106.25 MHz] COM_DET transmitter T C K T R S T M S T D the TX+, TX- pair, is 17.4 ns with an extra 9.4 ns if the 8b10b encoding function is enabled. A For FC106 FC106 Revision 1.2 11/32 September 98 example, if the REFCLK used is 106.25 MHz, then the ref =1/T ref Reference clock frequency 100 106.25 110 MHz F tol Frequency tolerance (dispersion 53.125 MHz Trbc1 RBC[1] frequency 1 53.125 MHz Trbc_skew RBC skew 8.9 - 9.9 ns RBC[0,1] Tr, Tf
/datasheets/files/stmicroelectronics/stonline/books/ascii/docs/5990-v3.htm
STMicroelectronics 25/05/2000 40.25 Kb HTM 5990-v3.htm
No abstract text available
/download/8809555-996045ZC/xapp762.zip ()
Xilinx 12/11/2004 2970.58 Kb ZIP xapp762.zip
No abstract text available
/download/49538481-996041ZC/xapp710.zip ()
Xilinx 13/09/2004 102.73 Kb ZIP xapp710.zip