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8B10B MHz

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: v 2. 0 8b10b Macro P r o d uc t S u m m a r y · Gigabit Ethernet 8b10b Function · 125 MHz , the 8b10b macro. G e n er a l D e sc r i p ti on The 8b10b macro implements the function for the physical coding sublayer for Gigabit Ethernet as defined in the IEEE 802.3z specification. The 8b10b is a , 8b10b macro is designed to work with a variety of standard transceiver devices. A set of generic , describing the use of the 8b10b macro is shown in Figure 1. The 8b10b macro provides a user interface and a Actel
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A54SXA 3b4b A54SX-A A54SX08A A54SX16A A54SX32A
Abstract: 8B10B Encoder/Decoder MegaCore Function User Guide 101 Innovation Drive San Jose, CA 95134 , December 2002 Copyright 8B10B Encoder/Decoder MegaCore Function User Guide Copyright © 2002 , User Guide This user guide provides comprehensive information about the Altera® 8B10B Encoder , 8B10B Encoder/Decoder MegaCore Function User Guide For the most up-to-date information about Altera , Corporation About this User Guide Typographic Conventions 8B10B Encoder/Decoder MegaCore Function Altera
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8B10B ansi encoder encoder verilog coding verilog hdl code for encoder Altera 8b10b 6AF7 verilog code for fibre channel UG-IPED8B10B-
Abstract: Ethernet MACs. XGMII is a 156 MHz double data rate, parallel short-reach (typically less than 2 inches , self-timed 8b10b encoded serial lanes, each operating at 3.125 Gbits/s. The IP core from Lattice , the ORT82G5 includes: · Eight channels of 3.125 Gbps serializer/deserializer with 8b10b encoding , per lane with a 156.25 MHz clock. The data and control lines are sampled on both the rising and , , is the data path from the XAUI to the XGMII interface. It maps 8b10b decoded XAUI data to XGMII data Lattice Semiconductor
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XGXS
Abstract: 8B10B Encoder/Decoder MegaCore Function User Guide 8B10B Encoder/Decoder MegaCore Function User , products or services. 8B10B Encoder/Decoder MegaCore Function User Guide May 2011 Altera Corporation , 8B10B Encoder /Decoder Walkthrough . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , . . . . . . . . . . . . Info­2 May 2011 Altera Corporation 8B10B Encoder/Decoder MegaCore Function User Guide iv Contents 8B10B Encoder/Decoder MegaCore Function User Guide May 2011 Altera
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UG-IPED8B10B-1 EP3SE110F
Abstract: 8B10B Encoder/Decoder MegaCore Function User Guide 101 Innovation Drive San Jose, CA 95134 , . . . . . . . . . . . . . . . . . . . . . 2­1 8B10B Encoder /Decoder Walkthrough . . . . . . . . . , . Info­ii © November 2009 Altera Corporation 8B10B Encoder/Decoder MegaCore Function User Guide Preliminary iv Contents 8B10B Encoder/Decoder MegaCore Function User Guide , Table 1­1 provides information about this release of the Altera® 8B10B Encoder/Decoder MegaCore Altera
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encoder/decoder EP2C35F484C6 EP2S30F484C3 EP3C80F780C6 vhdl code for character display
Abstract: 8b10b Encoder/Decoder MegaCore Function (ED8B10B) November 2001; ver. 1.02 Introduction , . The Altera® 8b10b Encoder/Decoder MegaCore® Function (ED8B10B) is a compact, high performance core capable of encoding and decoding at Gigabit Ethernet rates (125 MHz: 1 Gbps). The ED8B10B is optimized , , and the four-bit group f, g, h, j. Altera Corporation A-DS-IPED8B10B-1.02 1 8b10b Encoder/Decoder MegaCore Function (ED8B10B) Data Sheet Figure 1. 8b10b Conversion 7 6 5 4 3 2 Altera
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3624-4 equivalent EPF10K30ETC144-1
Abstract: designs with clock speeds above 100 MHz. Figure 1. Design Time Turnaround (RTL to Prototype) ISSP , System clock speeds up to 200 MHz · 1.5V core voltage · Low power dissipation · Complex multi-gate , Kb SRAM SRAM FIFO SRAM 8B10B FIFO FIFO Complex Multi Gates Test Circuits BSCAN Multi-SCAN BIST TestBus FIFO FIFO FIFO FIFO SerDes Core 8B10B Clock SerDes Core Embedded , 8B10B firm core. Additional gates will be available if the 8B10B firm core is not used. High-Speed NEC
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aircraft logic gates 50944 W-0009
Abstract: 8b10b Encoder/Decoder MegaCore Function (ED8B10B) July 2001; ver. 1.01 Introduction Data , . The Altera® 8b10b Encoder/Decoder MegaCore® Function (ED8B10B) is a compact, high performance core capable of encoding and decoding at Gigabit Ethernet rates (125 MHz: 1 Gbps). The ED8B10B is optimized , group F, G, H. Altera Corporation A-DS-IPED8B10B-1.01 1 8b10b Encoder/Decoder MegaCore , group f, g, h, j. Figure 1. 8b10b Conversion 7 6 5 4 3 2 1 0 H G F Altera
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800-EPLD
Abstract: with the 125 MHz 8B10B PCS clock whenever a full packet has been loaded into the FIFO (an EOF is , 2.10.3 RX Underflow 8B10B PCS 2.11.1 8B10B Encoder 2.11.2 8B10B Decoder 2.11.3 Start of Packet 2.11.4 End , Multicast Address Filter Map Receive Maximum Packet Size Selection 8B10B Coding Table 10B Defined Ordered , Sublayer) (8B10B PCS) for 1000 Mbits/s Gigabit Ethernet systems. The 8104 is functionally the same as the , · · Pin-compatible upgrade of 8100 Combined Ethernet MAC and 8B10B PCS 1000 Mbits/s data rate 64 LSI Logic
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RXD29 D3318 216520-4 R14017 DB14-000123-02 D-85540 D-33181
Abstract: media. s Combined Ethernet MAC and 8B10B PCS s Data Rate - 1000 Mbps s 64-Bit @ 66 Mhz Interface to , Clock Input. This 125 MHZ input clock is used by the 8B10B PCS Section and generates the 125 MHZ , Interface, 8B10B encoder/ decoder, 10-bit PHY Interface, and a 16-bit Register Interface. s Independent , Overflow 3.6.4 RX Underflow 2.0 Block Diagram 3.0 Functional Description 3.7 8B10B PCS 3.7.1 Transmit 3.7.2 Receive 3.7.3 8B10B Encoder 3.7.4 8B10B Decoder 3.7.5 Start of Packet 3.7.6 End Of LSI Logic
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sony rxd7 w1p13 3156 00010001 RXD14 XMT 2315 MD400176/B
Abstract: Reference Clock (MHz) 15 - 312.5 15 - 312.5 x1 8b10b 1. For slower rates, the SERDES are , to 16 Channels of High-Speed SERDES ­ 150 Mbps to 3.2 Gbps for Generic 8b10b, 10-bit SERDES and 8 , other standards ­ Supports user-specified generic 8b10b mode ­ Out-of-band (OOB) signal interface for , 8b10b-based packet protocols ­ SERDES Only mode allows direct 8-bit or 10-bit interface to FPGA logic , Data Rate (Mbps) System Reference Clock (MHz) FPGA Clock (MHz) Number of General/Link Lattice Semiconductor
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TN1176 HD-SDI deserializer 16 bit parallel HD-SDI over sdh ECP3-17 CTC 880 QD00 QD004
Abstract: by the SERDES (Continued) Data Rate (Mbps) Generic 8b10b FPGA Clock (MHz) Number of , to 16 Channels of High-Speed SERDES ­ 150 Mbps to 3.2 Gbps for Generic 8b10b, 10-bit SERDES and 8 , other standards ­ Supports user-specified generic 8b10b mode ­ Out-of-band (OOB) signal interface for , 8b10b-based packet protocols ­ SERDES Only mode allows direct 8-bit or 10-bit interface to FPGA logic , Rate (Mbps) System Reference Clock (MHz) FPGA Clock (MHz) Number of General/Link Width Lattice Semiconductor
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vhdl code for stm-1 sequence CDRPLL serdes Buffer hd-SDI driver HB100 encoder 74175
Abstract: (MHz) sysHSI Macro Serial Data Rate (Mbps) Min. Max. V (HS/LS) Min. Max. CDRX_8B10B , Data Rate (Mbps) Parallel Data/Clk (MHz) SERDES without Encoding/Decoding 8B/10B 400 to , CDRX_8B10B 8B/10B CDR receive mode TX_8B10B 8B/10B transmit mode 8B10B HSLB_8B10B 8B/10B High Speed Loop Back mode 10B12B HSLB_10B12B 10B/12B High Speed Loop Back mode 8B10B , Alignment) CDRX_8B10B 11000001010011111010 K28.5, D21.4, D21.5, D21.5 (Idle Pattern)2 CDRX Lattice Semiconductor
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verilog code for lvds driver vhdl code for deserializer vhdl code for clock and data recovery vhdl code for lvds driver verilog DPLL vhdl code direct digital synthesizer TN1020 TN1000 1-800-LATTICE
Abstract: Stratix GX GXB Duplex Word Aligner Deserializer RX PLL J 8B10B Decoder Place , Altera Corporation 8B10B Decoder Serializer Stratix GX FPGA Page 2 Receiver Phase , Problem, Example 1 Stratix GX GXB Duplex Word Aligner Deserializer RX PLL 8B10B Decoder , [0] TX PLL netclk tx_coreclk[0] Place Compensation FIFO and Byte Deserializer 8B10B , PLL J 8B10B Decoder Place Compensation FIFO and Byte Deserializer recouch Altera
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gxb tx_coreclk 8b10b decoder
Abstract: I Transm it Clock Input. This 125 MHZ input clock is used by the 8B10B PCS Section and generates the , 8B10B Encoder/Decoder (MAC + 8B10B PCS) D ecem ber 1, 1997 DATA SHEET Note: Check for latest Data , 8B10B PCS Data Rate -1000 Mbps 32/16-Bit System Interface To External System Bus - 4 Gbps Bandwith 10 , with the 8B10B Encoder/Decoder (also known as 8B10B PCS), which is the digital coding block for fiber , FIFO's, 32-bit System Interface, 8B10B encoder/ decoder, 10-bit P H Y Interface, and a 16-bit Register -
OCR Scan
transmitter ARK 200 32/16-B MD400164/C
Abstract: 8100 · Combined Ethernet MAC and 8B10B PCS · 1000 Mbits/s data rate · 64-bit, 66 MHz , Underflow 8B10B PCS 2.11.1 8B10B Encoder 2.11.2 8B10B Decoder 2.11.3 Start of Packet 2.11.4 End Of , Receive Maximum Packet Size Selection 8B10B Coding Table 10B Defined Ordered Sets Transmit Discard , integrated coding logic for fiber and short haul copper media (8 bit/10 bit Physical Coding Sublayer) (8B10B , Section 2.11, "8B10B PCS" · Section 2.12, "10-Bit PHY Interface" · Section 2.13, "Packet LSI Logic
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100BASE-FX DA16 sony R04 TX2 -RX2 DB14-000123-04 E-198
Abstract: CODEC, 8B10B CODEC, 3.125G SERDES, CDR, and PLL. These functions provide data conversion between the , interface service Internal TX and RX elastic FIFOs 8B10B and 64B66B encoders and decoders Flexible clock scheme; 644.53-MHz VCXO or external reference clocks On-chip phase-locked loop (PLL) providing clock synthesis from 156.25-MHz or 644.53-MHz reference clock MDIO interface Lock detect Comma detection and byte Mitsubishi
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M69850 10G serdes 10Gb CDR 10Gigabit Ethernet PHY IEEE802 3125G 10GBASE-R 3125-G 53-MH
Abstract: with the 125 MHz 8B10B PCS clock whenever a full packet has been loaded into the FIFO (an EOF is , 2.10.3 RX Underflow 8B10B PCS 2.11.1 8B10B Encoder 2.11.2 8B10B Decoder 2.11.3 Start of Packet 2.11.4 End , Multicast Address Filter Map Receive Maximum Packet Size Selection 8B10B Coding Table 10B Defined Ordered , Sublayer) (8B10B PCS) for 1000 Mbits/s Gigabit Ethernet systems. The 8104 is functionally the same as the , · · Pin-compatible upgrade of 8100 Combined Ethernet MAC and 8B10B PCS 1000 Mbits/s data rate 64 LSI Logic
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DB14-000123-01
Abstract: Data Rate (Mbps) Parallel Data/Clk (MHz) SERDES without Encoding/Decoding 8B/10B 400 to , 10B12B CDRX_10B12B 10B/12B CDR receive mode TX_10B12B 10B/12B transmit mode 8B10B CDRX_8B10B 8B/10B CDR receive mode TX_8B10B 8B/10B transmit mode 8B10B HSLB_8B10B 8B/10B High , (Byte Alignment) Synchronization Pattern (Bit Alignment) CDRX_8B10B 11000001010011111010 , in MHz. See Parallel Data/Clk column in Table 1.This attribute is a mandatory input. Table 5 Lattice Semiconductor
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8B10B in serial communication vhdl code for phase shift
Abstract: embedding a simple pseudo-random pattern into an 8b10b-encoded PCS payload, then looping back the payload , the LatticeECP2M's PCS block as transmit payload. The PCS then 8b10b-encodes the data and transmits , 0, 8b10b-decoded in the PCS, then checked for correctness by the PRBS checker. Figure 1 shows the , REFCLK TX PLL ebrd_clk_ch0 100 MHz OSC AUX CHANNEL Y2 txiclk_ch0 J19 Up Sample , ) performs the 8b10b encoding and serialization for the transmitted PRBS data. Likewise, 8b10b decodes and Lattice Semiconductor
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TN1124 verilog prbs generator verilog code of prbs pattern generator fpga loader verilog code 16 bit LFSR in PRBS ECP2M LFE2M50E TN1153 LFE2M-50E DS1006
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