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8B/10B Datasheet

Part Manufacturer Description PDF Type
8b10b Altera Encoder/Decoder MegaCore Function (ED8B10B) Original

8B/10B

Catalog Datasheet MFG & Type PDF Document Tags

8b10b

Abstract: amcc s2062 Part Number S2062 Revision 1.0 - June 22, 2000 S2062 APPLICATION NOTE BYPASSING 8B/10B , S2062 to bypass the 8B/10B encoding/ decoding blocks. Details on how the signals are renamed and the , the 8B/10B encoding/decoding blocks by setting the LC_BYP pin. The LC_BYP signal is located at pin B1 , . The 10 bit mode does not provide line coding/decoding; data passed into the device should be 8B/10B , , provides the option of either using the 8B/10B encoding/decoding scheme or bypassing it. This signal
Applied Micro Circuits
Original
amcc s2062 DINX9 8B/10B

lattice machxo lcmxo1200c

Abstract: set-3b 8b/10b Encoder/Decoder June 2010 Reference Design RD1012 Introduction Many serial data transmission standards utilize 8b/10b encoding to ensure sufficient data transitions for clock recovery. This reference design describes an encoder/decoder suitable for performing 8b/10b encoding/decoding within , reference design. Features · · · · · · 8b to 10b encoder and 10b to 8b decoder Previous octet , checking Conform to 8b/10b specified in IEEE 802.3z and ANSI X3.230-1994 Figure 1. The 8b/10b Encoder
Lattice Semiconductor
Original
LCMXO1200C-3T100C LFXP2-5E-5M132C LFECP6E-5T144C LC51024MB-52F484C lattice machxo lcmxo1200c set-3b K2801 5000MX6 LC4256B-3T100C

virtex-6 ML605 user guide

Abstract: virtex-7 LogiCORE IP Aurora 8B/10B v7.1 DS797 October 19, 2011 Product Specification Introduction The LogiCORETM IP Aurora 8B/10B core supports the AMBA® protocol AXI4-Stream user interface. The core implements the Aurora 8B/10B protocol using the high-speed serial transceivers on the Virtex®-7 and KintexTM , ; and the Spartan®-6 LXT family. The Aurora 8B/10B core is a scalable, lightweight, link-layer protocol , channels. The CORE GeneratorTM software produces source code for Aurora 8B/10B cores with variable datapath
Xilinx
Original
virtex-6 ML605 user guide virtex-7 sp605 UG476 virtex7 ARM v7 block diagram

PM5310

Abstract: PM5372 flows with an extended 8B/10B protocol over 777.6 MHz LVDS links. · Supports multi-plane (inverse , device performance. LVDS Receiver RXLV #1 Rx 8b/10b Frame Aligner R8FA#3 Data Recovery Unit DRU #4 Rx 8b/10b Frame Aligner R8FA#4 Data Recovery Unit DRU #61 Rx 8b/10b Frame Aligner R8FA#61 Data Recovery Unit DRU #62 Rx 8b/10b Frame Aligner R8FA#62 Data Recovery Unit DRU #63 Rx 8b/10b Frame Aligner R8FA#63 LVDS Receiver RXLV #64 RN[4] Data Recovery
PMC-Sierra
Original
PM5372 STS-48 STS-192 PM5310 PM7390 STS-12 STS12

virtex-7

Abstract: Aurora LogiCORE IP Aurora 8B/10B v8.1 DS797 April 24, 2012 Product Specification Introduction The LogiCORETM IP Aurora 8B/10B core supports the AMBA® protocol AXI4-Stream user interface. The core implements the Aurora 8B/10B protocol using the high-speed serial transceivers on the Virtex®-7 and KintexTM , ; and the Spartan®-6 LXT family. The Aurora 8B/10B core is a scalable, lightweight, link-layer protocol , channels. The CORE GeneratorTM tool produces source code for Aurora 8B/10B cores with variable datapath
Xilinx
Original
Aurora LX240T xilinx virtex-7 LX240T-FF1156 Spartan-6 LXT vhdl coding for error correction and detection

8b10b

Abstract: 1S2067 Part Number S2067 Revision 1.0 - June 22, 2000 S2067 APPLICATION NOTE BYPASSING 8B/10B , S2067 to bypass the 8B/10B encoding/ decoding blocks. Details on how the signals are renamed and the , the 8B/10B encoding/decoding blocks by setting the LC_BYP pin. The LC_BYP signal is located at pin B1 , . The 10 bit mode does not provide line coding/decoding; data passed into the device should be 8B/10B , , provides the option of either using the 8B/10B encoding/decoding scheme or bypassing it. This signal
Applied Micro Circuits
Original
1S2067 RX1B transmitter block diagram

virtex-6 ML605 user guide

Abstract: UG353 LogiCORE IP Aurora 8B/10B v5.3 DS637 January 18, 2012 Product Specification Introduction The LogiCORETM IP Aurora 8B/10B core implements the Aurora 8B/10B protocol using the high-speed serial , family, and the Spartan ®-6 LXT family. The Aurora 8B/10B core is a scalable, lightweight, linklayer , , data channels. The CORE GeneratorTM software produces source code for Aurora 8B/10B cores with variable , or 4 of 8 Spartan-6 FPGA GTP transceivers Aurora 8B/10B protocol specification v2.2 compliant Low
Xilinx
Original
UG353 vhdl code 8 bit LFSR SP006 virtex 5 fpga utilization Xilinx ISE Design Suite 14.2 ML605 UCF FILE ML605

K284

Abstract: d143 crystal higher performances in very disturbing environment and also two kind of codings. A 8B/10B coding , Compliant IBM®ESCONTM compliant ATM compatible 8B/10B coded or 10­bit bypass 8B/16B coded or 10­bit bypass Data rate · 8B/10B : 160 to 330 Mbps · 8B/16B : 160 to 400 Mbps · TTL synchronous I/O · · , Receiver transfer data over different kind of media up to 400 Mbps. Using 8B/10B or 8B/16B coding, height , byte is presented in parallel way to the host with the synchronized byte rate clock. The 8B/10B or 8B
Temic Semiconductors
Original
ANM050 K284 d143 crystal ECL 100111 11010 CY7B923 TSS923/933 8B/16B TSS923 TSS933

8b/10b encoder

Abstract: serdes 8b 10b flows with an extended 8B/10B protocol over 777.6 MHz LVDS links. · Supports multi-plane (inverse , device performance. LVDS Receiver RXLV #1 Rx 8b/10b Frame Aligner R8FA#3 Data Recovery Unit DRU #4 Rx 8b/10b Frame Aligner R8FA#4 Data Recovery Unit DRU #61 Rx 8b/10b Frame Aligner R8FA#61 Data Recovery Unit DRU #62 Rx 8b/10b Frame Aligner R8FA#62 Data Recovery Unit DRU #63 Rx 8b/10b Frame Aligner R8FA#63 LVDS Receiver RXLV #64 RN[4] Data Recovery
PMC-Sierra
Original
8b/10b encoder serdes 8b 10b Optical Receiver LVDS OC-48 PM5315 SPECTRA-2488 S/UNI-MACH48 PMC-2000328

8b10b

Abstract: Transceivers ) PINS/ BALL FEATURES SMD # STATUS 28 150-400 Mbps, 8B/10B, BIST N/A Full Production 28 150-400 Mbps, 8B/10B, BIST N/A Full Production 28 150-400 Mbps, 8B/10B, BIST N/A Full Production 28 150-400 Mbps, 8B/10B, BIST N/A Full Production 28 150-400 Mbps, 8B/10B, BIST N/A Full Production Cypress - Advanced Search CY7B923-JIT , 6:20:49 PM Plastic Leaded Chip Carrier (PLCC) 28 150-400 Mbps, 8B/10B, BIST 84
Cypress Semiconductor
Original
CY7B923-400JC CY7B923-400JCT CY7B923-JC CY7B923-JCT CY7B923-JI CY7B923-LMB Transceivers

Transceivers

Abstract: CY7B933-JCT ) PINS/ BALL FEATURES SMD # STATUS 28 150-400 Mbps, 8B/10B, BIST N/A Full Production 28 150-400 Mbps, 8B/10B, BIST N/A Full Production 28 150-400 Mbps, 8B/10B, BIST N/A Full Production 28 150-400 Mbps, 8B/10B, BIST N/A Full Production 28 150-400 Mbps, 8B/10B, BIST N/A Full Production Cypress - Advanced Search CY7B933-JIT , :// (2 of 2)6/26/2005 6:23:19 PM 28 150-400 Mbps, 8B/10B
Cypress Semiconductor
Original
CY7B933-400JC CY7B933-400JCT CY7B933-JC CY7B933-JCT CY7B933-JI CY7B933-LMB

transformer "fibre channel"

Abstract: 40MHz Crystal d40 two kind of codings. A 8B/10B coding totally Fibre Channel compliant. A 8B/16B coding specially , Fibre Channel Compliant IBM®ESCONTM compliant ATM compatible 8B/10B coded or 10-bit bypass 8B/16B coded or 10-bit bypass Data rate 8B/10B : 190 to 400 Mbps 8B/16B : 190 to 400 Mbps TTL synchronous , /10B or 8B/16B coding, height bits of user data are loaded into the transmitter and are encoded , rate clock. The 8B/10B or 8B/16B encoder/decoder can be bypassed in systems that already scramble the
Temic Semiconductors
Original
transformer "fibre channel" 40MHz Crystal d40 hamming encoder decoder D112 quartz crystal 11B/9B

JESD204

Abstract: JESD204A JESD204A 312.5 Mbps 3.125 Gbps 312.5 Mbps 3.125 Gbps 8b/10b R_10002_ZH 01 - 2010 4 12 © NXP B.V.2010 4/16 R_10002 JEDEC JESD204A 8b/10b "" "" "+" "-" 8b/10b "" JESD204A / DVI HDMI CML JESD204A CML 1.2 V 100 JESD204A 10-12 (BER) JESD204A 8b/10b CML FPGA/ASIC / / SYNC~ JESD204A DAC/ASIC , . R_10002_ZH 8B/10B ENCODE Lane 1 Encoded ON/OFF D13 MSB Octet D12 Scrambled Octet
NXP Semiconductors
Original
JESD204 jesd204a altera K287 JC-16

K2811

Abstract: p22bc ORIENTED DC BALANCED 8B/10B PARTITIONED BLOCK TRANSMISSION CODE. BY PROVIDING THIS REFERENCE DESIGN AS ONE , note is not intended to provide complete documentation on 8b/10b. This document gives a brief introduction to 8b/10b, how the encoding/decoding scheme is generated, and how it is implemented in a 16b/20b VHDL application targeted to a CoolRunner XPLA3 CPLD. For more information on 8b/10b coding rules , high-speed local area networks and computer links. The 8b/10b data transmission scheme has become the
Xilinx
Original
XAPP336 XAPP391 K2811 p22bc

vhdl code for clock and data recovery

Abstract: 8B10B , Applications Engineer, Xilinx Inc., jennifer.jenkins@xilinx.com T he 8B/10B data transmission scheme has , random ones and zeros into a 10-bit serial data stream. The 8B/10B encoding rules create a DC balanced , or point-to-point topologies. The 16B/20B transmission scheme incorporates the idea of the 8B/10B transmission code by combining two 8B/10B modules side-by-side. With 16B/20B encoding, a 16-bit word can be , Figure 2 - 8B/10B encoder logic block diagram. data is broken into 5B/6B and 3B/4B encoding functions
Xilinx
Original
vhdl code for clock and data recovery 20B/16B

8b/10b-Serializer Coding Example

Abstract: IBM serdes are relaxed significantly. 8b/10b SerDes Figure 4. 8b/10b serializer coding example. The 8-bit/10-bit (8b/10b) serializer maps each parallel data byte to a 10-bit code and serializes the 10 , 10-bit codes back to byte data, flagging an error if it detects an invalid 10b code. Most 8b/10b , SerDes multiplex several slower SONET/SDH or 8b/10b serial streams into one faster serial stream by , system example implementations based on DS92LV18 SerDes (above) and 8b/10b SerDes (below). Using a
-
Original
8b/10b-Serializer Coding Example IBM serdes ds92lv18 optical link 8b/10b-Serializer

lc4128v-5t100c

Abstract: 8B10B 8b/10b Encoder/Decoder November 2002 Reference Design RD1012 Introduction Many serial data transmission standards utilize 8b/10b encoding to ensure sufficient data transitions for clock recovery. This reference design describes an encoder/decoder suitable for performing 8b/10b encoding/decoding within , · · · · · 8b to 10b encoder and 10b to 8b decoder Previous octet disparity input and current , indicate when invalid data/control character is received Running disparity checking Conform to 8b/10b
Lattice Semiconductor
Original
LFX1200B-03FE680C lc4128v-5t100c KXY 23 8B10B ansi encoder K2371 LC4128V-5T100C 5000MX LC5512MV-5Q208C OR4E02-3BA352 1-800-LATTICE

10-Gigbit

Abstract: PLD Logic Array Byte Serializer 8B/10B Encoder Serializer Reset Logic State , Clocks Receiver Analog Circuits Byte Ordering Byte Deserializer 8B/10B Decoder Rate , 8B/10B Encoder Serializer CMU 1­2 Stratix II GX Device Handbook, Volume 2 Reference , bits or 40 bits, depending on the serialization factor. 8B/10B Encoder Many protocols use 8B/10B encoding. Stratix II GX devices have two dedicated 8B/10B encoders in each transmitter channel. This
Altera
Original
10-Gigbit SIIGX52001-2 375-G

hd-SDI deserializer

Abstract: 3G-SDI serializer PLD Logic Array Byte Serializer 8B/10B Encoder Serializer Reset Logic State , Clocks Receiver Analog Circuits Byte Ordering Byte Deserializer 8B/10B Decoder Rate , 8B/10B Encoder Serializer CMU 1­2 Stratix II GX Device Handbook, Volume 2 Reference , creates a PLD interface of 32 bits or 40 bits, depending on the serialization factor. 8B/10B Encoder Many protocols use 8B/10B encoding. Stratix II GX devices have two dedicated 8B/10B encoders in each
Altera
Original
hd-SDI deserializer 3G-SDI serializer SDI SERIALIZER simple block diagram for digital clock single phase ups block diagram OC-96

COOLRUNNER-II examples

Abstract: error detection code in vhdl STANDARD BYTE ORIENTED DC BALANCED 8B/10B PARTITIONED BLOCK TRANSMISSION CODE. BY PROVIDING THIS , . Notice This application note is not intended to provide complete documentation on 8b/10b. This document gives a brief introduction to 8b/10b, how the encoding/decoding scheme is generated, and how it , on 8b/10b coding rules, please refer to section References, page 26. Introduction Today binary , transmission scheme ideal for high-speed local area networks and computer links. The 8b/10b data transmission
Xilinx
Original
COOLRUNNER-II examples error detection code in vhdl XC2C128-6VQ100 vhdl code switch layer 2

V-by-One

Abstract: Vbyone board Serializer rd_clk Receiver Channel PCS Rx Phase Comp FIFO rx_dataout 8B/10B Encoder Byte Serializer Byte Ordering Byte Deserializer 8B/10B Decoder Rate Match FIFO Receiver , TX Phase Compensation FIFO 8B/10B Encoder Transmitter PMA Serializer Transmitter , 8B/10B encoder Note to Figure 1­4: (1) The x refers to the supported 8-, 10-, 16-, or 20 , significant byte. 8B/10B Encoder The optional 8B/10B encoder generates 10-bit code groups with proper
Altera
Original
V-by-One Vbyone board basic television block diagram CPRI Multi Rate hd-SDI deserializer LVDS K28 f CYIV-52001-3

XAPP581

Abstract: asynchronous fifo vhdl xilinx Design Description Implements PCS features, such as comma detection/alignment, 8B/10B encoding , interface after comma alignment, 8B/10B decoding, and clock correction. Figure 1 shows a block diagram , 8B/10B Decoder RXRUNDISP[1:0] 20 CC FIFO RXNOTINTABLE[1:0] RXDISPERR[1:0] RXCHARISCOMMA , 159.375 MHz BREFCLK_N TXDATA[15:0] 10 20 3x Stuffing 1 byte 8B/10B Encoder dv ­ ON,ON , transmitted/received by the MGT. Each CLK_COR_SEQ_*_* parameter is 10-bit 8B/10B encoded or decoded data, as
Xilinx
Original
XAPP581 XAPP572 asynchronous fifo vhdl xilinx vhdl code fc 2 verilog module of byte comparator verilog code of 8 bit comparator XC2VP7-FF672-6 PPC405 UG035 UG024
Abstract: Data Sheet January 25, 2002 ORCA® ORT82G5 1.0-1.25/2.0-2.5/3.125-3.5 Gbits/s 8b/10b SERDES , transceiver as a network termination device. The device supports embedded 8b/10b encoding/decoding and link , /3.125-3.5 Gbits/s 8b/10b SERDES Backplane Interface FPSC Data Sheet January 25, 2002 Table of Contents , .19 SERDES Receive Path (Backplane Æ FPGA) .19 8b/10b Encoding/Decoding , /3.125-3.5 Gbits/s 8b/10b SERDES Backplane Interface FPSC Table of Contents (continued) Figure Page Table Lattice Semiconductor
Original
680-P BM680 DS01-294NCIP DS01-218NCIP

8B10B

Abstract: SOIC28 8B/10B or 8B/16B encoder/decoder can be disabled in systems that already encode or scramble the , '¢ 8B/10B encoded mode3 â'¢ 8B/16B Hamming encoded mode â'¢ 160 up to 400 Mbaud/s link data rate (8B/16B) â'¢ 160 up to 330 Mbaud/s link data rate (8B/10B) â'¢ Hardened design for SEU tolerance (8B/16B , 3. US Patent 4,488,739 "8B/10B Partitioned Block Transmission Code" Dec 4,1984 (*) Preview MATRA , transmitter to encode the pattern on Do.7 as a data pattern (8B/10B or 8B/16B). When the BYPASS mode is
-
OCR Scan
SOIC28 8B16B 00G73L

8HBC

Abstract: D243 Channel Aligner 8B/10B Decoder debug_rx_phase_comp_fifo_error rx_digitalreset , Compensation FIFO tx_forcedisp tx_invpolarity PIPE Interface coreclkout Byte Serializer 8B/10B , 8B/10B decoder input. This port inverts the data at the input to the 8B/10B decoder. Channel , removed (not supported) 011 - Receiver detected 100 - 8B/10B decoder error 101 - Elastic buffer , the data at the output of rx_dataout is a control or data word. Used with the 8B/10B decoder
Altera
Original
8HBC D243 K280A B010011 10-bit-serdes SIIGX52002-4

JESD204

Abstract: JESD204A JESD204A JEDEC JESD204A PHY SERDES 8b/10b 312.5 Mbps 3.125 Gbps PHY JESD204A FR , Gbps : 312.5 Mbps 3.125 Gbps 8b/10b 8b/10b RD(running disparity) DC ("+" "-" ) 8b/10b 2 ( ) 1 DC JESD204A / CML ( ) DVI HDMI CML JESD204A 100 1.2 V JESD204A 10-12 (BER) DC AC AC JESD204A 3 1 8b/10b CML 2 ( FPGA/ASIC , © NXP B.V. . All rights reserved. 8 / 18 R_10002 NXP JEDEC JESD204A 4. 8B/10B
NXP Semiconductors
Original
DC-10B DAC1408D650 k2838

10G BERT

Abstract: altgx PCS Deserializer rdclk 8B/10B Encoder rx_datain wrclk Serializer Byte Serializer , 8B/10B Encoder rdclk FPGA Fabric CDR Deserializer Word Aligner Deskew FIFO , : TX phase compensation FIFO Byte serializer 8B/10B encoder Transmitter output , ALTGX MegaWizardTM Plug-In Manager. If you select this option, the 8B/10B encoder in the datapath is , Data Path to the Byte Serializer or the 8B/10B Encoder or Serializer rd_clk tx_coreclk tx_clkout
Altera
Original
10G BERT altgx bc 201 transistor match line match sense signal EP4S40G5H40 HD-SDI over sdh circuit diagram of rf transmitter and receiver SIV52001-4
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