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8B/10B- Datasheet

Part Manufacturer Description PDF Type
8b10b Altera Encoder/Decoder MegaCore Function (ED8B10B) Original

8B/10B-

Catalog Datasheet MFG & Type PDF Document Tags

virtex-7

Abstract: Aurora LogiCORE IP Aurora 8B/10B v8.1 DS797 April 24, 2012 Product Specification Introduction The LogiCORETM IP Aurora 8B/10B core supports the AMBA® protocol AXI4-Stream user interface. The core implements the Aurora 8B/10B protocol using the high-speed serial transceivers on the Virtex®-7 and KintexTM , ; and the Spartan®-6 LXT family. The Aurora 8B/10B core is a scalable, lightweight, link-layer protocol , channels. The CORE GeneratorTM tool produces source code for Aurora 8B/10B cores with variable datapath
Xilinx
Original
virtex-7 Aurora LX240T virtex7 xilinx virtex-7 LX240T-FF1156 8B/10B

8b/10b encoder

Abstract: serdes 8b 10b flows with an extended 8B/10B protocol over 777.6 MHz LVDS links. · Supports multi-plane (inverse , device performance. LVDS Receiver RXLV #1 Rx 8b/10b Frame Aligner R8FA#3 Data Recovery Unit DRU #4 Rx 8b/10b Frame Aligner R8FA#4 Data Recovery Unit DRU #61 Rx 8b/10b Frame Aligner R8FA#61 Data Recovery Unit DRU #62 Rx 8b/10b Frame Aligner R8FA#62 Data Recovery Unit DRU #63 Rx 8b/10b Frame Aligner R8FA#63 LVDS Receiver RXLV #64 RN[4] Data Recovery
PMC-Sierra
Original
PM5372 STS-48 STS-192 PM5310 PM7390 8b/10b encoder serdes 8b 10b Optical Receiver LVDS STS-12 STS12

transformer "fibre channel"

Abstract: 40MHz Crystal d40 two kind of codings. A 8B/10B coding totally Fibre Channel compliant. A 8B/16B coding specially , Fibre Channel Compliant IBM®ESCONTM compliant ATM compatible 8B/10B coded or 10-bit bypass 8B/16B coded or 10-bit bypass Data rate 8B/10B : 190 to 400 Mbps 8B/16B : 190 to 400 Mbps TTL synchronous , /10B or 8B/16B coding, height bits of user data are loaded into the transmitter and are encoded , rate clock. The 8B/10B or 8B/16B encoder/decoder can be bypassed in systems that already scramble the
Temic Semiconductors
Original
ANM050 transformer "fibre channel" 40MHz Crystal d40 hamming encoder decoder CY7B923 D112 quartz crystal TSS923/933 8B/16B TSS923 TSS933 11B/9B

10-Gigbit

Abstract: PLD Logic Array Byte Serializer 8B/10B Encoder Serializer Reset Logic State , Clocks Receiver Analog Circuits Byte Ordering Byte Deserializer 8B/10B Decoder Rate , 8B/10B Encoder Serializer CMU 1­2 Stratix II GX Device Handbook, Volume 2 Reference , bits or 40 bits, depending on the serialization factor. 8B/10B Encoder Many protocols use 8B/10B encoding. Stratix II GX devices have two dedicated 8B/10B encoders in each transmitter channel. This
Altera
Original
10-Gigbit SIIGX52001-2 375-G

K2811

Abstract: p22bc ORIENTED DC BALANCED 8B/10B PARTITIONED BLOCK TRANSMISSION CODE. BY PROVIDING THIS REFERENCE DESIGN AS ONE , note is not intended to provide complete documentation on 8b/10b. This document gives a brief introduction to 8b/10b, how the encoding/decoding scheme is generated, and how it is implemented in a 16b/20b VHDL application targeted to a CoolRunner XPLA3 CPLD. For more information on 8b/10b coding rules , high-speed local area networks and computer links. The 8b/10b data transmission scheme has become the
Xilinx
Original
XAPP336 XAPP391 K2811 p22bc

8b10b

Abstract: amcc s2062 Part Number S2062 Revision 1.0 - June 22, 2000 S2062 APPLICATION NOTE BYPASSING 8B/10B , S2062 to bypass the 8B/10B encoding/ decoding blocks. Details on how the signals are renamed and the , the 8B/10B encoding/decoding blocks by setting the LC_BYP pin. The LC_BYP signal is located at pin B1 , . The 10 bit mode does not provide line coding/decoding; data passed into the device should be 8B/10B , , provides the option of either using the 8B/10B encoding/decoding scheme or bypassing it. This signal
Applied Micro Circuits
Original
amcc s2062 DINX9

JESD204

Abstract: JESD204A JESD204A JEDEC JESD204A PHY SERDES 8b/10b 312.5 Mbps 3.125 Gbps PHY JESD204A FR , Gbps : 312.5 Mbps 3.125 Gbps 8b/10b 8b/10b RD(running disparity) DC ("+" "-" ) 8b/10b 2 ( ) 1 DC JESD204A / CML ( ) DVI HDMI CML JESD204A 100 1.2 V JESD204A 10-12 (BER) DC AC AC JESD204A 3 1 8b/10b CML 2 ( FPGA/ASIC , © NXP B.V. . All rights reserved. 8 / 18 R_10002 NXP JEDEC JESD204A 4. 8B/10B
NXP Semiconductors
Original
JESD204 DC-10B DAC1408D650 K287 k2838 JC-16

8B10B

Abstract: SOIC28 8B/10B or 8B/16B encoder/decoder can be disabled in systems that already encode or scramble the , '¢ 8B/10B encoded mode3 â'¢ 8B/16B Hamming encoded mode â'¢ 160 up to 400 Mbaud/s link data rate (8B/16B) â'¢ 160 up to 330 Mbaud/s link data rate (8B/10B) â'¢ Hardened design for SEU tolerance (8B/16B , 3. US Patent 4,488,739 "8B/10B Partitioned Block Transmission Code" Dec 4,1984 (*) Preview MATRA , transmitter to encode the pattern on Do.7 as a data pattern (8B/10B or 8B/16B). When the BYPASS mode is
-
OCR Scan
SOIC28 8B16B 00G73L

BCM5682

Abstract: broadcom switch ethernet "on-chip packet buffer" . Non-Blocking Eight-Port Gigabit Switch GMII 8B/10B GPIC GMII 8B/10B GPIC GMII 8B/10B GMII 8B/10B GPIC GMII 8B/10B GMII 8B/10B GPIC BCM5404 PHY or Fiber Xcvr GMII 8B/10B GMII 8B/10B BCM5404 PHY or Fiber Xcvr GPIC GPIC GPIC GPIC BCM5682 I2C I2C , GIGABIT PORTS 10/100/1000 MBIT CAPABL E (GMII OR 8B/10B) BCM5682 Micr oc on tr oller wit h PROM
Broadcom
Original
broadcom switch ethernet "on-chip packet buffer" GMII microcontroller optics fiber BCM5401 BCM5402 BCM5411 5682-PB05-R

virtex-6 ML605 user guide

Abstract: virtex-7 LogiCORE IP Aurora 8B/10B v7.1 DS797 October 19, 2011 Product Specification Introduction The LogiCORETM IP Aurora 8B/10B core supports the AMBA® protocol AXI4-Stream user interface. The core implements the Aurora 8B/10B protocol using the high-speed serial transceivers on the Virtex®-7 and KintexTM , ; and the Spartan®-6 LXT family. The Aurora 8B/10B core is a scalable, lightweight, link-layer protocol , channels. The CORE GeneratorTM software produces source code for Aurora 8B/10B cores with variable datapath
Xilinx
Original
virtex-6 ML605 user guide sp605 UG476 ARM v7 block diagram verilog code 8 bit LFSR

lattice machxo lcmxo1200c

Abstract: set-3b 8b/10b Encoder/Decoder June 2010 Reference Design RD1012 Introduction Many serial data transmission standards utilize 8b/10b encoding to ensure sufficient data transitions for clock recovery. This reference design describes an encoder/decoder suitable for performing 8b/10b encoding/decoding within , checking Conform to 8b/10b specified in IEEE 802.3z and ANSI X3.230-1994 Figure 1. The 8b/10b Encoder , abcdeifghjabcdeifghjabcdeifghjabcdeifghj D0.0 (RD-) D31.5 (RD-) D0.0 (RD+) K28.5 (RD+) Functional Description The 8b/10b
Lattice Semiconductor
Original
LCMXO1200C-3T100C LFXP2-5E-5M132C LFECP6E-5T144C LC51024MB-52F484C lattice machxo lcmxo1200c set-3b K2801 5000MX6 LC4256B-3T100C

PMD 1000

Abstract: pmd1000 Transceiver Datapath Modules Transmitter PLD/Receiver Byte 8B/10B Functional Word Rate Transceiver , PLD Logic Array PIPE Interface TX Phase Compensation FIFO Byte Serializer 8B/10B , out 8-bit data to the 8B/10B encoder at 250 MHz. This allows clocking the PLD-transceiver interface , ] Byte Serializer From Transmitter Phase Compensation FIFO To 8B/10B Encoder wrclk rdclk , Low-Speed Parallel Clock CMU Local/Central Clock Divider Block 8B/10B Encoder In PCI Express (PIPE
Altera
Original
AGX52002-1 PMD 1000 pmd1000 Arria GX alt2gxb

8b10b

Abstract: 1S2067 Part Number S2067 Revision 1.0 - June 22, 2000 S2067 APPLICATION NOTE BYPASSING 8B/10B , S2067 to bypass the 8B/10B encoding/ decoding blocks. Details on how the signals are renamed and the , the 8B/10B encoding/decoding blocks by setting the LC_BYP pin. The LC_BYP signal is located at pin B1 , . The 10 bit mode does not provide line coding/decoding; data passed into the device should be 8B/10B , , provides the option of either using the 8B/10B encoding/decoding scheme or bypassing it. This signal
Applied Micro Circuits
Original
1S2067 RX1B transmitter block diagram

OC192

Abstract: rsc Encoder supported per channel. The RSC includes 8B/10B encode/decode functions, to support asynchronous data , rate with 8B/10B encoding. Thus, a single Quad RSC supports the entire data rate of a 10Gbps line , 312.5Mbps). These inputs control an 8B/10B encoder, which produces a 10 bit coded character for the output shift register. Users can bypass the 8B/10B encoder for synchronous data transfers that do not require , frame alignment. The received 10 bit character is decoded by an 8B/10B decoder which outputs data on a
Rambus
Original
OC192 rsc Encoder Rambus ASIC Cell 250MH DL-00

10-bit-serdes

Abstract: serdes 8b 10b InfiniBandTM compatible SSTL_2 parallel interface Programmable 8-bit or 10-bit SERDES Selectable 8B/10B , framing - SONET/SDH A1/A2 - 1G Ethernet/Fibre Channel, InfiniBand, XAUI 8B/10B COMMA Diagnostic loop , CODE FRAME APPLICATION 10 bit SERDES, 8B/10B 1 0 1 1 encoding/decoding, COMMA framing, and PCS functions 10 bit SERDES, no en2 0 0 0 coding/decoding and no framing 10 bit SERDES, 8B/10B 3 0 1 0 encoding , device capable of operating at serial rates up to 3.125 Gbps per channel. It performs the 8B/10B encode
Cypress Semiconductor
Original
10-bit-serdes ann antes 0401DX CYP32G0401DX XAUI/10G IEEE802 256-L BG256

PM5310

Abstract: PM5372 flows with an extended 8B/10B protocol over 777.6 MHz LVDS links. · Supports multi-plane (inverse , device performance. LVDS Receiver RXLV #1 Rx 8b/10b Frame Aligner R8FA#3 Data Recovery Unit DRU #4 Rx 8b/10b Frame Aligner R8FA#4 Data Recovery Unit DRU #61 Rx 8b/10b Frame Aligner R8FA#61 Data Recovery Unit DRU #62 Rx 8b/10b Frame Aligner R8FA#62 Data Recovery Unit DRU #63 Rx 8b/10b Frame Aligner R8FA#63 LVDS Receiver RXLV #64 RN[4] Data Recovery
PMC-Sierra
Original
OC-48 PM5315 SPECTRA-2488 S/UNI-MACH48 PMC-2000328
Abstract: size (omax/ (mArms/ 20c, fDbL(mm) 125c, 100kHz) Note1) 8B 10B 10B 10B 12.5B 16B 16B 8B 10B 10B 10B 12.5B 16B 16B 8B 10B 10B 10B 12.5B 16B 8B 10B 10B 10B 12.5B 16B 8B 8B 8B 8B 10B 10B 12.5B 12.5B 16B 8B 10B 10B 12.5B 12.5B 12.5B 16B 8B 10B 12 12.5 12.5 20 25 25 31.5 12 12.5 12.5 16 20 25 31.5 12 12.5 16 Nippon Chemi-Con
Original
000MF EGXE101ESS331MLN3S EGXE161ESS220MJ20S EGXE161ESS330MJ25S EGXE161ESS470MK20S EGXE161ESS680MK25S

64b/66b encoder

Abstract: BCM8702 /descrambler XGXS 8B/10B error detection ENDEC XAUI link synchronization/deskew Four-lane, 3.125-Gbps XAUI , 8B/10B Encoder XDOP XDON Serializer 8B/10B Encoder 64B/66B Synchronizer Descrambler , CDR & Deserializer XDIP XDIN Sync Detect Lane Sync 8B/10B Decoder Sync Detect Lane Sync 8B/10B Decoder Lane Alignment FIFO Lane Alignment FIFO 64B/66B Encoder Scrambler , include 8B/10B coding, 64B/66B coding, SerDes, Clock Multiplication Unit (CMU), and Clock and Data
Broadcom
Original
BCM8702 64b/66b encoder 8b/10b decoder gearbox MDIO clause 45 64B66B 10-GIGABIT 125-G 8702-PB04-R

K284

Abstract: d143 crystal higher performances in very disturbing environment and also two kind of codings. A 8B/10B coding , Compliant IBM®ESCONTM compliant ATM compatible 8B/10B coded or 10­bit bypass 8B/16B coded or 10­bit bypass Data rate · 8B/10B : 160 to 330 Mbps · 8B/16B : 160 to 400 Mbps · TTL synchronous I/O · · , Receiver transfer data over different kind of media up to 400 Mbps. Using 8B/10B or 8B/16B coding, height , byte is presented in parallel way to the host with the synchronized byte rate clock. The 8B/10B or 8B
Temic Semiconductors
Original
K284 d143 crystal ECL 100111 11010 TSS323

EP2SGX60EF

Abstract: k307 Channel Aligner 8B/10B Decoder debug_rx_phase_comp_fifo_error rx_digitalreset , Compensation FIFO tx_forcedisp tx_invpolarity PIPE Interface coreclkout Byte Serializer 8B/10B , for PCI Express (PIPE) polarity inversion at the 8B/10B decoder input. This port inverts the data at the input to the 8B/10B decoder. Channel Altera Corporation October 2007 Stratix II GX , is a control or data word. Used with the 8B/10B decoder. Channel rx_errdetect Output 8B
Altera
Original
SIIGX52002-4 EP2SGX60EF k307 PRBS10 CEI 23-16 circuit diagram of PPM transmitter and receiver

COOLRUNNER-II examples

Abstract: error detection code in vhdl STANDARD BYTE ORIENTED DC BALANCED 8B/10B PARTITIONED BLOCK TRANSMISSION CODE. BY PROVIDING THIS , . Notice This application note is not intended to provide complete documentation on 8b/10b. This document gives a brief introduction to 8b/10b, how the encoding/decoding scheme is generated, and how it , on 8b/10b coding rules, please refer to section References, page 26. Introduction Today binary , transmission scheme ideal for high-speed local area networks and computer links. The 8b/10b data transmission
Xilinx
Original
COOLRUNNER-II examples error detection code in vhdl XC2C128-6VQ100 vhdl code switch layer 2

V-by-One

Abstract: Vbyone board Serializer rd_clk Receiver Channel PCS Rx Phase Comp FIFO rx_dataout 8B/10B Encoder Byte Serializer Byte Ordering Byte Deserializer 8B/10B Decoder Rate Match FIFO Receiver , TX Phase Compensation FIFO 8B/10B Encoder Transmitter PMA Serializer Transmitter , 8B/10B encoder Note to Figure 1­4: (1) The x refers to the supported 8-, 10-, 16-, or 20 , significant byte. 8B/10B Encoder The optional 8B/10B encoder generates 10-bit code groups with proper
Altera
Original
V-by-One Vbyone board basic television block diagram CPRI Multi Rate hd-SDI deserializer LVDS K28 f CYIV-52001-3

virtex-6 ML605 user guide

Abstract: UG353 LogiCORE IP Aurora 8B/10B v5.3 DS637 January 18, 2012 Product Specification Introduction The LogiCORETM IP Aurora 8B/10B core implements the Aurora 8B/10B protocol using the high-speed serial , family, and the Spartan ®-6 LXT family. The Aurora 8B/10B core is a scalable, lightweight, linklayer , , data channels. The CORE GeneratorTM software produces source code for Aurora 8B/10B cores with variable , or 4 of 8 Spartan-6 FPGA GTP transceivers Aurora 8B/10B protocol specification v2.2 compliant Low
Xilinx
Original
UG353 vhdl code 8 bit LFSR SP006 virtex 5 fpga utilization Xilinx ISE Design Suite 14.2 ML605 UCF FILE ML605

XAPP581

Abstract: asynchronous fifo vhdl xilinx Design Description Implements PCS features, such as comma detection/alignment, 8B/10B encoding , interface after comma alignment, 8B/10B decoding, and clock correction. Figure 1 shows a block diagram , 8B/10B Decoder RXRUNDISP[1:0] 20 CC FIFO RXNOTINTABLE[1:0] RXDISPERR[1:0] RXCHARISCOMMA , 159.375 MHz BREFCLK_N TXDATA[15:0] 10 20 3x Stuffing 1 byte 8B/10B Encoder dv ­ ON,ON , transmitted/received by the MGT. Each CLK_COR_SEQ_*_* parameter is 10-bit 8B/10B encoded or decoded data, as
Xilinx
Original
XAPP581 XAPP572 asynchronous fifo vhdl xilinx vhdl code fc 2 verilog module of byte comparator verilog code of 8 bit comparator XC2VP7-FF672-6 PPC405 UG035 UG024
Abstract: Data Sheet January 25, 2002 ORCA® ORT82G5 1.0-1.25/2.0-2.5/3.125-3.5 Gbits/s 8b/10b SERDES , transceiver as a network termination device. The device supports embedded 8b/10b encoding/decoding and link , /3.125-3.5 Gbits/s 8b/10b SERDES Backplane Interface FPSC Data Sheet January 25, 2002 Table of Contents , .19 SERDES Receive Path (Backplane Æ FPGA) .19 8b/10b Encoding/Decoding , /3.125-3.5 Gbits/s 8b/10b SERDES Backplane Interface FPSC Table of Contents (continued) Figure Page Table Lattice Semiconductor
Original
680-P BM680 DS01-294NCIP DS01-218NCIP

8HBC

Abstract: D243 Channel Aligner 8B/10B Decoder debug_rx_phase_comp_fifo_error rx_digitalreset , Compensation FIFO tx_forcedisp tx_invpolarity PIPE Interface coreclkout Byte Serializer 8B/10B , 8B/10B decoder input. This port inverts the data at the input to the 8B/10B decoder. Channel , removed (not supported) 011 - Receiver detected 100 - 8B/10B decoder error 101 - Elastic buffer , the data at the output of rx_dataout is a control or data word. Used with the 8B/10B decoder
Altera
Original
8HBC D243 K280A B010011

lc4128v-5t100c

Abstract: 8B10B 8b/10b Encoder/Decoder November 2002 Reference Design RD1012 Introduction Many serial data transmission standards utilize 8b/10b encoding to ensure sufficient data transitions for clock recovery. This reference design describes an encoder/decoder suitable for performing 8b/10b encoding/decoding within , indicate when invalid data/control character is received Running disparity checking Conform to 8b/10b , in ispXPGA and ispGDX2 Figure 1. The 8b/10b Encoder/Decoder in a System LSB MSB LSB MSB
Lattice Semiconductor
Original
LFX1200B-03FE680C lc4128v-5t100c KXY 23 8B10B ansi encoder K2371 LC4128V-5T100C 5000MX LC5512MV-5Q208C OR4E02-3BA352 1-800-LATTICE

10G BERT

Abstract: altgx PCS Deserializer rdclk 8B/10B Encoder rx_datain wrclk Serializer Byte Serializer , 8B/10B Encoder rdclk FPGA Fabric CDR Deserializer Word Aligner Deskew FIFO , : TX phase compensation FIFO Byte serializer 8B/10B encoder Transmitter output , ALTGX MegaWizardTM Plug-In Manager. If you select this option, the 8B/10B encoder in the datapath is , Data Path to the Byte Serializer or the 8B/10B Encoder or Serializer rd_clk tx_coreclk tx_clkout
Altera
Original
10G BERT altgx bc 201 transistor match line match sense signal EP4S40G5H40 HD-SDI over sdh circuit diagram of rf transmitter and receiver SIV52001-4
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