88F6180 88F6190 88F6192 88F6281 MV-S104860-U0 88F6192/88F6281 - Datasheet Archive

 

88F6180, 88F6190, 88F6192, and 88F6281 Integrated Controller Functional Specifications Doc. No. MV-S104860-U0, Rev. C December 2,

 

Cover 88F6180 88F6180, 88F6190 88F6190, 88F6192 88F6192, and 88F6281 88F6281 Integrated Controller Functional Specifications Doc. No. MV-S104860-U0 MV-S104860-U0, Rev. C December 2, 2008, Preliminary Marvell. Moving Forward Faster Document Classification: Proprietary Information 88F6180/88F619x/88F6281 Functional Specifications Document Conventions Note: Provides related information or information of special importance. Caution: Indicates potential damage to hardware or software, or loss of data. Warning: Indicates a risk of personal injury. Document Status Doc Status: Preliminary Technical Publication: 0.xx For more information, visit our website at: www.marvell.com Disclaimer No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, for any purpose, without the express written permission of Marvell. Marvell retains the right to make changes to this document at any time, without notice. Marvell makes no warranty of any kind, expressed or implied, with regard to any information contained in this document, including, but not limited to, the implied warranties of merchantability or fitness for any particular purpose. Further, Marvell does not warrant the accuracy or completeness of the information, text, graphics, or other items contained within this document. Marvell products are not designed for use in life-support equipment or applications that would cause a life-threatening situation if any such products failed. Do not use Marvell products in these types of equipment or applications. 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At all times hereunder, the recipient of any such information agrees that they shall be deemed to have manually signed this document in connection with their receipt of any such information. Copyright © 2008. Marvell International Ltd. All rights reserved. Marvell, the Marvell logo, Moving Forward Faster, Alaska, Fastwriter, Datacom Systems on Silicon, Libertas, Link Street, NetGX, PHYAdvantage, Prestera, Raising The Technology Bar, The Technology Within, Virtual Cable Tester, and Yukon are registered trademarks of Marvell. Ants, AnyVoltage, Discovery, DSP Switcher, Feroceon, GalNet, GalTis, Horizon, Marvell Makes It All Possible, RADLAN, UniMAC, and VCT are trademarks of Marvell. All other trademarks are the property of their respective owners. Doc. No. MV-S104860-U0 MV-S104860-U0 Rev. C Page 2 Copyright © 2008 Marvell Document Classification: Proprietary Information December 2, 2008, Preliminary Table of Contents Table of Contents Preface.17 About this Document .17 Relevant Devices .17 Related Documentation.17 Document Conventions .19 1 Overview. 20 1.1 Block Diagrams .21 1.2 Overview of Functions and Interfaces .25 1.3 Differences Between the 88F6180 88F6180, 88F6190 88F6190, 88F6192 88F6192, and 88F6281 88F6281 Devices.31 2 Address Map . 34 2.1 SheevaTM CPU Core Address Decoding.34 2.2 TDM (SLIC/Codec) Address Map (88F6192/88F6281 88F6192/88F6281 Only) .37 2.3 PCI Express Address Decoding .37 2.4 SATA Address Decoding (88F619x/88F6281) .39 2.5 Gigabit Ethernet Address Decoding .39 2.6 USB Address Decoding .39 2.7 Security Accelerator Address Decoding.39 2.8 XOR Engine Address Decoding .40 2.9 TWSI Address Decoding .40 2.10 Audio Interface Address Map (88F6180/88F6192/88F6281 88F6180/88F6192/88F6281 Only).40 2.11 SDIO Address Map .40 2.12 Transport Stream (TS) Address Map (88F6192/88F6281 88F6192/88F6281 Only) .41 2.13 Default Address Map.41 3 SheevaTM CPU Core. 43 4 DDR SDRAM Controller . 44 4.1 SDRAM Controller Implementation .44 4.2 DDR SDRAM Addressing.45 4.3 SDRAM Timing Parameters .47 4.4 DRAM Burst .48 4.5 SDRAM Bank Interleaving .48 4.6 SDRAM Open Pages .49 4.7 SDRAM Refresh.49 4.8 SDRAM Initialization .49 4.9 SDRAM Operation Register .50 Copyright © 2008 Marvell December 2, 2008, Preliminary Doc. No. MV-S104860-U0 MV-S104860-U0 Rev. C Document Classification: Proprietary Information Page 3 88F6180/88F619x/88F6281 Functional Specifications 4.10 SDRAM Self Refresh Mode .50 4.11 Heavy Load Support .52 4.12 SDRAM Clocking .52 4.13 SDRAM Address/Data Drive .52 4.14 SDRAM Read Data Sample .53 4.15 DDR2 On Die Termination (ODT) .53 5 Time Division Multiplexing (TDM) Unit (88F6192 88F6192 and 88F6281 88F6281 Only) . 56 5.1 Functional Description.56 5.2 TDM Protocol Specification .59 5.3 TDM (SLIC/Codec) Registers Access via SPI.71 6 PCI Express Interface. 74 6.1 Functional Description.74 6.2 Link Initialization .76 6.3 Master Memory Transactions.76 6.4 Master I/O Transactions .77 6.5 Master Configuration Transactions .77 6.6 Target Memory Transactions .78 6.7 Target I/O Transactions .78 6.8 Target Configuration Transactions .78 6.9 Target Special Cases .79 6.10 Messages.79 6.11 Message Signaled Interrupts (MSI).81 6.12 Locked Transactions .81 6.13 Arbitration and Ordering .81 6.14 PCI Express Register Access .82 6.15 Hot Reset .83 6.16 Link Disable.83 6.17 Power Management .83 6.18 Error Handling .84 6.19 Loopback Modes.86 6.20 Peer-to-Peer Traffic.88 7 Serial-ATA (SATA) II Interface (88F619x and 88F6281 88F6281 Only) . 89 7.1 Serial ATA II Host Controller (SATAHC) .89 7.2 SATAHC Block Diagram .90 7.3 SATAHC Initialization .90 7.4 Host Direct Control Over the Hard Disk Drive .90 7.5 LED Indications .91 7.6 EDMA Operation .91 7.7 BIST .111 Doc. No. MV-S104860-U0 MV-S104860-U0 Rev. C Page 4 Copyright © 2008 Marvell Document Classification: Proprietary Information December 2, 2008, Preliminary Table of Contents 7.8 Vendor Unique .112 7.9 Protocol Based Port Select .112 8 Gigabit Ethernet Controller .113 8.1 Port Features .113 8.2 Functional Overview.114 8.3 DMA Functionality .116 8.4 Receive Frame Processing .134 8.5 Marvell® Header Support.136 8.6 Distributed Switching Architecture (DSA) Tag Support .139 8.7 Ethernet Interrupts .143 8.8 Transmit Weighted Round-Robin Arbitration.144 8.9 Token Rate Configuration .146 8.10 Transmit Queues Egress Jitter Pacing (EJP) Arbitration .147 8.11 Network Interface (10/100/1000 Mbps) .150 8.12 Auto-Negotiation .153 8.13 Data Blinder .154 8.14 Inter-packet Gap .154 8.15 Illegal Frames.154 8.16 Backpressure Mode .155 8.17 Flow Control .155 8.18 Serial Management Interface (SMI) .157 8.19 Link Detection and Link Detection Bypass (ForceLinkPass*) .158 8.20 Precise Time Protocol (PTP).158 8.21 Network Management Interface Counters.168 8.22 Port MIB Counters.168 9 Universal Serial Bus (USB 2.0) Interface .173 10 Cryptographic Engines and Security Accelerator (CESA) .174 10.1 Cryptographic Engine Features .175 10.2 Security Accelerator Features .175 10.3 Cryptographic Engines Operational Description .175 10.4 Security Accelerator Operational Description.189 10.5 TDMA Controller .200 11 XOR Engine.205 11.1 Theory of Operation .205 11.2 Descriptor Chain .209 11.3 Address Decoding .213 11.4 Arbitration .214 11.5 XOR Engine Programming.215 Copyright © 2008 Marvell December 2, 2008, Preliminary Doc. No. MV-S104860-U0 MV-S104860-U0 Rev. C Document Classification: Proprietary Information Page 5 88F6180/88F619x/88F6281 Functional Specifications 11.6 Burst Limit .219 11.7 Errors and Interrupts .220 12 Two-Wire Serial Interface (TWSI) .221 12.1 TWSI Bus Operation .221 12.2 TWSI Port Operation .222 12.3 TWSI Serial ROM Initialization .227 13 UART Interface.228 13.1 Features .228 13.2 UART Interface Pin Assignment .228 13.3 Operation .228 13.4 Programmable Baud-Rate Generator .229 14 8-bit NAND Flash Interface .231 14.1 NAND Flash Interface Pin Assignment .231 14.2 NAND Flash Types .231 14.3 Software Responsibilities .231 14.4 NAND Flash Interface Read Timing Parameters .232 14.5 NAND Flash Interface Write Timing Parameters.234 14.6 Boot from NAND Flash.234 15 Serial Peripheral Interface (SPI) .236 15.1 SPI Interface Signals.236 15.2 Indirect Mode .237 15.3 Direct Mode .237 16 Audio (I2S / S/PDIF) Interface (88F6180 88F6180, 88F6192 88F6192, and 88F6281 88F6281 Only) .240 16.1 Recording Data Flow.242 16.2 Playback Flow .246 16.3 Error Handling .251 16.4 Audio Unit Memory Structure .252 17 Secure Digital Input/Output (SDIO) Interface .256 17.1 Features .257 17.2 SDMem, MMC, and SDIO Arbitration Scheme .257 17.3 Difference Between SD Cards and MMC Cards .259 17.4 SDIO / SDMem / MMC Host Controller Initialization .259 17.5 SDIO / SDMem / MMC Command Execution.259 17.6 SDIO / SDMem / MMC Interrupts.261 18 Transport Stream (TS) Interface (88F6192 88F6192 and 88F6281 88F6281 Only) .262 18.1 TS Port Architecture .263 18.2 TS Interface.263 Doc. No. MV-S104860-U0 MV-S104860-U0 Rev. C Page 6 Copyright © 2008 Marvell Document Classification: Proprietary Information December 2, 2008, Preliminary Table of Contents 18.3 Clocks .266 18.4 TS Input Data Flow .267 18.5 TS Output Data Flow.267 18.6 DMA Engine .267 18.7 TS Timestamp Mechanism.272 18.8 TS Packet Aggregation .273 18.9 TS Port Interrupts .275 18.10 Loopback Mode.276 19 General-Purpose I/O (GPIO) Port Interface .277 19.1 GPIO Control Registers .277 19.2 GPIO Blink Enable Register .277 19.3 GPIO Interrupts .277 20 Real-Time Clock (RTC) Unit .278 20.1 Features .278 20.2 Functionality .278 21 Interrupt Controller.280 21.1 Local Interrupt Cause and Mask Registers .280 21.2 Main Interrupt Cause and Mask Registers .281 21.3 Doorbell Interrupt .281 21.4 Device Interrupt Controller Scheme .282 22 Timers and Counters.283 22.1 32-bit General-Purpose Timers .283 22.2 Watchdog Timer .283 22.3 RTC Alarm .283 22.4 SYSRSTn Duration Counter .285 23 eFuse .286 23.1 Typical eFuse Applications .286 23.2 eFuse Power Supply .286 23.3 eFuse Program and Lock .286 23.4 eFuse Read.287 24 System Considerations.288 24.1 Big and Little Endian Support.288 24.2 BootROM Firmware .290 24.3 Power Management .303 24.4 Error Handling Functional Description.309 Copyright © 2008 Marvell December 2, 2008, Preliminary Doc. No. MV-S104860-U0 MV-S104860-U0 Rev. C Document Classification: Proprietary Information Page 7 88F6180/88F619x/88F6281 Functional Specifications 25 Internal Architecture .312 25.1 Mbus-L-SheevaTM CPU Core Local Bus.312 25.2 Mbus-Device Internal Bus.315 25.3 Mbus-L to Mbus Bridge .317 25.4 Transaction Ordering .317 A 88F6180/88F619x/88F6281 Register Set .352 A.1 Registers Overview .352 A.2 Internal Registers Address Map .354 B Revision History .786 Doc. No. MV-S104860-U0 MV-S104860-U0 Rev. C Page 8 Copyright © 2008 Marvell Document Classification: Proprietary Information December 2, 2008, Preliminary List of Tables List of Tables Preface.17 1 Overview. 20 Table 1: 2 88F6180 88F6180, 88F619x, and 88F6281 88F6281 Device Differences and Similarities .31 Address Map . 34 Table 2: Units IDs and Attributes-CPU .35 Table 3: Unit IDs and Attributes-PCI Express .38 Table 4: Device Default Address Map .41 3 SheevaTM CPU Core. 43 4 DDR SDRAM Controller. 44 Table 5: DDR2 DRAM Addressing .45 Table 6: Address Multiplex for 16b Interface, AddrSel = 0 .46 Table 7: SDRAM Timing Parameters .47 Table 9: 5 Address Multiplex for 16b Interface, AddrSel = 1 .46 Table 8: M_STARTBURST Output Assertion Point Configuration.53 Time Division Multiplexing (TDM) Unit (88F6192 88F6192 and 88F6281 88F6281 Only) . 56 Table 10: 6 Time Division Multiplexing (TDM) Interface Signals .58 PCI Express Interface. 74 Table 11: Supported Message Groups-Endpoint Mode .80 Table 13: Physical Layer Error List .84 Table 14: Data Link Layer Error List .84 Table 15: 7 Supported Message Groups-Root Complex Mode .79 Table 12: Transaction Layer Error List .85 Serial-ATA (SATA) II Interface (88F619x and 88F6281 88F6281 Only) . 89 Table 16: Disc Status LED State Settings .91 Table 17: EDMA CRQB Data Structure Map .104 Table 18: CRQB DW0-cPRD Descriptor Table Base Low Address .105 Table 19: CRQB DW1-cPRD Descriptor Table Base High Address .105 Table 20: CRQB DW2-Control Flags .105 Table 21: CRQB DW3-Data Region Byte Count .106 Table 22: CRQB DW4-ATA Command .106 Table 23: CRQB DW5-ATA Command .106 Table 24: CRQB DW6-ATA Command .107 Table 25: CRQB DW7-ATA Command .107 Table 26: ePRD Table Data Structure Map .108 Table 27: ePRD DWORD 0 .108 Table 28: ePRD DWORD 1 .109 Copyright © 2008 Marvell December 2, 2008, Preliminary Doc. No. MV-S104860-U0 MV-S104860-U0 Rev. C Document Classification: Proprietary Information Page 9 88F6180/88F619x/88F6281 Functional Specifications Table 29: ePRD DWORD 2 .109 Table 30: ePRD DWORD 3 .109 Table 31: EDMA CRPB Data Structure Map .110 Table 32: CRPB Response Flags Register .110 Table 34: 8 CRPB ID Register .110 Table 33: CRPB Time Stamp Register .111 Gigabit Ethernet Controller.113 Table 35: Transmit Descriptor Command/Status.123 Table 36: Transmit Descriptor Byte Count.125 Table 37: Transmit Descriptor Buffer Pointer .125 Table 38: Transmit Descriptor Next Descriptor Pointer .125 Table 39: Receive Descriptor Command/Status.132 Table 40: Receive Descriptor Byte Count.134 Table 41: Receive Descriptor Buffer Pointer .134 Table 42: Receive Descriptor Next Descriptor Pointer .134 Table 43: Marvell Header Fields .137 Table 44: DSA Tag Fields (TO_CPU Format) .140 Table 45: DSA Tag Fields (FORWARD Format) .141 Table 46: Token Rate Configuration Examples .147 Table 47: SMI Bit Stream Format .157 Table 48: Definitions for MAC MIB Counters .168 9 Universal Serial Bus (USB 2.0) Interface .173 10 Cryptographic Engines and Security Accelerator (CESA) .174 Table 49: Acronyms, Abbreviations, and Definitions .174 Table 50: Security Accelerator Data Structure Dword 0-Configuration .196 Table 51: Security Accelerator Data Structure Dword 1-Encryption Pointers .197 Table 52: Security Accelerator Data Structure Dword 2-Encryption Data Length .198 Table 53: Security Accelerator Data Structure Dword 3-Encryption Keys Pointer .198 Table 54: Security Accelerator Data Structure Dword 4-Encryption Initial Values Pointer.198 Table 55: Security Accelerator Data Structure Dword 5-MAC Source Pointer.199 Table 56: Security Accelerator Data Structure Dword 7-MAC Initial Values Pointers .199 Table 58: 11 Security Accelerator Data Structure Dword 6-MAC Digest .199 Table 57: TDMA Descriptor Definitions .201 XOR Engine .205 Table 59: Descriptor Status Word Definition.211 Table 60: Descriptor CRC-32 CRC-32 Result Word Definition.211 Table 61: Descriptor Command Word Definition .211 Table 62: Descriptor Next Descriptor Address Word .212 Table 63: Descriptor Byte Count Word .212 Table 64: Descriptor Destination Address Word.212 Table 65: Descriptor Source Address #N Words .213 Table 66: EOC/EOD interpretation .220 Doc. No. MV-S104860-U0 MV-S104860-U0 Rev. C Page 10 Copyright © 2008 Marvell Document Classification: Proprietary Information December 2, 2008, Preliminary List of Tables 12 Two-Wire Serial Interface (TWSI) .221 Table 67: 13 TWSI Control Register Bits .223 Table 68: TWSI Status Codes .224 UART Interface.228 Table 69: 14 8-bit NAND Flash Interface .231 Table 70: 15 Audio Unit Memory Bit Description .255 Secure Digital Input/Output (SDIO) Interface .256 Table 73: 18 SPI Interface Signals .236 Audio (I2S / S/PDIF) Interface (88F6180 88F6180, 88F6192 88F6192, and 88F6281 88F6281 Only) .240 Table 72: 17 Device Controller Pin Assignments .231 Serial Peripheral Interface (SPI) .236 Table 71: 16 Typical Baud Rates where TCLK = 166 MHz .230 Software Flow .260 Transport Stream (TS) Interface (88F6192 88F6192 and 88F6281 88F6281 Only).262 Table 74: Transport Stream (TS) Interface Signal Assignment .264 19 General-Purpose I/O (GPIO) Port Interface .277 20 Real-Time Clock (RTC) Unit .278 21 Interrupt Controller.280 22 Timers and Counters.283 Table 75: 23 24 Alarm Interrupt Valid Bit Usage .284 eFuse .286 System Considerations.288 Table 76: MMU Virtual-to-Physical Address Translation Table .291 Table 77: Main Header Format .293 Table 78: Header Extension Format .294 Table 79: Types of NAND Flash Read Commands Supported.301 Table 80: Types of ECC Protocols Supported per Flash Type .302 Table 81: Bad Block Indicators per NAND Flash Cell Type.302 Table 82: 512 Mb-SDRAM IDD Values .304 Table 83: PCI Express Error Handling.310 Table 85: 25 CPU Address Decoding Error Handling.310 Table 84: USB Error Handling .311 Internal Architecture.312 Table 86: Mbus Units .315 Copyright © 2008 Marvell December 2, 2008, Preliminary Doc. No. MV-S104860-U0 MV-S104860-U0 Rev. C Document Classification: Proprietary Information Page 11 88F6180/88F619x/88F6281 Functional Specifications A 88F6180/88F619x/88F6281 Register Set .352 Table 87: Register Field Type Codes .352 Table 88: Device Internal Registers Address Map .354 Table 89: Register Map Table for the Mbus-L to Mbus Bridge Registers .355 Table 159: Register Map Table for the DDR SDRAM Controller Registers.389 Table 194: Register Map Table for the Time Division Multiplexing (TDM) Unit Registers .413 Table 242: Register Map Table for the PCI Express Interface Registers .437 Table 326: Register Map Table for the Serial-ATA Host Controller (SATAHC) Registers.491 Table 399: Shadow Register Block Registers Map .549 Table 400: Register Map Table for the Gigabit Ethernet Controller Registers.550 Table 465: Register Map Table for the PTP Registers .597 Table 500: Register Map Table for the USB 2.0 Registers.625 Table 515: USB Controller Register Map (Offsets: 0x50000­0x502FF).632 Table 516: Register Map Table for the Cryptographic Engine and Security Accelerator (CESA) Registers .634 Table 581: Register Map Table for the XOR Engine Registers .657 Table 601: Register Map Table for the TWSI Registers .671 Table 610: Register Map Table for the NAND Flash Registers .675 Table 614: Register Map Table for the UART Registers .678 Table 627: Register Map Table for the SPI Registers .685 Table 636: Register Map Table for the Audio Interface Registers .689 Table 677: Register Map Table for the SDIO Registers .714 Table 729: Register Map Table for the Transport Stream (TS) Registers .744 Table 740: Register Map for TSU Registers .749 Table 766: Register Map Table for the General Purpose Port Registers .762 Table 783: Register Map Table for the RTC Registers.767 Table 790: Register Map Table for the Boot ROM Registers .771 Table 792: Register Map Table for the MPP Registers .773 Table 801: Register Map Table for the eFuse Registers .779 Table 808: Register Map Table for the Miscellaneous Registers .782 B Revision History .786 Table 816: Revision History .786 Doc. No. MV-S104860-U0 MV-S104860-U0 Rev. C Page 12 Copyright © 2008 Marvell Document Classification: Proprietary Information December 2, 2008, Preliminary List of Figures List of Figures Preface.17 1 Overview. 20 Figure 1: 88F6180 88F6180 Interface Block Diagram .21 Figure 2: 88F6190 88F6190 Interface Block Diagram .22 Figure 3: 88F6192 88F6192 Interface Block Diagram .23 Figure 4: 88F6281 88F6281 Interface Block Diagram .24 2 Address Map . 34 3 SheevaTM CPU Core. 43 4 DDR SDRAM Controller. 44 Figure 5: 5 DDR2 I/O Buffer .54 Time Division Multiplexing (TDM) Unit (88F6192 88F6192 and 88F6281 88F6281 Only) . 56 Figure 6: SLIC/Codec Connection Example .56 Figure 7: TDM Unit Block Diagram .57 Figure 8: TDM Operation Time Slot 0 .59 Figure 9: TDM Wideband Mode Operation .60 Figure 10: TDM Transmit Path.63 Figure 11: TDM Receive Path.68 Figure 12: 6 Codec Register Write Operation .72 Figure 13: Codec Register Read Operation.73 PCI Express Interface. 74 Figure 14: High-level Block Diagram .75 Figure 15: 7 Shallow Internal Loopback.87 Figure 16: Deep Internal Loopback.87 Serial-ATA (SATA) II Interface (88F619x and 88F6281 88F6281 Only) . 89 Figure 17: SATAHC Block Diagram .90 Figure 18: Command Request Queue-32 Entries .92 Figure 20: Command Response Queue-32 Entries .93 Figure 21: 8 Disc Status LED Indication Diagram.91 Figure 19: EDMA Interrupt Hierarchy.100 Gigabit Ethernet Controller. 113 Figure 22: Ethernet Descriptors and Buffers.116 Figure 23: Ethernet Packet Transmission Example .119 Figure 24: Transmit Descriptor Description .122 Figure 25: Receive Descriptor Description .131 Figure 26: Rx Packet Marvell Header Example .137 Copyright © 2008 Marvell December 2, 2008, Preliminary Doc. No. MV-S104860-U0 MV-S104860-U0 Rev. C Document Classification: Proprietary Information Page 13 88F6180/88F619x/88F6281 Functional Specifications Figure 27: Tx Packet with Marvell Header Example .138 Figure 28: Rx Packet with DSA Tag Example (4 bytes tag, TO_CPU Format).139 Figure 29: Tx Packet with a DSA Tag Example (FROM_CPU format, use_vidx = 0) .143 Figure 30: MII Connection.150 Figure 31: GMII Connection .152 Figure 32: RGMII Pin Interconnection Between MAC and PHY .152 Figure 33: PTP Common Header Format .160 Figure 34: PTP over UDP Frame .161 Figure 35: PTP 2.1 Pipe Block Diagram .162 Figure 36: 10 Ethernet Frame Classification.170 Figure 38: 9 Time Stamping Pipeline Stages.164 Figure 37: Bad Frame Procedure .171 Universal Serial Bus (USB 2.0) Interface . 173 Cryptographic Engines and Security Accelerator (CESA) . 174 Figure 39: Authentication of a Data Chunk .178 Figure 40: Typical Authentication Flow for a Packet .179 Figure 41: DES Engine Pipeline .181 Figure 42: Typical DES/3DES Encryption Flow for Packet .184 Figure 43: Typical AES Decryption Flow for a Data Block .189 Figure 45: Security Accelerator Main Decision Flow .190 Figure 46: Security Acceleration Flow for Packet Processing.191 Figure 47: Security Acceleration Flow for Packet Processing-Enhanced Mode.192 Figure 48: TDMA Descriptors Structure for Security Accelerator Packet Processing in Enhanced Mode .193 Figure 49: TDMA Descriptors .201 Figure 50: 11 Typical AES Encryption Flow for a Data Block .187 Figure 44: Chained Mode TDMA .203 XOR Engine . 205 Figure 51: Schematic Diagram of the Two XOR Engines .205 Figure 52: XOR Operation with Multiple Incoming Data Blocks.207 Figure 53: XOR iSCSI CRC32C CRC32C Operation.208 Figure 54: XOR Descriptor Format .210 Figure 55: 12 Programmable Channel Pizza Arbiter .214 Figure 56: Software and Hardware Synchronization .218 Two-Wire Serial Interface (TWSI) . 221 Figure 57: TWSI Examples .222 Doc. No. MV-S104860-U0 MV-S104860-U0 Rev. C Page 14 Copyright © 2008 Marvell Document Classification: Proprietary Information December 2, 2008, Preliminary List of Figures 13 UART Interface. 228 Figure 58: 14 Example UART Data Frame (Two Stop Bits).229 Figure 59: Example UART Data Frame (One Stop Bit) .229 8-bit NAND Flash Interface . 231 Figure 60: 8-bit NAND Flash Read Parameters Example.233 Figure 61: 8-bit NAND Flash Write Parameters Example .234 15 Serial Peripheral Interface (SPI) . 236 16 Audio (I2S / S/PDIF) Interface (88F6180 88F6180, 88F6192 88F6192, and 88F6281 88F6281 Only) . 240 Figure 62: Figure 63: Recording Flow .244 Figure 64: Playback Flow.249 Figure 65: 17 Audio Unit Block Diagram .240 Memory Structure for Transmit and Receive .254 Secure Digital Input/Output (SDIO) Interface . 256 Figure 66: 18 SD_MMC Host Controller Hardware Block Diagram .256 Figure 67: Host Initialization Flow .258 Transport Stream (TS) Interface (88F6192 88F6192 and 88F6281 88F6281 Only). 262 Figure 68: TSU Block Diagram .262 Figure 69: TS Interface Block Diagram .263 Figure 70: TS Parallel Protocol (Example).266 Figure 71: TS Continuous Serial Data Protocol (Example) .266 Figure 72: TS Input Descriptor Queue .269 Figure 73: TS Output Descriptor Structure-No Packet Aggregation .270 Figure 74: TS Output Descriptor Queue-No Packet Aggregation.271 Figure 75: Impact of Timestamp on the Average TS Data Output Data Rate.273 Figure 76: Aggregated TS Input Mode.274 Figure 77: Aggregated TS Output Mode .275 Figure 78: TS Loopback Modes.276 19 General-Purpose I/O (GPIO) Port Interface . 277 20 Real-Time Clock (RTC) Unit . 278 21 Interrupt Controller. 280 Figure 79: Device Interrupt Controller Scheme.282 Copyright © 2008 Marvell December 2, 2008, Preliminary Doc. No. MV-S104860-U0 MV-S104860-U0 Rev. C Document Classification: Proprietary Information Page 15 88F6180/88F619x/88F6281 Functional Specifications 22 Timers and Counters. 283 23 eFuse . 286 24 System Considerations. 288 Figure 80: Binary Image Layout in the Boot Device.292 Figure 81: Initialization and Boot Method Selection Flow .296 Figure 82: 25 Header Decoding, DDR Initialization, and Image Execution Flowchart .299 Figure 83: Endpoint Power Supply Control .307 Internal Architecture. 312 Figure 84: 88F6180 88F6180 and 88F619x Bus Interface Unit Mbus-L Block Diagram.312 Figure 85: CPU to DDR Mbus-L Timing Diagrams-CPU2MbusLTickDrv=0, CPU2MbusLTickSample=0.314 Figure 87: CPU to DDR Mbus-L Timing Diagrams-CPU2MbusLTickDrv=2, CPU2MbusLTickSample=2 .314 Figure 88: A 88F6281 88F6281 Bus Interface Unit Mbus-L Block Diagram.313 Figure 86: Masters Request Default Arbitration Cycle .316 88F6180/88F619x/88F6281 Register Set .352 Figure 89: PTP Configuration Data Structure Registers .600 Figure 90: PTP Global Status Data Structure Registers .602 Figure 91: PTP Port Configuration Data Structure Registers .603 Figure 92: PTP Port Status Data Structure Registers.607 Figure 93: B TAI Global Configuration Data Structure .615 Figure 94: PTP Time Application Interface Global Status Data Structure.620 Revision History .786 Doc. No. MV-S104860-U0 MV-S104860-U0 Rev. C Page 16 Copyright © 2008 Marvell Document Classification: Proprietary Information December 2, 2008, Preliminary Preface About this Document Preface About this Document This document provides the functional specifications for the 88F6180 88F6180, 88F6190 88F6190, 88F6192 88F6192, and 88F6281 88F6281 integrated controllers. This datasheet also provides detailed definitions for the registers implemented in these devices. This document is intended to be the basic source of information for designers of new systems. All feature descriptions and specifications described in this document refer to all the devices, unless otherwise specified. In this document, the 88F6180 88F6180, 88F6190 88F6190, 88F6192 88F6192, and 88F6281 88F6281 are often referred to as "the device/s". In addition, the 88F6190 88F6190 and 88F6192 88F6192 are often referred to as the 88F619x. Relevant Devices 88F6180 88F6180 88F6190 88F6190 88F6192 88F6192 88F6281 88F6281 Related Documentation The following documents contain additional information related to the 88F6180 88F6180,88F619x, and 88F6281 88F6281: 88F6180 88F6180 Hardware Specifications, Doc No. MV-S104988-U0 MV-S104988-U0 88F6190 88F6190 and 88F6192 88F6192 Hardware Specifications, Doc No. MV-S104987-U0 MV-S104987-U0 88F6281 88F6281 Hardware Specifications, Doc No. MV-S104859-U0 MV-S104859-U0 88F6180 88F6180, 88F6190 88F6190, 88F6192 88F6192, and 88F6281 88F6281 Design Guide, Doc No. MV-S301398-001 MV-S301398-001 SheevaTM 88SV131 88SV131 ARM v5TE Processor Core with MMU and L1/L2 Cache Datasheet, Doc No. MV-S104950-U0 MV-S104950-U0 Unified Layer 2 (L2) Cache for SheevaTM CPU Cores Addendum, Doc No. MV-S104858-U0 MV-S104858-U0 AN-179 AN-179 TWSI Software Guidelines for DiscoveryTM, HorizonTM, and Feroceon® Devices, Doc No. MV-S300754-001 MV-S300754-001 AN-183 AN-183, 88F5181 88F5181 and 88F5281 88F5281 Big Endian and Little Endian Support, Doc No. MV-S300767-001 MV-S300767-001 AN-249 AN-249: Configuring the Marvell® SATA PHY to Transmit Predefined Test Patterns, Doc No. MV-S301342-001 MV-S301342-001 AN-260 AN-260 System Power-Saving Methods for 88F6180 88F6180, 88F6190 88F6190, 88F6192 88F6192, and 88F6281 88F6281, Doc No. MV-S301454-001 MV-S301454-001 TB-227 TB-227: Differences Between the 88F6192 88F6192, and 88F6281 88F6281 Stepping Z0 and A0, Doc No. MV-S105223-001 MV-S105223-001 ARM Architecture Reference Manual, Second Edition PCI Express Base Specification, Revision 1.1 Universal Serial Bus Specification, Revision 2.0, April 2000, Compaq, Hewlett-Packard, Intel, Lucent, Microsoft, NEC, Philips 1. This document is a Marvell proprietary, confidential document, requiring an NDA and can be downloaded from the Marvell Extranet. Copyright © 2008 Marvell December 2, 2008, Preliminary Doc. No. MV-S104860-U0 MV-S104860-U0 Rev. C Document Classification: Proprietary Information Page 17 88F6180/88F619x/88F6281 Functional Specifications Enhanced Host Controller Interface Specification for Universal Serial Bus, Revision 0.95, November 2000, Intel Corporation ARC USB-HS OTG High-Speed USB On-The-Go Controller Core V 4.0.1 Reference. Federal Information Processing Standards (FIPS) 46-2 (Data Encryption Standard) FIPS 81 (DES Modes of Operation) FIPS 180-1 (Secure Hash Standard) FIPS draft - Advanced Encryption Standard (Rijndeal) RFC 1321 (The MD5 Message-Digest Algorithm) RFC 1851 ­ The ESP Triple DES Transform RFC 2104 (HMAC: Keyed-Hashing for Message Authentication). RFC 2405 ­ The ESP DES-CBC Cipher Algorithm With Explicit IV IEEE standard, 802.3-2000 Clause 14 ANSI standard X3.263-1995 See the Marvell Extranet website for the latest product documentation. Doc. No. MV-S104860-U0 MV-S104860-U0 Rev. C Page 18 Copyright © 2008 Marvell Document Classification: Proprietary Information December 2, 2008, Preliminary Preface Document Conventions Document Conventions The following conventions are used in this document: ns Signal Range A signal name followed by a range enclosed in brackets represents a range of logically related signals. The first number in the range indicates the most significant bit (MSb) and the last number indicates the least significant bit (LSb). Example: DB_Addr[12:0] Active Low Signals # An n letter at the end of a signal name indicates that the signal's active state occurs when voltage is low. Example: INTn State Names State names are indicated in italic font. Example: linkfail Register Naming Conventions Register field names are indicated by angle brackets. Example: Register field bits are enclosed in brackets. Example: Field [1:0] Register addresses are represented in hexadecimal format. Example: 0x0 Reserved: The contents of the register are reserved for internal use only or for future use. A lowercase in angle brackets in a register indicates that there are multiple registers with this name. Example: Multicast Configuration Register Reset Values Reset values have the following meanings: 0 = Bit clear 1 = Bit set Abbreviations Gb: gigabit GB: gigabyte Kb: kilobit KB: kilobyte Mb: megabit MB: megabyte Numbering Conventions Unless otherwise indicated, all numbers in this document are decimal (base 10). An 0x prefix indicates a hexadecimal number. An 0b prefix indicates a binary number. Copyright © 2008 Marvell December 2, 2008, Preliminary Doc. No. MV-S104860-U0 MV-S104860-U0 Rev. C Document Classification: Proprietary Information Page 19 88F6180/88F619x/88F6281 Functional Specifications 1 Overview The Marvell® 88F6180 88F6180, 88F6190 88F6190, 88F6192 88F6192, and 88F6281 88F6281 devices are high-performance, highly integrated controllers. The devices are based on the ARMv5TE-compliant, high-speed Marvell® SheevaTM 88SV131 88SV131 CPU core with 256 KB L2 cache. This section provides a brief description of the interfaces in each of these devices. Note The functions, interfaces, and registers/register bits described in this document do not necessarily apply to all of the devices. Doc. No. MV-S104860-U0 MV-S104860-U0 Rev. C Page 20 Copyright © 2008 Marvell Document Classification: Proprietary Information December 2, 2008, Preliminary Overview Block Diagrams 1.1 Block Diagrams Figure 1 is a block diagram of the 88F6180 88F6180 interfaces. Figure 1: 88F6180 88F6180 Interface Block Diagram Dual Channel 16-bit up to 400 MHz data rate DDR2 SDRAM Controller PCI Express with integrated SERDES x1 port Gigabit Ethernet x1 port SheevaTM 88SV131 88SV131 CPU core 600 MHz or 800 MHz 16 KB L1 D-cache 16 KB L1 I-cache USB 2.0 with integrated PHY 256 KB L2 cache up to 400 MHz Mbus-L Local bus 64-bit Mbus-L to Mbus Bridge up to 200 MHz Security engine Mbus 64-bits @ 166 MHz XOR / DMA x4 channels TWSI, SPI, UART x2, MPP, NAND Flash, BootROM S/PDIF / I2S Audio interface SDIO interface Copyright © 2008 Marvell December 2, 2008, Preliminary Doc. No. MV-S104860-U0 MV-S104860-U0 Rev. C Document Classification: Proprietary Information Page 21 88F6180/88F619x/88F6281 Functional Specifications Figure 2 is a block diagram of the 88F6190 88F6190 interfaces. Figure 2: 88F6190 88F6190 Interface Block Diagram Dual Channel 16-bit up to 400 MHz data rate DDR2 SDRAM Controller PCI Express with integrated SERDES x1 port SATA II with integrated PHYs x1 port Gb Ethernet x1 port, Fast Ethernet x1 port SheevaTM 88SV131 88SV131 CPU core 600 MHz 16 KB L1 D-cache 16 KB L1 256 KB L2 cache Mbus-L Local bus 64-bit up to 300 MHz up to 200 MHz Mbus-L to Mbus Bridge Mbus 64-bits @ 166 MHz USB 2.0 with integrated PHY Security engine I-cache XOR / DMA x4 channels TWSI, SPI, UART x2, MPP, NAND flash, BootROM SDIO interface Doc. No. MV-S104860-U0 MV-S104860-U0 Rev. C Page 22 Copyright © 2008 Marvell Document Classification: Proprietary Information December 2, 2008, Preliminary Overview Block Diagrams Figure 3 is a block diagram of the 88F6192 88F6192 interfaces. Figure 3: 88F6192 88F6192 Interface Block Diagram Dual Channel 16-bit up to 400 MHz data rate DDR2 SDRAM Controller TDM SLIC/Codec interface PCI Express with integrated SERDES x1 port SATA II with integrated PHYs x2 ports Gigabit Ethernet x2 ports SheevaTM 88SV131 88SV131 CPU core 16 KB L1 D-cache 800 MHz 16 KB L1 I-cache 256 KB L2 cache up to 400 MHz Mbus-L Local bus 64-bit USB 2.0 with integrated PHY Mbus-L to Mbus Bridge up to 200 MHz Mbus 64-bits @ 166 MHz Security engine XOR / DMA x4 channels TWSI, SPI, UART x2, MPP, NAND flash, BootROM S/PDIF / I2S Audio interface SDIO interface TS/Video interface Copyright © 2008 Marvell December 2, 2008, Preliminary Doc. No. MV-S104860-U0 MV-S104860-U0 Rev. C Document Classification: Proprietary Information Page 23 88F6180/88F619x/88F6281 Functional Specifications Figure 4 is a block diagram of the 88F6281 88F6281 interfaces. Figure 4: 88F6281 88F6281 Interface Block Diagram Dual Channel 16-bit up to 800 MHz data rate DDR2 SDRAM Controller TDM SLIC/Codec interface PCI Express with integrated SERDES x1 port SATA II with integrated PHYs x2 ports Gigabit Ethernet x2 ports SheevaTM 88SV131 88SV131 CPU core 1.0 GHz, 1.2 GHz, or 1.5 GHz 16 KB L1 D-cache 16 KB L1 I-cache 256 KB L2 cache up to 500 MHz Mbus-L Local bus 64-bit USB 2.0 with integrated PHY Mbus-L to Mbus Bridge up to 400 MHz Mbus 64-bits @ 200 MHz Security engine XOR / DMA x4 channels TWSI, SPI, UART x2, MPP, NAND flash, BootROM S/PDIF / I2S Audio interface SDIO interface TS/Video interface Doc. No. MV-S104860-U0 MV-S104860-U0 Rev. C Page 24 Copyright © 2008 Marvell Document Classification: Proprietary Information December 2, 2008, Preliminary Overview Overview of Functions and Interfaces 1.2 Overview of Functions and Interfaces The following is a list of the device functions and interfaces: SheevaTM 88SV131 88SV131 CPU The device integrates the Sheeva 88SV131 88SV131 CPU core. This core is compliant with ARMv5TE Core architecture, as published in the ARM Architecture Reference Manual, Second Edition. The Sheeva 88SV131 88SV131 CPU core provides integrated 16/16 KB, four-way, set-associative I/D L1 caches and a unified 256 KB four-way, set-associative L2 cache. 88F6180 88F6180: Running at 600 MHz or 800 MHz 88F6190 88F6190: Running at 600 MHz 88F6192 88F6192: Running at 800 MHz 88F6281 88F6281: Running at 1.0 GHz, 1.2 GHz, or 1.5 GHz The Sheeva 88SV131 88SV131 CPU core also provides: 32-bit and 16-bit RISC architecture An MMU to support virtual memory features 64-bit internal data bus Branch Prediction Unit JTAG/ARM ICE support Big and Little Endian modes support See Section 3, SheevaTM CPU Core, on page 43. DDR SDRAM Interface The device integrates a 16-bit DDR2 SDRAM interface. 88F6180 88F6180 and 88F619x Up to 200 MHz clock frequency with an 400 MHz data rate Supports two DRAM chip selects Supports all DDR2 devices with densities up to 1 Gb Supports up to 16 open pages (page per bank) Up to 512 MB total address space 88F6281 88F6281 Up to 400 MHz clock frequency with an 800 MHz data rate Supports four DRAM chip selects Supports all DDR2 devices with densities up to 2 Gb Supports up to 32 open pages (page per bank) Up to 2 GB total address space All of the devices Provide the following DDR SDRAM interface features: Support for on board DDR designs (no DIMM support) DDR SDRAM with a clock ratio of 1:N and 2:N between the DDR SDRAM and the CPU core, respectively SSTL 1.8V I/Os Auto calibration of I/Os output impedance Support for 2T mode to enable high-frequency operation with a heavy load configuration Supports DRAM bank interleaving Supports up to a 128-byte burst per single memory access See Section 4, DDR SDRAM Controller, on page 44. Copyright © 2008 Marvell December 2, 2008, Preliminary Doc. No. MV-S104860-U0 MV-S104860-U0 Rev. C Document Classification: Proprietary Information Page 25 88F6180/88F619x/88F6281 Functional Specifications Time Division Multiplexing (SLIC/SLAC/Codec) Interface The 88F6192 88F6192 and 88F6281 88F6281 contain a Time Division Multiplexing (SLIC/SLAC/Codec) interface. The TDM is a generic interface to the standard SLIC/SLAC/codec devices. It provides: Compatibility with standard PCM highway formats TDM protocol support for two channels, up to 128 time slots SPI interface for codec register read/write access Two integrated DMA engines to transfer voice data to/from memory buffer See Section 5, Time Division Multiplexing (TDM) Unit (88F6192 88F6192 and 88F6281 88F6281 Only), on page 56. PCI Express Interface The device integrates a PCI Express Base 1.1 compatible interface containing a single PCI Express lane (x1) host port with an integrated low power SERDES, based on Marvell® SERDES technology. This interface can serve as a Root Complex or an Endpoint port with: x1 lane width 2.5 Gbps data rate Lane polarity reversal support Maximum payload size of 128 bytes Single Virtual Channel (VC-0) Replay buffer support Extended PCI Express configuration space Advanced Error Reporting (AER) support Power management: L0s and software L1 support Interrupt emulation message support Error message support As a master, the PCI Express interface contains: Single outstanding read transaction Maximum read request of up to 128 bytes Maximum write request of up to 128 bytes Up to four outstanding read transactions in Endpoint mode As a target, the PCI Express interface contains: Supports up to eight read request transactions Maximum read request size of 4 KB Maximum write request of 128 bytes Supports PCI Express access to all of the device's internal registers See Section 6, PCI Express Interface, on page 74. Doc. No. MV-S104860-U0 MV-S104860-U0 Rev. C Page 26 Copyright © 2008 Marvell Document Classification: Proprietary Information December 2, 2008, Preliminary Overview Overview of Functions and Interfaces Serial ATA II (SATA II) Interface The 88F6192 88F6192 and 88F6281 88F6281 contain two and the 88F6190 88F6190 contains one SATA II compliant 3 Gbps (Gen2i) SATA PHY(s). The SATA interface supports: SATA II Native command queuing, up to 128 outstanding commands per port First party DMA (FPDMA) full support Backwards compatibility to SATA I 1.5-Gbps speed and devices Fully supports the SATA II Phase 1.0 specification, and the following advanced SATA II Phase 2.0 specification features: · 3 Gbps (Gen2i) SATA II speed · SATA II Port Multiplier performs FIS-Based Switching as defined in SATA working group Port Multiplier definition · SATA II Port Selector issues the protocol-based OOB sequence to select the active host port Supports device 48-bit addressing Supports ATA Tag Command Queuing The SATA Host Controller supports: Enhanced-DMA [EDMA] for the SATA ports Automatic command execution without host intervention Command queuing support, for up to 32 outstanding commands Separate SATA request/response queues 64-bit addressing support for descriptors and data buffers in system memory Read ahead Advanced interrupt coalescing Target mode operation-Two devices can be attached back-to-back, through Serial ATA ports, enabling data communication between different 88F619x/88F6281 devices, with one acting as a host and the other emulate a device Advanced drive diagnostics via the ATA SMART command See Section 7, Serial-ATA (SATA) II Interface (88F619x and 88F6281 88F6281 Only), on page 89. Copyright © 2008 Marvell December 2, 2008, Preliminary Doc. No. MV-S104860-U0 MV-S104860-U0 Rev. C Document Classification: Proprietary Information Page 27 88F6180/88F619x/88F6281 Functional Specifications Gigabit Ethernet Interface 88F6180 88F6180 The Gigabit Ethernet interface consists of a single full-duplex Gigabit Ethernet (GbE) port that supports an RGMII/MII/MMII interface. 88F6190 88F6190 The Gigabit Ethernet interface consists of one full-duplex Gigabit Ethernet (GbE) port and one full-duplex Fast Ethernet (FE) port that supports the following modes: · Port0 RGMII, Port1 MII/MMII · Port0 GMII, Port1 N/A 88F6192 88F6192 and 88F6281 88F6281 The Gigabit Ethernet interface consists of two full-duplex Gigabit Ethernet (GbE) ports that support the following modes: · · · · Port0 RGMII, Port1 RGMII Port0 RGMII, Port1 MII/MMII Port0 MII/MMII, Port1 RGMII Port0 GMII, Port1 N/A The Gigabit Ethernet interface supports 10/100/1000 Mbps speeds, as well as the 200 Mbps proprietary Marvell® MII (MMII). Receive and transmit buffer management is based on buffer-descriptor linked lists. Data transfers are performed by the port dedicated SDMA (see Section 8.3, DMA Functionality, on page 116). Each Ethernet port includes advanced Destination Address (DA) filtering on received packets that also detects packet type/encapsulations that can be used by the CPU for packet routing: Layer 2: BPDU,VLAN (programmable VLAN-EtherType), Ethernet v2, LLC/SNAP Layer 3: IPv4, IPv6 (according to Ethertype), other Layer 4 (only over IPv4): TCP and UDP The port has eight receive priority queues. Queuing is performed based on DA, VLAN-Tag, IP-TOS, Marvell Header, and DSA Tag. The port supports standard Ethernet frames (up to 1.5 KB) and, in addition, Jumbo frames (up to 9 KB). It also supports hardware TCP and UDP checksum check on receive, and generate on transmit (checksum generation for Jumbo frames is not supported). Precise Timing Protocol (PTP) with: · Precise time stamping for packets, as defined in IEEE 1588 PTP v1 and v2 and IEEE 802.1AS draft standards · Flexible Time Application interface to distribute PTP clock and time to other devices in the system · Optionally accepts an external clock input for time stamping Audio Video Bridging Networks including: · IEEE 802.1Qav pre-draft Audio Video Bridging networks · Time- and priority-aware egress pacing algorithm to prevent bunching and bursting effects-suitable for audio/video applications · Egress Jitter Pacer for AVB-Class A and AVB-Class B traffic and strict priority for legacy traffic queues See Section 8, Gigabit Ethernet Controller, on page 113. Doc. No. MV-S104860-U0 MV-S104860-U0 Rev. C Page 28 Copyright © 2008 Marvell Document Classification: Proprietary Information December 2, 2008, Preliminary Overview Overview of Functions and Interfaces USB 2.0 Interface The device integrates a single USB 2.0 compliant high-speed port with an integrated PHY: Serves as a peripheral or host Enhanced Host Controller Interface (EHCI) compatible as a host As a host, supports direct connection to all peripheral types (LS, FS, HS) As a peripheral, connects to all host types (HS, FS) and hubs Integrates up to four independent Endpoints that support control, interrupt, bulk, and isochronous data transfers Integrates a dedicated DMA for data movement between memory and port See Section 9, Universal Serial Bus (USB 2.0) Interface, on page 173. Cryptographic Engine The device integrates a Cryptographic Engine and Security Accelerator to support data and Security encryption and authentication. It also contains a dedicated Direct Memory Access (DMA) Accelerator controller to perform the following: Hardware implementation of encryption and authentication engines to boost packet processing speed Dedicated DMA to feed the hardware engines with data from the internal SRAM memory or from the DDR memory Implements AES, DES, and 3DES encryption algorithms Implements SHA1 and MD5 authentication algorithms See Section 10, Cryptographic Engines and Security Accelerator (CESA), on page 174. XOR / DMA Channel The device integrates four XOR / DMA channels. Each channel has the capability to transfer data between the interfaces. The channels: Support chaining via linked-lists of descriptors Move data from source interface to destination interface Support increment or hold of source and/or destination address Support XOR operation on up to eight source blocks, useful for RAID application Support iSCSI CRC-32 CRC-32 calculation See Section 11, XOR Engine, on page 205. Two-Wire Serial Interface (TWSI) The device contains a single Two-Wire Serial Interface (TWSI) port that can be configured as either a master or a slave interface. This port can also be used for serial ROM initialization. The TWSI fully supports multiple TWSI master environments (clock synchronization, bus arbitration). The TWSI interface can be used for multiple applications such as a master to control other TWSI on board devices and to auto-load values from an external serial ROM device. It can be used as a slave for communication with some other TWSI masters See Section 12, Two-Wire Serial Interface (TWSI), on page 221. UART Interface The device supports a Universal Asynchronous Receiver/Transmitter (UART) Interface that consists of two Synopsis DW_16550 compatible UART ports. The UART interface integrates: Two pins for transmit and receive operations Two pins for modem control functions See Section 13, UART Interface, on page 228. NAND Flash Interface The device implements an 8-bit NAND Flash interface to boot from NAND Flash, or for any other non-volatile memory usage. The NAND Flash interface provides a glueless interface to CE care and CE don't care type NAND Flash devices. See Section 14, 8-bit NAND Flash Interface, on page 231. Copyright © 2008 Marvell December 2, 2008, Preliminary Doc. No. MV-S104860-U0 MV-S104860-U0 Rev. C Document Classification: Proprietary Information Page 29 88F6180/88F619x/88F6281 Functional Specifications SPI Serial Flash Interface The device implements an SPI interface for direct boot from external SPI flash memory. This interface operates at up to 41.6 MHz in the 88F6180 88F6180 and 88F619x, and up to 50 MHz in the 88F6281 88F6281. See Section 15, Serial Peripheral Interface (SPI), on page 236. 2 Audio I S / S/PDIF Interface The 88F6180 88F6180, 88F6192 88F6192, and 88F6281 88F6281 contain an I2S / S/PDIF interface for audio in and audio out: Either I2S / S/PDIF inputs can be active at one time Both I2S or S/PDIF outputs can be simultaneously active (transferring the same PCM data) This interface supports the following I2S and S/PDIF specific features: I2S specific features: · Sample rates of 44.1/48/96 kHz · I2S input and I2S output operate at the same sample rate · 16/24-bit depths · I2S in and I2S out support Independent bit depths (16 bit/24 bit) · Supports plain I2S, right justified and left justified formats S/PDIF specific features: · Compliant to IEC 60958-1, IEC 60958-3, and IEC 61937 specifications · Sample rates of 44.1/48/96 kHz · 16/20/24-bit depths See Section 16, Audio (I2S / S/PDIF) Interface (88F6180 88F6180, 88F6192 88F6192, and 88F6281 88F6281 Only), on page 240. SDIO Interface The device integrates an SD/SDIO/MMC host interface that operates at up to 50 MHz.This interface supports: 1-bit/4-bit SDMem, SDIO, and MMC cards Hardware generate/check CRC on all command and data transaction on the card bus MPEG Video / Transport Stream Interface (TS) The 88F6192 88F6192 and 88F6281 88F6281 implement an MPEG Video / TS interface of up to 80 Mbps. See Section 17, Secure Digital Input/Output (SDIO) Interface, on page 256. It is ISO/IEC 13818-1 standard compliant, supports any of the following modes: Parallel (8 bit) input Parallel (8 bit) output Two independent serial interfaces See Section 18, Transport Stream (TS) Interface (88F6192 88F6192 and 88F6281 88F6281 Only), on page 262. General-Purpose I/O Port (GPIO) 88F6180 88F6180 provides a 30-bit general-purpose I/O port 88F619x provides a 36-bit general-purpose I/O port 88F6281 88F6281 provides a 50-bit general-purpose I/O port Each of these general-purpose I/O pins can be used for peripheral functions or for general-purpose I/O. Each pin can be configured independently GPIO inputs can be used to register interrupts from external devices, and generate maskable interrupts See Section 19, General-Purpose I/O (GPIO) Port Interface, on page 277. Doc. No. MV-S104860-U0 MV-S104860-U0 Rev. C Page 30 Copyright © 2008 Marvell Document Classification: Proprietary Information December 2, 2008, Preliminary Overview Differences Between the 88F6180 88F6180, 88F6190 88F6190, 88F6192 88F6192, and 88F6281 88F6281 Devices Real-Time Clock (RTC) The device integrates a real-time clock that records second, minute, hour, date, day, month, and year. While the system power is off, a backup battery (1.5V­1.8V) can operate the RTC unit. The RTC unit operates with an external 32.768 kHz crystal. See Section 20