PUMA84SV64000 84SV64000 -40OC ICC32 ICC16 I-012 - Datasheet Archive

 

Description The PUMA 84 range of devices provide a high density, surface mount memory solution with density up to twice that of

 

Issue 1.1 November 2002 Description The PUMA 84 range of devices provide a high density, surface mount memory solution with density up to twice that of standard monolithic devices. Block Diagram A0 ~A20 /OE /CS1 /WE1 2M x 8 /CS2 /WE2 2M x 8 The device is available to commercial and industrial temperature grade. /CS3 /WE3 2M x 8 Features /CS4 /WE4 2M x 8 The PUMA 84 may accomodate various memory technologies including SRAM, FLASH and EEPROM. The devices are designed to offer a defined upgrade path and may be user configured as 8, 16 or 32 bits wide using four Chip Selects (/CS1~4). The PUMA84SV64000 PUMA84SV64000 is a 2Mx32 SRAM module housed in a JEDEC 84 pin surface mount J-leaded PLCC. Access times of 12, 15 or 20ns are available. ï Access times of 12/15/20 ns. ï 3.3V + 10%. ï Comercial and Industrial temperature grades ï JEDEC 84 ëJí Leaded surface mount package. ï May be organised as 2M x 32, 4M x 16 and 8M X 8 ï Operating Power (32 Bit) 6.34W (max) ï Low power standby. (CMOS) 90mW (max) ï Completely Static Operation. Package Details PUMA 84 - Plastic 84 ëJí Leaded Package. Max. Dimensions - 30.35 x 30.35 x 5.08 (max) All Dimensions in mm. D0 ~ 7 SRAM D8 ~ 15 SRAM D16 ~ 23 SRAM D24 ~ 31 SRAM Pin Definition See page 2. Pin Functions Description Signal Address Input Data Input/Output Chip Select Write Enable Output Enable No Connect Power Ground A0~A20 D0~D31 /CS1~4 /WE1~4 /OE NC VCC GND Elm Road, West Chirton Industrial Estate, North Shields, NE29 8SE, England. TEL +44 (0191) 2930500. FAX +44 (0191) 2590997 E-mail: sales@hmpeurope.com 2M x 32 Static RAM PUMA 84SV64000 84SV64000 - 012/015/020 Pin Definition - PUMA84SV64000 PUMA84SV64000 11 Pin Pin Signal 1 VCC 43 /WE2 44 /CS1 45 /CS2 46 A11 5 /CS3 47 A10 6 /CS4 48 A9 7 A17 49 A8 8 A18 50 A7 9 D16 51 D0 10 A19 52 /WE4 11 A20 53 NC 12 NC 54 NC 13 NC 55 NC 14 D17 56 D1 15 D18 57 D2 16 D19 58 D3 17 GND 59 GND 18 D20 60 D4 19 D21 61 D5 20 D22 62 D6 21 D23 63 D7 22 VCC 64 VCC 23 D24 65 D8 24 D25 66 D9 25 D26 67 D10 26 D27 68 D11 27 GND 69 GND 28 D28 70 D12 29 D29 71 D13 30 D30 72 D14 31 NC 73 NC 32 NC 74 NC 33 NC 75 D15 34 /WE3 76 A14 35 D31 77 A15 36 A6 78 A16 37 A5 79 /WE1 38 A4 80 /OE 39 A3 81 NC 40 A2 82 NC 41 A1 83 NC 42 A0 84 74 12 A12 4 75 A13 3 84 VCC 2 PAGE 2 Signal 1 NC VIEW FROM ABOVE 54 32 33 53 Issue 1.1 November 2002 Absolute Maximum Ratings(1) Symbol Voltage on any pin relative to VSS VT Power Dissipation TSTG Max PT Storage Temperature Min -0.5 +4.6 to Unit V 7.2 -55 W to O +125 C Notes : (1) Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability Recommended Operating Conditions Parameter Symbol Min Typ Max Unit Supply Voltage VCC 3.0 3.3 3.6 V Input High Voltage VIH 2.0 - VCC+0.3 V Input Low Voltage VIL -0.3 - 0.8 V Operating Temperature TA 0 - 70 O TAI -40 - 85 O C C (I Suffix) DC Electrical Characteristics (VCC=3.3V+10%, TA=-40OC -40OC to +85OC) Parameter Symbol Test Condition Min Typ Max Units Input Leakage Current ILI VIN = GND to VCC -8 - 8 µA Output Leakage Current ILO /CS=VIH or /OE=VIH or /WE=VIL, VOUT= GND to VCC -8 - 8 µA 32 Bit ICC32 ICC32 Min. Cycle, 100% Duty /CS=VIL, VIN=VIH or VIL, IOUT=0mA - - 1760 mA 16 Bit ICC16 ICC16 As Above. - - 1120 mA 8 Bit ICC8 As Above. - - 800 mA TTL ISB Min. Cycle, /CS=VIH - - 480 mA CMOS ISB1 f=0MHz, /CSVCC-0.2V, VINVCC-0.2V or VIN 0.2V - - 25 mA IOL=2.0mA - - 0.4 V 0.2 V - V Operating Supply Current Standby Supply Current Output Voltage Low VOL Output Voltage High VOH Notes PAGE 3 IOL= 100µA IOH= -2.0mA 2.4 - IOH= -100µA VCC-0.2 V (1) /CS should be used in pairs for 16 bit mode or use /CS1~4 for 32 bit operation. Issue 1.1 November 2002 DC Operating Conditions Parameter Capacitance (VCC = 3.3V + 10%, TA = 25OC) Parameter Symbol Test Condition Min Typ Max Unit Input Capacitance Address, /OE CIN1 VIN=0V - - 34 pF Input Capacitance /CS1~4, /WE1~4 CIN2 VIN=0V - - 18 pF 8 bit mode (worst case) CI/O VI/O=0V - - 42 pF Output Capacitance Note : These Parameters are calculated not measured. Test Conditions ï ï ï ï ï Output Load Input pulse levels : 0V to 3.0V Input rise and fall times : 2ns Input and Output timing reference levels : 1.5V Output Load : See Load Diagram. VCC = 3.3V+10% I/O Pin 166 1.76V 30pF Operation Truth Table /CS /OE /WE Data Pins Supply Current Mode H X X High Impedance ISB,ISB1 Standby L L H Data Out ICC32 ICC32,ICC16 ICC16,ICC8 Read L H L Data In ICC32 ICC32,ICC16 ICC16,ICC8 Write L L L Data In ICC32 ICC32,ICC16 ICC16,ICC8 Write L H H High Impedance ICC32 ICC32,ICC16 ICC16,ICC8 High Z Notes : H = VIH : L = VIL : X = VIH or VIL PAGE 4 Issue 1.1 November 2002 012 Parameter 015 020 Symbol Min Max Min Max Min Max Units Read Cycle Time tRC 12 - 15 - 20 - ns Address Access Time tAA - 12 - 15 - 20 ns Chip Select Access Time tACS - 12 - 15 - 20 ns Output Enable to Output Valid tOE - 6 - 8 - 10 ns Output Hold From Address Change tOH 3 - 3 - 3 - ns Chip Selection to Output in Low Z tCLZ 3 - 3 - 3 - ns Output Enable to Output in Low Z tOLZ 0 - 0 - 0 - ns Chip Deselection to Output in High Z tCHZ 0 7 0 8 0 9 ns Output Disable to Output in High Z tOHZ 0 7 0 8 0 9 ns Write Cycle 012 Parameter Symbol 015 020 Min Max Min Max Min Max Units Write Cycle Time tWC 12 - 15 - 20 - ns Chip Selection to End of Write tCW 10 - 12 - 15 - ns Address Valid to End of Write tAW 10 - 12 - 15 - ns Address Setup Time tAS 0 - 0 - 0 - ns Write Pulse Width tWP 8 - 10 - 12 - ns Write Recovery Time tWR 0 - 0 - 0 - ns Write to Output in High Z tWHZ 0 7 0 8 0 9 ns Data to Write Time Overlap tDW 7 - 8 - 9 - ns Data Hold time from Write Time tDH 0 - 0 - 0 - ns Output Active from End of Write tOW 1 - 1 - 1 - ns PAGE 5 Issue 1.1 November 2002 AC Operating Conditions Read Cycle (Address Controlled, /CS=/OE=VIL, /WE=VIH) tRC Address tAA tOH Data Out Previous Data Valid Data Valid Read Cycle 2 (/WE = VIH) tRC Address tAA tCO tHZ(3,4,5) /CS tOHZ tOE /OE tOLZ tOH tLZ(4,5) Valid Data Data Out VCC Current ICC ISB tPU tPD 50% 50% NOTES(READ CYCLE) 1. /WE is high for read cycle. 2. All read cycle timing is referenced from the last valid address to the first transition address. 3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or VOL levels. 4. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device. 5. Transition is measured ±200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested. 6. Device is continuously selected with /CS=VIL. 7. Address valid prior to coincident with /CS transition low. 8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. Note: /CS = /CS1~4, /WE = /WE1~4 PAGE 6 Issue 1.1 November 2002 Timing Waveforms Read Cycle 1 Write Cycle 1 (/OE = Clock) tWC Address tAW tWR(5) /OE tCW(3) /CS tAS(4) tWP(2) /WE tDW tDH High Z Data In Valid Data tOHZ(6) High Z(8) Data Out NOTES(WRITE CYCLE) 1. All write cycle timing is referenced from the last valid address to the first transition address. 2. A write occurs during the overlap of a low /CS and /WE. A write begins at the latest transition /CS going low and /WE going low ; A write ends at the earliest transition /CS going high or /WE going high. tWP is measured from the beginning of write to the end of write. 3. tCW is measured from the later of /CS going low to end of write. 4. tAS is measured from the address valid to the beginning of write. 5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as /CS or /WE going high. 6. If /OE, /CS and /WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase of the output must not be applied because bus contention can occur. 7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. 8. If /CS goes low simultaneously with /WE going or after /WE going low, the outputs remain high impedance state. 9. Dout is the read data of the new address. 10.When /CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be applied. Note: /CS = /CS1~4, /WE = /WE1~4 PAGE 7 Issue 1.1 November 2002 Write Cycle 2 (/OE = Low Fixed) tWC Address tAW tWR(5) tCW(3) /CS tAS(4) tWP(2) /WE tDW tDH High Z Valid Data Data In tOW tWHZ(6) High Z(8) (10) (9) Data Out NOTES(WRITE CYCLE) 1. All write cycle timing is referenced from the last valid address to the first transition address. 2. A write occurs during the overlap of a low /CS and /WE. A write begins at the latest transition /CS going low and /WE going low ; A write ends at the earliest transition /CS going high or /WE going high. tWP is measured from the beginning of write to the end of write. 3. tCW is measured from the later of /CS going low to end of write. 4. tAS is measured from the address valid to the beginning of write. 5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as /CS or /WE going high. 6. If /OE, /CS and /WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase of the output must not be applied because bus contention can occur. 7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. 8. If /CS goes low simultaneously with /WE going or after /WE going low, the outputs remain high impedance state. 9. Dout is the read data of the new address. 10.When /CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be applied. Note: /CS = /CS1~4, /WE = /WE1~4 PAGE 8 Issue 1.1 November 2002 Write Cycle 3 (/CS = Controlled) tWC Address tAW tWR(5) tCW(3) /CS tAS(4) tWP(2) /WE tDW tDH High Z High Z Valid Data Data In tLZ High Z tWHZ(6) High Z(8) Data Out NOTES(WRITE CYCLE) 1. All write cycle timing is referenced from the last valid address to the first transition address. 2. A write occurs during the overlap of a low /CS and /WE. A write begins at the latest transition /CS going low and /WE going low ; A write ends at the earliest transition /CS going high or /WE going high. tWP is measured from the beginning of write to the end of write. 3. tCW is measured from the later of /CS going low to end of write. 4. tAS is measured from the address valid to the beginning of write. 5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as /CS or /WE going high. 6. If /OE, /CS and /WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase of the output must not be applied because bus contention can occur. 7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. 8. If /CS goes low simultaneously with /WE going or after /WE going low, the outputs remain high impedance state. 9. Dout is the read data of the new address. 10.When /CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be applied. Note: /CS = /CS1~4, /WE = /WE1~4 PAGE 9 Issue 1.1 November 2002 Package Details PUMA 84 - Plastic 84 ëJí Leaded Package. 30.35 (1.195 ) 30.10 (1.185 ) 5.08 (0.200) max 0 .4 6 (0 . 01 8 ) typ 1 .2 7 (0 . 05 0 ) typ 0.90 (0.035) typ 29.20 (1.1 50) 28.20 (1.1 10) PAGE 10 Issue 1.1 November 2002 Ordering Information Speed 012 = 12ns 015 = 15ns 020 = 20ns Temp. Range/Screening Blank = Commercial I = Industrial Power Consumption Blank = Standard Memory Organisation 64000 = 2M x 32 configurable as 4M x 16 and 8M x 8 Technology Package SV = SRAM 3.3V+10% VCC PUMA 84 = Plastic 84 ëJí Leaded Package. Note : Although this data is believed to be accurate the information contained herein is not intended to and does not create any warranty of merchantibility or fitness for a particular purpose. Our products are subject to a constant process of development. Data may be changed without notice. Products are not authorised for use as critical components in life support devices without the express written approval of a company director. PAGE 11 http://www.hmpeurope.com/ Issue 1.1 November 2002 Ordering Information PUMA 84SV64000 84SV64000 I-012 I-012