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Part : N82S103N Supplier : Signetics Manufacturer : Chip One Exchange Stock : 117 Best Price : - Price Each : -
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82S103 Datasheet

Part Manufacturer Description PDF Type
82S103 Signetics FIELD PROGRAMMABLE GATE ARRAY (16x9x9) Scan


Catalog Datasheet MFG & Type PDF Document Tags
Abstract: (O.CJ/82S103 (T.S.) INTEGRATED FUSE LO GIC SERIES 28 DESCRIPTION FEATURES T he 82S 102 a n d , collector 82S103: T ri-state â'¢ O u tp u l disable function: 82S102: Hi 82S103: H i-Z 16 in p u ts , PROGRAMMABLE GATE ARRAY ( 1 6 x 9 x 9 ) 82S102 (O.C.J/82S103 (T.S.) INTEGRATED FUSE LO G IC SERIES 28 , ly v o lta g e In p u t v o lta g e O u tp u t v o lta g e H ig h (82S102) O ff-s ta te (82S103 , t v o lta g e L o w 1.4 H ig h (82S103>1.5 1L 1 I ih In p u t c u rre n t Low H igh -
OCR Scan
Abstract: '¢ 82S103-I.N 92 signotiES 82S102-I,N â'¢ 82S103-I,N 16X9 FPGA PROGRAM TABLE customer name purchase order # , 82S102-I,N â'¢ 82S103-I,N PIN CONFIGURATION l,N PACKAGE* '< DI '281 Vcc 27] lâ'ž U[I £6] 1» l.tl , sfgnotiES 82S102-I.N â'¢ 82S103-I.N ABSOLUTE MAXIMUM RATINGS PARAMETER RATING UNIT Vcc Supply voltage +7 , Z=X»Y OR Z;X'V SipDtiCB 87 82S102-I.N â'¢ 82S103-I.N DC ELECTRICAL CHARACTERISTICS N82S102/103: 0 , level are programmed active high (Fp function). 82S102-I.N â'¢ 82S103-I.N Input Matrix PROGRAM INPUT -
OCR Scan
FUSE f7 470H signetics 82s102 P601 F-7112 82S1 S82S102/103
Abstract: Signetics Memories - Bipolar FPGA N82S102, IM82S103 Bipolar Field Pro grammable Gate Array (16x9) GENERAL DESCRIPTION The 82S102 and 82S103 are Bipolar programmable AND/ NAND gate arrays , outlined in this data sheet. The 82S102 and 82S103 include chip-enable control for output strobing and , : Open collector 82S103: Tri-state â'¢ Output disabte function; 82S102: Hi 82S103: Hi-Z â'¢ Fully TTL , voltage +5.5 Vdc Output voltage Vdc VOH High (82S102) +5.5 vo Off-state (82S103) +5.5 'in Input -
OCR Scan
signetics 82s103 FPGA 82S103 lm 742 N82S103 Signetics SE 540 N82S102N
Abstract: BIPOLAR MEMORY DIVISION JANUARY 1983 FIELD PROGRAMMABLE GATE ARRAY (16x9x9) 82S102 (O.C.) /82S103 (T.S.) OUTPUT POLARITY PROGRAM-VERIFY SEQUENCE (TYPICAL) VCCP-"cc Vccv - V0PFâ'"I-T- OUTPUT / VOLTAGE " V°Hâ'"u cr vix â'" «IH- (Fp) TPR (PROGRAM) (Fp + 1) PWp (VERIFY) «d- ¡"^ V|L_.J- / -vol (Fp + 2) ~iâ'"r I_I "LT J 1 INPUT MATRIX PROGRAM-VERIFY SEQUENCE (TYPICAL) VIRGIN DEVICE , (16x9x9) 82S102 (0,C.)/82S103 (T.S.) The state of lo contained in each gate is determined in accordance -
OCR Scan
Abstract: 10H20EV8 82S100 82S101 82S103 82S105 82S105A 82S151 82S153 82S153A 82S155 82S157 82S159 82S161 82S162 -
OCR Scan
PLS152 P16L8 ck2605 ck2678 PLHS16L8AN PLS100 fpla plhs18p8an 10020EV8 CK2605 CK2678 PHD16N8 PHD48N22 PLC105