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82C37A Datasheet

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82C37A Harris Semiconductor CMOS High Performance Programmable DMA Controller
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23 pages,
204.35 Kb

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82C37A Harris Semiconductor CMOS High Performance Programmable DMA Controller
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24 pages,
277.8 Kb

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82C37A Intersil Corporation CMOS High Performance Programmable DMA Controller
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23 pages,
147.3 Kb

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82C37A-5 Intel CHMOS High Performance Programmable DMA Controller
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18 pages,
697.4 Kb

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82C37A-5 Intersil Corporation CMOS High Performance Programmable Dma Controller
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24 pages,
277.8 Kb

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82C37A

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Abstract: g ) H A R R IS 82C37A/883 CMOS High Performance Programmable DMA Controller , Description The 82C37A/883 Is an enhanced version of the industry standard 823TA 823TA Direct Memory AoCttss (DMA , 82C37A/ 883 offers increased functionality, improved performance, and dramatically reduced power , 82C37A/883 controller can Improve system performance by allowing external devices to transfer data , operation. The 82C37A/883 is designed to be used with an external address latch, such as the 82C82 82C82, to ... OCR Scan
datasheet

1 pages,
62.15 Kb

8086 DMA channels 82c37a datasheet abstract
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Abstract: Aktiengesellschaft 615 SAB 82C37A Ordering Information Type SA B 82C37A-5-P S A B 82C37A-8-P Ordering code , 82C37A-5 300 ns at least for the S A B 82C37A-8 S iem en s Aktiengesellschaft 611 SAB 82C37A DMA , SAB 82C37A-5/82C37A-8 High-Performance CMOS Programmable DMA Controller '« f t SAB 82C37A-5 5 MHz , in a 40-pin DIP. The S A B 82C37A-8 is the 8 MHz version of the 5 MHz S A B 82C37A-5. The S A B , 82C37A-5and up to 8 MHz for the S A B 82C37A-8. R ESET Reset is an asynchronous active-high input w hich ... OCR Scan
datasheet

18 pages,
719.9 Kb

82C37A-5/82C37A-8 82C37A-5 82C37A-8 82C37A-5/82C37A-8 abstract
datasheet frame
Abstract: INTEGRATED PERIPHERAL CONTROLLER WITH STANDARD PC-AT PERIPHERALS COMBINES TWO 82C37A DMA CONTROLLERS, TWO , PCI Arbiter Fast Internal Bus DMA Controllers 2x 82C37A 32 bit address 32 PCI Bus Interface ... Original
datasheet

1 pages,
23.2 Kb

P-QFP-208 W83C553F PQFP208 82C37A 82C59A 82C54 33MHZ W83C553F abstract
datasheet frame
Abstract: driven from DC to 8MHz for the 82C37A, or from DC to 5 MHz for the 82C37A-5. The Clock may be stopped in , ) (I82C37A-5 I82C37A-5) TA = -55°C to +1250C 1250C (M82C37A M82C37A) (M82C37A-5 M82C37A-5) SYMBOL PARAMETER 82C37A-5 82C37A UNITS MIN MAX MIN , T-52-33-19 T-52-33-19 A.C. Electrical Spécifications DMA Master Mode 82C37A-S 82C37A SYMBOL , signal used by the CPU to load information into the 82C37A. In the Active cycle, It is an output control , (SW) can be inserted between S2 or S3 and S4 by the use of the Ready line on the 82C37A. 4-6 HARRIS ... OCR Scan
datasheet

18 pages,
1641.04 Kb

octal priority encoder datasheet abstract
datasheet frame
Abstract: C M O S Peripherals PAGE CMOS PERIPHERALS Industry CMOS Peripheral Cross Reference. 82C37A 82C50A 82C50A 82C52 82C52 82C54 82C54 82C55A 82C55A 82C59A 82C59A 82C82 82C82 82C83H 82C83H 82C84A 82C84A 82C85 82C85 82C86H/87H 82C86H/87H 82C88 82C88 82C89 82C89 App Note 109 High Performance Programmable DMA Controller. Asynchronous Communications Element . Serial Controller Interface. Programmable Interval Tim er. ... OCR Scan
datasheet

1 pages,
16.89 Kb

82C84A 82C37A 82C50A 82C52 82C54 82C55A 82C59A 82C82 82C83H 82C85 82C86H/87H 82C88 82C89 82C37A abstract
datasheet frame
Abstract: 82C37A operations. This input may be driven from DC to 12.5MHz for the 82C37A-12, from DC to 8MHz for the 82C37A, or from DC to 5MHz for the 82C37A-5. The Clock may be stopped in either state for standby , DACK signals respectively of a channel for the initial 82C37A.This allows the DMA requests of the , input control signal used by the CPU to load information into the 82C37A. In the Active cycle, it is an , S4 in normal transfers by the use of the Ready line on the 82C37A. For compressed transfers, wait ... Original
datasheet

24 pages,
416.18 Kb

82C82 80C88 80C86 80C286 8088 microprocessor 80286 microprocessor pin out diagram 80286 microprocessor features control data bus for 80286 CP82C37A-5 NSC800 logical block diagram of 80286 IP82C37A-5 FN2967 82C37A FN2967 82C37A abstract
datasheet frame
Abstract: from DC to 12.5MHz for the 82C37A-12, from DC to 8MHz for the 82C37A, or from DC to 5MHz for the 82C37A-5. The Clock may be stopped in either state for standby operation. CHIP SELECT: Chip Select is an , signals respectively of a channel for the initial 82C37A.This allows the DMA requests of the additional , information into the 82C37A. In the Active cycle, it is an output control signal used by the 82C37A to load , between S3 and S4 in normal transfers by the use of the Ready line on the 82C37A. For compressed transfers ... Original
datasheet

24 pages,
586.44 Kb

82C37A FN2967 82C82 80C286 80C86 80C88 NSC800 82C37A abstract
datasheet frame
Abstract: from DC to 12.5MHz for the 82C37A-12, from DC to 8MHz for the 82C37A, or from DC to 5MHz for the 82C37A-5. The Clock may be stopped in either state for standby operation. CS 11 I CHIP SELECT , the DREQ and DACK signals respectively of a channel for 197 82C37A the initial 82C37A.This , load information into the 82C37A. In the Active cycle, it is an output control signal used by the , 82C37A. For compressed transfers, wait states can be inserted between S2 and S4. See timing Figures 14 ... Original
datasheet

24 pages,
277.8 Kb

NSC800 80C86 80C88 82C37A 82C82 CP82C37A-5 CS82C37A-5 IP82C37A-5 IS82C37A-5 80C286 82C37A abstract
datasheet frame
Abstract: control 82C37A operations. This input may be driven from DC to 12.5MHz for the 82C37A-12, from DC to 8MHz for the 82C37A, or from DC to 5MHz for the 82C37A-5. The Clock may be stopped in either state for , DACK signals respectively of a channel for 4-197 82C37A the initial 82C37A.This allows the DMA , control signal used by the CPU to load information into the 82C37A. In the Active cycle, it is an output , between S3 and S4 in normal transfers by the use of the Ready line on the 82C37A. For compressed ... Original
datasheet

23 pages,
204.35 Kb

NSC800 80C86 80C88 82C37A 82C82 CP82C37A-12 CP82C37A-5 CS82C37A-5 IP82C37A-5 IS82C37A-5 80C286 82C37A abstract
datasheet frame
Abstract: This input may be driven from DC to 12.5MHz for the 82C37A-12, from DC to 8MHz for the 82C37A, or from DC to 5MHz for the 82C37A-5. The Clock may be stopped in either state for standby operation. CS , DACK signals respectively of a channel for 4-197 82C37A the initial 82C37A.This allows the DMA , control signal used by the CPU to load information into the 82C37A. In the Active cycle, it is an output , between S3 and S4 in normal transfers by the use of the Ready line on the 82C37A. For compressed ... Original
datasheet

23 pages,
147.29 Kb

NSC800 80C286 80C86 80C88 82C37A 82C82 CP82C37A-5 CS82C37A-5 IP82C37A-5 IS82C37A-5 8086 DMA channels 82C37A abstract
datasheet frame
Abstract: Peripheral Cross Reference HARRIS PERIPHERALS M 5M 82C 37A - 4 ,- 5 u n w r m \iL8 ? C 3 7 A -b V L82C3- L82C3-'A-5i M 5M 82C 54-6 M 5M 82C54 82C54 M 5M 82C 55A -5 ' M 5M 82C59A 82C59A e ' C S lA -2 (jPD71059 '.L 0 2 > _ t 1A à AM82C59A AM82C59A AM 82C55A-2 82C55A-2 I 1 IN T E L . | NEC 0 *1 | MITSUBISHI VLSf | OTHER 82C 37A -5 82C37A a p r i* M S M 8JC 57A 5 f1SVdPC37A 82C54 82C54 82C 55A -5 82C55A 82C55A 82 C 5 9A -5 82C59A 82C59A UARTS ,uPD71054 uPD71054 MSVSafS4 MSM82eS5A>5 -? '.I jBSC54-P AM82C54 AM82C54 "2C55A-2 2C55A-2 (jPD71055 msmsscsm w 82C50A 82C50A 82C52 82C52 ... OCR Scan
datasheet

1 pages,
148.3 Kb

uPD71054 Mitsubishi 82c54 82C55A-2 L82C3- 82C54 82C59A AM82C59A 82C37A L82C3- abstract
datasheet frame
Abstract: Perform ance P rogram m able DM A C ontroller Description The 82C37A is an enhanced version of the , CMOS process. Pin compatible with NMOS designs, the 82C37A offers increased functionality, improved , operation for even further reduction of power. The 82C37A controller can improve system performance by , features for flexible operation. The 82C37A is designed to be used with an external address latch, such as the 82C82 82C82, to demultiplex the most significant 8-bits of address. The 82C37A can be used with industry ... OCR Scan
datasheet

23 pages,
1744.99 Kb

datasheet abstract
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Voltage Reference 82C37A CMOS High Performance Programmable DMA Controller Datasheet & Related Description The 82C37A is an enhanced version of the industry standard 8237A Direct Memory Access (DMA 82C37A offers increased functionality, improved performance, and dramatically reduced power consumption. The fully static design permits gated clock operation for even further reduction of power. The 82C37A independently programmable with a variety of features for flexible operation. The 82C37A is designed to be used
www.datasheetarchive.com/files/intersil/device_pages/device_82c37a-v1.html
Intersil 13/10/2005 22.49 Kb HTML device_82c37a-v1.html
Harris Corporation's Home Page ¤ Semiconductor's Home Page ¤ Product Information ¤ 82C37A 82C37A Data Sheets fn2967.pdf CMOS High Performance Programmable DMA Controller ( Adobe's pdf format - 209523 bytes) Packaging F40.6 Mil-Std-1835 GDIP1-T40 GDIP1-T40 GDIP1-T40 GDIP1-T40 (D-5, Configuration A) 40 Lead Ceramic Dual-In-Line Frit Seal Package J44.A Mil-Std-1835 CQCC1-N44 CQCC1-N44 CQCC1-N44 CQCC1-N44 (C-5) 44 Pad Ceramic Leadless Chip Carrier Package
www.datasheetarchive.com/files/harris/data/fn/fn2/fn2967/index.htm
Harris 15/08/1997 3.24 Kb HTM index.htm
Harris Corporation's Home Page ¤ Semiconductor's Home Page ¤ Product Information ¤ 82C37A 82C37A Data Sheets fn2967.pdf CMOS High Performance Programmable DMA Controller ( Adobe's pdf format - 209523 bytes) Packaging F40.6 Mil-Std-1835 GDIP1-T40 GDIP1-T40 GDIP1-T40 GDIP1-T40 (D-5, Configuration A) 40 Lead Ceramic Dual-In-Line Frit Seal Package J44.A Mil-Std-1835 CQCC1-N44 CQCC1-N44 CQCC1-N44 CQCC1-N44 (C-5) 44 Pad Ceramic Leadless Chip Carrier Package
www.datasheetarchive.com/files/harris/data/fn/fn2/fn2967/index-v1.htm
Harris 29/04/1998 3.23 Kb HTM index-v1.htm
/Crosspoints Switching Regulation Timing Circuits Video ICs Voltage References 82C37A CMOS High J-STD-020 J-STD-020 J-STD-020 J-STD-020 SMD = Standard Microcircuit Drawing Description The 82C37A is an enhanced version of the micron CMOS process. Pin compatible with NMOS designs, the 82C37A offers increased functionality clock operation for even further reduction of power. The 82C37A controller can improve system features for flexible operation. The 82C37A is designed to be used with an external address latch, such as
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Intersil 07/09/2006 23.8 Kb HTML device_82c37a.html
Device Datasheet Link Device Description Features Package 82C37A CMOS High Performance Microprocessors Device Datasheet Link Device Description Package 82C37A CMOS 16-Bit Microprocessor 68 Ld PLCC 82C37A High Performance Microprocessor with Memory Management and Protection 68 Ld PGA 82C37A CMOS 16-Bit Microprocessor 40 Ld CerDIP 40 Ld PDIP
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Intersil 17/09/2006 27.23 Kb HTML parametric_6000.html
PERIPHERALS GENERAL 82C37A-5 82C37A-5 MSM82C37A-5 MSM82C37A-5 MSM82C37A-5 MSM82C37A-5 CAB2C37A5 CAB2C37A5 CAB2C37A5 CAB2C37A5 82C37A CAB2C37A8 CAB2C37A8 CAB2C37A8 CAB2C37A8 Programmable DMA Controller 82C237 82C237 82C237 82C237 Enhanced Programmable DMA Controller 82C37A-12 with the 82C237 82C237 82C237 82C237, 82C284 82C284 82C284 82C284, 82C37A, 82C50A 82C50A 82C50A 82C50A, 82C52 82C52 82C52 82C52, 82C54 82C54 82C54 82C54, 82C55A 82C55A 82C55A 82C55A, 82C59A 82C59A 82C59A 82C59A, 82C82 82C82 82C82 82C82, 82C83H 82C83H 82C83H 82C83H, 82C84A 82C84A 82C84A 82C84A, 82C85 82C85 82C85 82C85
www.datasheetarchive.com/files/harris/micro/upx86.htm
Harris 15/08/1997 10.79 Kb HTM upx86.htm
Package 82C37A CMOS High Performance Programmable DMA Controller • Compatible with the NMOS Link Device Description Package 82C37A CMOS 16-Bit Microprocessor 68 Ld PLCC 82C37A High Performance Microprocessor with Memory Management and Protection 68 Ld PGA 82C37A CMOS 16-Bit Microprocessor 40 Ld CerDIP 40 Ld PDIP 82C54 82C54 82C54 82C54 CMOS
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Intersil 17/09/2006 60.85 Kb HTML parametric_15095.html
Peripherals 82C82 82C82 82C82 82C82 - CMOS Octal Latching Bus Driver 82C86 82C86 82C86 82C86 - CMOS Octal Bus Transceiver 82C37A
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Intersil 13/10/2005 25.81 Kb HTML microp_c.html
, EDO, 3,3Volt, 60 ns) 128 KByte 8 Bit BIOS-EPROM Im Prozessor integriert zwei 82C37A
www.datasheetarchive.com/files/stmicroelectronics/stonline/products/support/stpc/appli/mkc/486sipi-v2.htm
STMicroelectronics 14/06/1999 11.33 Kb HTM 486sipi-v2.htm
integriert zwei 82C37A DMA-Controller, zwei 82C59A 82C59A 82C59A 82C59A Interrupt-Controller, ein 82C54 82C54 82C54 82C54 Timer, PLL-Clock
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STMicroelectronics 02/11/1999 12.99 Kb HTM 486sipi.htm

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