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Part Manufacturer Description Datasheet BUY
MD82C37A/B Intersil Corporation 4 CHANNEL(S), 8MHz, DMA CONTROLLER, CDIP40, CERAMIC, DIP-40 visit Intersil
CP82C37A-5 Intersil Corporation 4 CHANNEL(S), 5MHz, DMA CONTROLLER, PDIP40, PLASTIC, DIP-40 visit Intersil
CS82C37A-1296 Intersil Corporation 4 CHANNEL(S), 12.5MHz, DMA CONTROLLER, PQCC44, PLASTIC, MO-047AC, LCC-44 visit Intersil
CS82C37AZ Intersil Corporation 4 CHANNEL(S), 8MHz, DMA CONTROLLER, PQCC44, ROHS COMPLIANT, MO-047AC, PLASTIC, LCC-44 visit Intersil
CS82C37A Intersil Corporation 4 CHANNEL(S), 8MHz, DMA CONTROLLER, PQCC44 visit Intersil

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82C37A Datasheet

Part Manufacturer Description PDF Type
82C37A Harris Semiconductor CMOS High Performance Programmable DMA Controller Original
82C37A Harris Semiconductor CMOS High Performance Programmable DMA Controller Original
82C37A Intersil CMOS High Performance Programmable DMA Controller Original
82C37A-5 Intersil CMOS High Performance Programmable Dma Controller Original
82C37A-5 Intel CHMOS High Performance Programmable DMA Controller Scan

82C37A

Catalog Datasheet MFG & Type PDF Document Tags

82C37A

Abstract: 82C37A DMA Controller . This input may be driven from DC to 12.5MHz for the 82C37A-12, from DC to 8MHz for the 82C37A, or from DC to 5MHz for the 82C37A-5. The Clock may be stopped in either state for standby operation. CS , DACK signals respectively of a channel for the initial 82C37A.This allows the DMA requests of the , input control signal used by the CPU to load information into the 82C37A. In the Active cycle, it is an , transfers by the use of the Ready line on the 82C37A. For compressed transfers, wait states can be
Intersil
Original
82C37A DMA Controller marking db2 M82C37 80C286 80C86 80C88 FN2967 ISO9000
Abstract: from DC to 12.5MHz for the 82C37A-12, from DC to 8MHz for the 82C37A, or from DC to 5MHz for the 82C37A-5. The Clock may be stopped in either state for standby operation. CHIP SELECT: Chip Select is an , signals respectively of a channel for the initial 82C37A.This allows the DMA requests of the additional , the 82C37A. In the Active cycle, it is an output control signal used by the 82C37A to load data to the , transfers by the use of the Ready line on the 82C37A. For compressed transfers, wait states can be inserted Intersil
Original
82C82 NSC800 1N4002 F14/2

octal priority encoder

Abstract: driven from DC to 8MHz for the 82C37A, or from DC to 5 MHz for the 82C37A-5. The Clock may be stopped in , (I82C37A) (I82C37A-5) TA = -55°C to +1250C (M82C37A) (M82C37A-5) SYMBOL PARAMETER 82C37A-5 82C37A UNITS , ©cifications 82C37A T-52-33-19 A.C. Electrical Spécifications DMA Master Mode 82C37A-S 82C37A , HARRIS SEflICOND SECTOR TS DE | M302271 OOIO^L o |~ ' T-52-33-19 20 HARRIS 82C37Ã' CMOS High , signal used by the CPU to load information into the 82C37A. In the Active cycle, It is an output control
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octal priority encoder 430E571 43GS57 001GT43
Abstract: Information Type SA B 82C37A-5-P S A B 82C37A-8-P Ordering code Q 67120-P215 Q 67Ì20-P239 Description Program , SAB 82C37A-5/82C37A-8 High-Performance CMOS Programmable DMA Controller '« f t SAB 82C37A-5 5 MHz , in a 40-pin DIP. The S A B 82C37A-8 is the 8 MHz version of the 5 MHz S A B 82C37A-5. The S A B , 82C37A-5and up to 8 MHz for the S A B 82C37A-8. R ESET Reset is an asynchronous active-high input w hich , Sym bol Param eter 82C37A-5 min. ^AEL ¿AET ^AFAB ^AFC ^AFDB ^AHR ^AHS ^AHW Lim it values 82C37A-8 -
OCR Scan
82C37A-5/82C37A-8 82C37A-B P-DIP-40

D82c

Abstract: r29671 input may be driven from DC to 12.5M Hz for the 82C37A-12, from DC to 8M Hz for the 82C37A, or from DC to 5MHz for the 82C37A-5. The Clock may be stopped in either state for standby operation. CHIP SELECT , . Separate software commands can also set or reset this flip-flop. 4-197 82C37A the initial 82C37A.This , 82C37A. In the Active cycle, it is an output control signal used by the 82C37A to load data to the , (SW) can be inserted between S3 and S4 in normal transfers by the use of the Ready line on the 82C37A.
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D82c r29671 R82C37A 29--------------OPEN N4002

80C286

Abstract: 80C86 control 82C37A operations. This input may be driven from DC to 12.5MHz for the 82C37A-12, from DC to 8MHz for the 82C37A, or from DC to 5MHz for the 82C37A-5. The Clock may be stopped in either state for , respectively of a channel for 4-197 82C37A the initial 82C37A.This allows the DMA requests of the , control signal used by the CPU to load information into the 82C37A. In the Active cycle, it is an output , between S3 and S4 in normal transfers by the use of the Ready line on the 82C37A. For compressed
Harris Semiconductor
Original
IS82C37A-5 CP82C37A-12 MR82C37A

8086 DMA channels

Abstract: 80C286 . This input may be driven from DC to 12.5MHz for the 82C37A-12, from DC to 8MHz for the 82C37A, or from DC to 5MHz for the 82C37A-5. The Clock may be stopped in either state for standby operation. CS , respectively of a channel for 4-197 82C37A the initial 82C37A.This allows the DMA requests of the , control signal used by the CPU to load information into the 82C37A. In the Active cycle, it is an output , between S3 and S4 in normal transfers by the use of the Ready line on the 82C37A. For compressed
Intersil
Original
8086 DMA channels

smd transistor A7w

Abstract: 12.5MHz for the 82C37A-12, from DC to 8MHz for the 82C37A, or from DC to 5MHz for the 82C37A-5. The Clock , connected to the DREQ and DACK signals respectively of a channel for 4-197 82C37A the initial 82C37A.This , information into the 82C37A. In the Active cycle, it is an output control signal used by the 82C37A to load , the 82C37A. For compressed transfers, wait states can be inserted between S2 and S4. See timing , the microprocessor to write or read the internal registers of the 82C37A. When CS is low and HLDA is
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smd transistor A7w MD82C37A
Abstract: which control 82C37A operations. This input may be driven from DC to 12.5MHz for the 82C37A-12, from DC to 8MHz for the 82C37A, or from DC to 5MHz for the 82C37A-5. The Clock may be stopped in either , DACK signals respectively of a channel for 4-197 82C37A the initial 82C37A.This allows the DMA , information into the 82C37A. In the Active cycle, it is an output control signal used by the 82C37A to load , S4 in normal transfers by the use of the Ready line on the 82C37A. For compressed transfers, wait -
OCR Scan

82C37A

Abstract: 80C286 from DC to 12.5MHz for the 82C37A-12, from DC to 8MHz for the 82C37A, or from DC to 5MHz for the 82C37A-5. The Clock may be stopped in either state for standby operation. CS 11 I CHIP SELECT , for 197 82C37A the initial 82C37A.This allows the DMA requests of the additional device to , by the CPU to load information into the 82C37A. In the Active cycle, it is an output control signal , S4 in normal transfers by the use of the Ready line on the 82C37A. For compressed transfers, wait
Intersil
Original

HS4D

Abstract: 417Z driven from DC to 8MHz fo r the 82C37A, or from DC to 5 MHz fo r the 82C37A-5. The C lock may be stopped , , it is an input c o n tro l signal used by the CPU to load inform ation into the 82C37A. In the A , inserted between S2 or S3 and S4 by the use of the Ready line on the 82C37A. F IG U R E 1. 82C 37A IN TE , to the DREQ and DACK signals respectively of a channel for the initial 82C37A. This allows the DMA , icroprocessor to w rite or read the internal registers of the 82C37A. When CS is low and HLDA is low. the 82C37A
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HS4D 417Z 0RE02 82C37I
Abstract: may be driven from DC to 12.5MHz for the 82C37A-12, from DC to 8MHz for the 82C37A, or from DC to 5MHz for the 82C37A-5. The Clock may be stopped in either state for standby operation. CS 1 1 , the initial 82C37A.This allows the DMA requests of the additional device to propagate through the , is an input con­ trol signal used by the CPU to load information into the 82C37A. In the Active , normal transfers by the use of the Ready line on the 82C37A. For compressed transfers, wait states can -
OCR Scan
520S2 430BB71
Abstract: 12.5MHz for the 82C37A-12, from DC to 8MHz for the 82C37A, or from DC to 5MHz for the 82C37A-5. The Clock , . In the Idle cycle, it is an input control signal used by the CPU to load information into the 82C37A. , S4 in normal transfers by the use of the Ready line on the 82C37A. For com pressed transfers, wait , the DREQ and DACK signals respectively of a channel for the initial 82C37A. This allow s the DMA , the m icroprocessor to w rite or read the internal registers of the 82C37A. When CS is low and HLDA is -
OCR Scan

82c37a

Abstract: 8085 block transfer program g ) H A R R IS 82C37A/883 CMOS High Performance Programmable DMA Controller , Description The 82C37A/883 Is an enhanced version of the industry standard 823TA Direct Memory AoCttss (DMA , 82C37A/ 883 offers increased functionality, improved performance, and dramatically reduced power , 82C37A/883 controller can Improve system performance by allowing external devices to transfer data , . The 82C37A/883 is designed to be used with an external address latch, such as the 82C82, to
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8085 block transfer program 82C37A/883
Abstract: 82C37A-12, from DC to 8MHz for the 82C37A, or from DC to 5MHz for the 82C37A-5. The Clock may be stopped in , information into the 82C37A. In the Active cycle, it is an output control signal used by the 82C37A to load , between S3 and S4 in normal transfers by the use of the Ready line on the 82C37A. For com pressed , of the 82C37A. W hen CS is low and HLDA is low, the 82C37A enters the Program Condition. The CPU , 82C37A are connected to the DREQ and DACK signals respectively of a channel for the initial 82C37A. -
OCR Scan

PQFP208

Abstract: W83C553F INTEGRATED PERIPHERAL CONTROLLER WITH STANDARD PC-AT PERIPHERALS COMBINES TWO 82C37A DMA CONTROLLERS, TWO , PCI Arbiter Fast Internal Bus DMA Controllers 2x 82C37A 32 bit address 32 PCI Bus Interface
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Original
W83C553F 82C59A PQFP208 P-QFP-208 interface device pci port ide controller 82C54 33MHZ

Intel 8237A

Abstract: CSN-11 Page 1 of 4 IA8237 Programmable DMA Controller Advanced Information Sheet FEATURES · · · · · Form, Fit, and Function Compatible with the Intel® 8237A and Harris© 82C37A Packaging options available: 40 Pin Plastic Dip or 44 Pin Plastic Leaded Chip Carrier Static Read/Write or Handshaking Modes Direct Bit Set/Reset Capability Memory-to-Memory Transfers The IA8237 uses innovASIC , equivalent to the Intel 8237A and Harris 82C37A devices. The A8237 controls data transfers between memory
InnovASIC Semiconductor
Original
Intel 8237A CSN-11 40 pin plcc ic base ic base for 40 pin DIP ic 8237A a739 MIL-STD-883
Abstract: a modified version of the 82C37A. The 82C237 is fully software and pin for pin compatible with the 82C37A but provides an additional mode for 16-bit DMA transfers, as well as enhanced speed. Each channel , for pin compatible with the 82C37A. All operational and pin descriptions of the 82C37A apply to the , compatible with the 82C37A. Therefore, the 82C 237 may be used as a faster 82C37A without modifications to , ). February 1992 Features · Fully Compatible with Harris 82C37A - 82C237 May be Used in 8MHz -
OCR Scan
H3DSS71 30C88 T--52--33--19-

IP82C237-12

Abstract: TCY-75 Software The 82C237 is a modified version of the 82C37A. The 82C237 is fully software and pin for pin compatible with the 82C37A but provides an additional mode for 16-bit DMA transfers, as well as enhanced , and pin for pin compatible with the 82C37A. All operational and pin descriptions of the 82C37A apply , with the 82C37A. Therefore, the 82C237 may be used as a faster 82C37A without modifications to , Description · Fully Compatible with Intersil 82C37A - 82C237 May be Used in 8MHz and 12.5MHz 82C37A
Intersil
Original
IP82C237-12 TCY-75 CP82C237 CS82C237 IP82C237

82C237

Abstract: 80C286 1997 Features Description · Fully Compatible with Harris 82C37A - 82C237 May be Used in 8MHz and 12.5MHz 82C37A Sockets The 82C237 is a modified version of the 82C37A. The 82C237 is fully software and pin for pin compatible with the 82C37A but provides an additional mode for 16-bit DMA , controller and is fully software and pin for pin compatible with the 82C37A. All operational and pin , with the 82C37A. Therefore, the 82C237 may be used as a faster 82C37A without modifications to
Harris Semiconductor
Original

m5l8085

Abstract: M5L8085a a modified version of the 82C37A. The 82C237 is fully software and pin for pin compatible with the 82C37A but provides an additional mode for 16-bit DMA transfers, as well as enhanced speed. Each channel , ). February 1992 Features · Fully Compatible with Harris 82C37A - 82C237 May be Used in 8MHz and 12.5MHz 82C37A Sockets · Optimized for 10MHzand 12.5MHz 80C286 Systems · Special Mode Permits 16 , -52-33-19 The 82C 237 is an improved version of the Harris 82C37A DMA controller and Is fully software and pin
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m5l8085 M5L8085a M5L8085AP e15f M5M82C37AP M5M82C37AP-5 M5M82C37AP-4

74f75

Abstract: Performance Programmable DMA Controller Description The 82C237 is a modified version of the 82C37A. The 82C237 is fully software and pin for pin compatible with the 82C37A but provides an additional mode for , 82C37A - 62C237 May be Used in 8M Hz and 12.5MHz 82C37A Sockets · Optim ized for 10MHz and 12.5MHz 80C2S6 , 82 C 2 37 is an improved version o f the Harris 82C37A DMA controller and is fully software and pin for pin com patible with the 82C37A. All operational and pin descriptions of the 82C 37A apply to the
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OCR Scan
74f75
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