NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Catalog Datasheet Results | Type | Document Tags |
| Abstract: peripherals fit into a single FPGA. Block Diagram Features iW-86 CPU Core with Bus Interface Unit Bus Arbitration Unit Wait Control Unit Multi Protocol Serial Controller similar to 8530 Programmable Timer similar to 8254 PCI Target Controller with on-chip memory Peripheral / Memory Bus Interface CPU on-chip peripherals Programmable 16-bit Timer similar to 8254 Serial Controller Unit similar to 8251 Interrupt Controller Unit similar to 8259 DMA Controller Unit similar to 8237 80186 CPU Core Programmable ... | Original |
1 pages, |
a3pe1500 interfacing chip 8251 8251 timer 8254 8251 DMA controller interrupt controller verilog code interrupt controller verilog USART 8251 interfacing with RS-232 8259 Programmable Peripheral Interface verilog code for 8251 block diagram 8251 USART 8251 interfacing datasheet abstract |
|
|||
| Abstract: is programmable allowing any peripheral that requires wait states to create them. DRAM Refresh , 32 Bit DMA Controller with 8 channels each individually programmable. Bus Interface This block , o Fifteen external interrupts o 5 internal interrupts o Intel 8259 superset Four 16-Bit Programmable In- terval Timers o Intel 8254 compatible Programmable Wait State gene- The C82380 C82380 32-Bit DMA Controller core is a multi-function support system. It is designed to provide peripheral support ... | Original |
2 pages, |
82380 8259 programmable interval timer block diagram of intel 8254 chip vhdl code dma controller intel 8259 verilog code for 8254 timer C82380 8259 Programmable Peripheral Interface intel 82380 8254 vhdl code 8254 vhdl intel 80386 block diagram C82380 abstract |
|
|||
| Abstract: 82C356 82C356 peripheral controller contains the address buffers used to interface between the processor address , peripheral controller that incorporates: two 8237 DMA controllers, two 8259 interrupt controllers, one 8254 , peripheral controller. The CHIPSet supports a local CPU bus, a 32-bit memory bus, and AT buses. Features • , direct mapped cache 0 Supports 4 blocks (variable size from 4KB to 4MB) of main memory as programmable , Programmable wait states and RAS precharge time for each block (2 pair of banks) o Supports 256KB 256KB, 1MB, and ... | OCR Scan |
2 pages, |
Non-Pipelined processor CS82310 82C356 82C355 82C351 486DX 386DX 386DX chipset 0Q040CH 386/AT 0Q040CH abstract |
|
|||
| Abstract: peripheral controller. The CHIPSet supports a local CPU bus, a 32-bit memory bus, and AT buses. Features • , direct mapped cache 0 Supports 4 blocks (variable size from 4KB to 4MB) of main memory as programmable , Programmable wait states and RAS precharge time for each block (2 pair of banks) o Supports 256KB 256KB, 1MB, and , Data Buffer The 82C355 82C355 bus controller contains the data buffers used to interface the local and system , The 82C355 82C355 is available in a 120-pin PFP package. 82C356 82C356 Peripheral Controller The 82C356 82C356 peripheral ... | OCR Scan |
2 pages, |
82C356 3870X 486DX CS82310 82C35 cache controller 82C351 82C355 Non-Pipelined processor CHIPS TECHNOLOGIES IC 386 ic LM 386 8259 Programmable Peripheral Interface 386DX 0Q040CH CS82310 0Q040CH abstract |
|
|||
| Abstract: amplifiers 8259-compatible Programmable Peripheral 8255 standard with three 8-bit ports Interface Extended Programmable 8254-compatible with three independent Interval Timer 16-bit counters Serial , (PCMCIA) Personal Computer Memory Card Industry Association PCI Peripheral Component , Counter, UART. Programmable USART 8251-compatible and 16450-compatible devices Real Time Clock Cell VC01 Multimedia codec IQDAC Low-power I/Q digital-to-analog interface Data Codec ... | Original |
2 pages, |
PCI, 8251 MC01 Interfacing of LCD with ARM7 AT8051 interfacing 8051 with 8255 8251 DMA controller 8259 microcontroller 8254 with 8051 UART 8251 8255 usart ATMEL MICROCONTROLLER 16 BIT interfacing of 8237 with 8051 USART 8251 interfacing datasheet abstract |
|
|||
| Abstract: , interface module, or Southbridge component of personal computer chipsets. The AMD-768 AMD-768 peripheral bus , ) Legacy-AT Compatible Logic: ¾ 5 Interrupt Controller (8259-based) The AMD-768 AMD-768 peripheral bus , AMD-768TM AMD-768TM Peripheral Bus , chipset. Extended performance is offered by the 66-MHz/64-bit/32-bit PCI bus and a feature-rich peripheral , ) memory technology, and AGP-4X Graphics Interface. The AMD-760 AMD-760 MPX chipset consists of the following ... | Original |
9 pages, |
PC2100 AMD BGA AMD-760 AMD-762 AMD-766 AMD-768 Athlon 64 Athlon MP datasheet AMD Athlon 64 8259 programmable interval timer AMD-760TM 8259 Programmable Peripheral Interface 35x35 bga AMD-760 abstract |
|
|||
| Abstract: (GPIO) functionality AT-compatible Interrupt Controller (8259-based) Programmable interval timer , .7 AMD-766TM AMD-766TM Peripheral Bus Controller , Rate) memory technology, and AGP-4X Graphics Interface. Together with other sophisticated core logic , components. · AMD-762TM AMD-762TM system controller (Northbridge) · AMD-766TM AMD-766TM peripheral bus controller (Southbridge). , of memory space) · AGP-4X Graphics Interface (supports 1X and 2X modes) · PCI 2.2 Compliant 33 MHz ... | Original |
8 pages, |
AMD Athlon 64 AMD BGA AMD-760 AMD-760TM AMD-762 AMD-766 Athlon 64 Athlon MP datasheet PC2100 amd motherboard southbridge 24229C AMD-760TM abstract |
|
|||
| Abstract: ) INTEGRATED PERIPHERAL CONTROLLER WITH SUPPPORT FOR EXTERNAL RTC ULTRA DMA-66 DMA-66 IDE CONTROLLER POWER MANAGEMENT UNIT 16-BIT 16-BIT LOCAL BUS INTERFACE I2C BUS CONTROLLER UART (1 RxTx) IEEE 1149.1 JTAG INTERFACE 8 GENERAL PURPOSE IO PROGRAMMABLE CLOCKS 0.18 MICRON TECHNOLOGY 1.8 V CORE & 3.3 V I/Os LOW POWER , SDRAM Interface 64-bit data bus 100 MHz maximum SDRAM clock 8 MByte to 256 MByte memory size (only , parts Supports buffered and non-buffered DIMMs Supports registered DIMMs Programmable latency ... | Original |
4 pages, |
VEGA PBGA388 Mac-1 CRC-16 8259 Programmable Peripheral Interface DMA Controller 8237 802.3 CRC32 datasheet abstract |
|
|||
| Abstract: PORT USB HOST CONTROLLER (OCHI) 10/100 ETHERNET MAC INTEGRATED PERIPHERAL CONTROLLER WITH SUPPPORT FOR EXTERNAL RTC ULTRA DMA-66 DMA-66 IDE CONTROLLER POWER MANAGEMENT UNIT 16-BIT 16-BIT LOCAL BUS INTERFACE I2C BUS CONTROLLER UART (1 RxTx) IEEE 1149.1 JTAG INTERFACE Eight GENERAL PURPOSE IO PROGRAMMABLE , with multiplication factors of X1, X2, X2.5, X3, X3.5 SDRAM Interface 64-bit data bus 100 MHz , DIMMs Programmable latency s s s s s s s s s s s s s s s s s s s s s s s ... | Original |
5 pages, |
PBGA388 CRC-16 Intel 8237 dma controller block diagram datasheet abstract |
|
|||
| Abstract: 1) INTEGRATED PERIPHERAL CONTROLLER WITH SUPPPORT FOR EXTERNAL RTC ULTRA DMA-66 DMA-66 IDE CONTROLLER POWER MANAGEMENT UNIT 16-BIT 16-BIT LOCAL BUS INTERFACE I2C BUS CONTROLLER UART (1 RxTx) IEEE 1149.1 JTAG INTERFACE 8 GENERAL PURPOSE IO PROGRAMMABLE CLOCKS 0.18 MICRON TECHNOLOGY 1.8 V CORE & 3.3 V I/Os LOW , SDRAM Interface 64-bit data bus 100 MHz maximum SDRAM clock 8 MByte to 256 MByte memory size (only , parts Supports buffered and non-buffered DIMMs Supports registered DIMMs Programmable latency ... | Original |
4 pages, |
VEGA PBGA388 DMA Controller 8237 CRC-16 8259 Programmable Peripheral Interface datasheet abstract |
|
|||
| Abstract | Saved from | Date Saved | File Size | Type | Download |
| Over 1.1 million files (1986-2013): html articles, reference designs, gerber files, chemical content, spice models, programs, code, pricing, images, circuits, parametric data, RoHS data, cross references, pcns, military data, and more. Please note that due to their age, these files do not always format correctly in modern browsers. Disclaimer. |
|||||
| cascadable up to a maximun of 64 levels. Programmable Peripheral Interface Following the 8255 standard -standard microcontroller peripherals include: Programmable USART Atmel offers the choice between an 8251-compatible and 100-year calendar, programmable periodic interrupts and a RAM interface. Power consumption is microprocessor interface. Extended Programmable Interval Timer This 8254-compatible device features three Cell-based ASICs Microcontroller Peripherals www.datasheetarchive.com/files/atmel/atmel/peripher-v4.htm |
Atmel | 30/06/1999 | 18.6 Kb | HTM | peripher-v4.htm |
| cascadable up to a maximun of 64 levels. Programmable Peripheral Interface Following the 8255 standard -standard microcontroller peripherals include: Programmable USART Atmel offers the choice between an 8251-compatible and 100-year calendar, programmable periodic interrupts and a RAM interface. Power consumption is microprocessor interface. Extended Programmable Interval Timer This 8254-compatible device features three EPROM Field Programmable Gate Array Flash Memory/DataFlash FPGA Configuration Memory www.datasheetarchive.com/files/atmel/atmel/peripher-v1.htm |
Atmel | 26/02/2001 | 20.51 Kb | HTM | peripher-v1.htm |
| cascadable up to a maximun of 64 levels. Programmable Peripheral Interface Following the 8255 standard -standard microcontroller peripherals include: Programmable USART Atmel offers the choice between an 8251-compatible and 100-year calendar, programmable periodic interrupts and a RAM interface. Power consumption is microprocessor interface. Extended Programmable Interval Timer This 8254-compatible device features three EPROM Field Programmable Gate Array Flash Memory/DataFlash FPGA Configuration Memory www.datasheetarchive.com/files/atmel/atmel/peripher.htm |
Atmel | 07/05/2002 | 20.25 Kb | HTM | peripher.htm |
| cascadable up to a maximun of 64 levels. Programmable Peripheral Interface Following the 8255 standard -standard microcontroller peripherals include: Programmable USART Atmel offers the choice between an 8251-compatible and 100-year calendar, programmable periodic interrupts and a RAM interface. Power consumption is microprocessor interface. Extended Programmable Interval Timer This 8254-compatible device features three ATMEL CBICs: Microcontroller Peripherals Microcontroller www.datasheetarchive.com/files/atmel/atmel/cbic/peripher.bak |
Atmel | 14/09/1998 | 13.13 Kb | BAK | peripher.bak |
| cascadable up to a maximun of 64 levels. Programmable Peripheral Interface Following the 8255 standard -standard microcontroller peripherals include: Programmable USART Atmel offers the choice between an 8251-compatible and 100-year calendar, programmable periodic interrupts and a RAM interface. Power consumption is microprocessor interface. Extended Programmable Interval Timer This 8254-compatible device features three ATMEL CBICs: Microcontroller Peripherals Microcontroller www.datasheetarchive.com/files/atmel/atmel/peripher-v3.htm |
Atmel | 26/05/1998 | 9.84 Kb | HTM | peripher-v3.htm |
| cascadable up to a maximun of 64 levels. Programmable Peripheral Interface Following the 8255 standard -standard microcontroller peripherals include: Programmable USART Atmel offers the choice between an 8251-compatible and 100-year calendar, programmable periodic interrupts and a RAM interface. Power consumption is microprocessor interface. Extended Programmable Interval Timer This 8254-compatible device features three ATMEL CBICs: Microcontroller Peripherals Microcontroller www.datasheetarchive.com/files/atmel/atmel/peripher-v2.htm |
Atmel | 14/09/1998 | 13.14 Kb | HTM | peripher-v2.htm |
| . Each peripheral function can be individually disabled. System Interface functions include two 8237 programmable for each interrupt line. A PCIway Serial Interrupt interface (Master or Slave mode) is supported provides Fast GateA20 and I/O peripheral design flexibility. Advanced Configuration and Power Interface compatible peripherals; 2 Programmable I/O range Chip Selects; 1 Programmable Memory Range; 1 programmable remappable Chip Select; DS1287 DS1287 DS1287 DS1287 style Real-Time Clock; X86 CPU interface support Two 8259 Interrupt www.datasheetarchive.com/files/national/docs/wcd0000c/wcd00c8a.htm |
National | 03/04/1998 | 9.71 Kb | HTM | wcd00c8a.htm |
| off-chip. C8259A Programmable Interrupt Controller October12, 1998 Product Specification C8259A Programmable Interrupt Controller c8259a.fm Page 2 Tuesday, October 6, 1998 11:23 AM General Description The C8259A Programmable Interrupt Controller core man- ages up to 8 vectored priority interrupts -directional 8-bit buffer is used to interface the C8259A core to the system Data Bus. Control words and status (IRR) and the In-Service Register (ISR). The IRR is used to store all Figure 1: C8259A Programmable www.datasheetarchive.com/download/55018419-977412ZC/rp069e2.zip (c8259a.pdf) |
Xilinx | 22/02/2000 | 3361.97 Kb | ZIP | rp069e2.zip |
| /Counter M8255 M8255 M8255 M8255 Programmable Peripheral Interface UART C8259A Programmable Interrupt Controller X_DES Cryptoprocessor CC143s UTOPIA Slave Interface 10/100 Ethernet MAC Descrambler UTOPIA Level 2 PHY side TX interface UTOPIA Level 2 PHY side RX interface Flip805x-PR Core www.datasheetarchive.com/files/xilinx/docs/rp0000a/rp00aaf.htm |
Xilinx | 29/02/2000 | 13.31 Kb | HTM | rp00aaf.htm |
| ;Peripheriebausteine;Intel;intel i8259;dil28b;i8259;i8085 Peripheral;i8085 Peripheriebaustein;Peripherals ;Periphals;Peripheriebausteine;Philips;philips tms9901;dil40;TMS9901 TMS9901 TMS9901 TMS9901;TMS99 TMS99 TMS99 TMS99 System Interface programmable;TMS99 TMS99 TMS99 TMS99 System-Interface programmierbar;Programmable . dp83815;tqfp144;DP83815VNG DP83815VNG DP83815VNG DP83815VNG;10/100MBit/s Ethernet PCI ;Periphals;Peripheriebausteine;National Semiconductor;nsc i8237;dil40;i8237;i8085 Peripheral;i8085 i8250;dil40;i8250;i8085 Peripheral;i8085 Peripheriebaustein;Peripherals www.datasheetarchive.com/download/48664731-299145ZC/bae65022linux.tgz |
Kaleidoscope | 22/08/2005 | 11421.08 Kb | TGZ | bae65022linux.tgz |