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TL28L92FR Texas Instruments 3.3-V/5-V Dual Universal Asynchronous Receiver/Transmitter 44-QFP 0 to 70 visit Texas Instruments Buy
TL28L92IFR Texas Instruments 3.3-V/5-V Dual Universal Asynchronous Receiver/Transmitter 44-QFP -40 to 85 visit Texas Instruments Buy
HD3-6402R-9Z Intersil Corporation CMOS Universal Asynchronous Receiver Transmitter (UART); CERDIP40, PDIP40; Temp Range: See Datasheet visit Intersil Buy
HD3-6402R-9 Intersil Corporation CMOS Universal Asynchronous Receiver Transmitter (UART); CERDIP40, PDIP40; Temp Range: See Datasheet visit Intersil Buy
PC16550DVX/NOPB Texas Instruments Universal Asynchronous Receiver/Transmitter with FIFOs 44-PLCC 0 to 70 visit Texas Instruments
PC16550DN/NOPB Texas Instruments Universal Asynchronous Receiver/Transmitter with FIFOs 40-PDIP 0 to 70 visit Texas Instruments Buy

8251 UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER

Catalog Datasheet MFG & Type PDF Document Tags

8251A programmable communication interface

Abstract: 8251 microprocessor block diagram DESCRIPTION The 8251A is the enhanced version of the industry standard 8251 Universal Synchronous/Asynchronous Receiver/Transmitter (USART) designed for data communications with microprocessor families, such , CHARACTERISTICS â'¢ SMD/DESC qualified â'¢ Synchronous baud rate-DC to 64K baud â'¢ Synchronous and asynchronous operation â'¢ Asynchronous baud rate-DC to 19.2K baud â'¢ Synchronous 5-8-bit characters; internal or , between Writes for Asynchronous Mode is 8tCv and for Synchronous Mode is 16tCY-6. Reset Pulse Width = 6tcy
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intel 8251

Abstract: intel 8251 USART ® 8251 Universal Synchronous/Asynchronous Receiver/Transmitter (USART), designed for data communications , irry 18251A APM©! PROGRAMMABLE COMMUNICATION INTERFACE INDUSTRIAL a Synchronous and Asynchronous Operation â  Synchronous 5-8 Bit Characters; Internal or External Character Synchronization , '¢ In asynchronous operations, the Receiver detects and handles "break" automatically, relieving the CPU , . Recovery Time between Writes tor Asynchronous Mode is 8 tcy and for synchronous Mode is 16 tcy- 5. The TxC
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8251 microprocessor block diagram

Abstract: operation of 8251 microprocessor enhanced version of the industry stan dard 8251 Universal Synchronous/Asynchronous Receiver/Transmitter , CHARACTERISTICS SMD/DESC qualified Synchronous and asynchronous operation Synchronous 5 - 8-bit characters; internal or external character synchronization; automatic sync insertion Asynchronous 5 - 8-bit characters , baud Asynchronous baud rate - DC to 19.2K baud Full-duplex, double-buffered transmitter and receiver , for Asynchronous Mode is 8tcy and for Synchronous Mode is 16tcY6. Reset Pulse Width = 6tcY minimum
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Intel 8251

Abstract: intel 8251 USART version of the industry standard, Intel® 8251 Universal Synchronous/Asynchronous Receiver/Transmitter , Asynchronous Operation i Synchronous 5-8 Bit Characters; Internal or External Character Synchronization , Synchronous Baud Rate â'" DC to 64K Baud Military Temperature Range: - 55°C to + 125°C Asynchronous Baud , simplifies control programming and minimizes CPU overhead. â'¢ In asynchronous operations, the Receiver , only when TxRDY = 1. Recovery Time between Writes for Asynchronous Mode is 8 tQy and for Synchronous
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USART 8251

Abstract: intel 8251 The Intel® 8251A is the enhanced version of the industry standard, Intel® 8251 Universal Synchronous/Asynchronous Receiver/Transmitter (USART), designed for data communications with Intel's new high performance , 8251A/S2657 PROGRAMMABLE COMMUNICATION INTERFACE â  Synchronous and Asynchronous Operation , minimizes CPU overhead. â'¢ In asynchronous operations, the Receiver detects and handles "break" , AFN-01573B inteT 8251A/S2657 FUNCTIONAL DESCRIPTION General The 8251A is a Universal Synchronous
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USART 8251 intel 8251 8251 IC FUNCTION microprocessors interface 8085 to 8251 intel IC 8251 S26S7

USART 8251

Abstract: intel 8251 USART higher speed and better operating margins. * Synchronous Baud rate is from DC to 64K. * Asynchronous Baud rate is from DC to 19.2K. GENERAL The MA28151 is a Universal Synchronous /Asynchronous Receiver , ) GENERAL DESCRIPTION The MA28151 is the enhanced version of the industry standard, 8251 Universal Synchronous Asynchronous Receiver/Transmitter (USART), modified for data communications with the MAS281 , programming and minimizes CPU overhead. * In synchronous operations, the Receiver detects and handles "break"
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intel 8251 USART 8251 microprocessor block diagram 8251 UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER 8251 usart INTEL 8251A USART 8251 programmable interface MAS-281 MIL-M-38510

M2128-15

Abstract: M2764 ; Automatic Break Detect and Handling Synchronous Baud Rate-DC to 64K Baud The Intel M8251A is the enhanced version of the industry standard, Intel 8251 Universal Synchronous/ Asynchronous Receiver , Asynchronous Baud Rate-DC to 19.2K Baud Full-Duplex, Double-Buffered Transmitter and Receiver Error , Clock Synchronous and Asynchronous Operation Synchronous 5-8 Bit Characters; Internal or External Character Synchronization; Automatic Sync Insertion Asynchronous 5-8 Bit Characters; Clock Rate-1,16, or 64
Intel
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M2764 M2128-15 M8755A M8748 M8035L application USART 8251 MIL-STD-883B MR2I28 MR2147H MR2I48H MR2167 MR2164

intel 8251 USART

Abstract: intel IC 8255 Universal Synchronous/Asynchronous Receiver/Transmitter (USART) is contained on the SBC 80/10. A jumper , , 98-206. ISIS-II Systems User's Guide, 98-306. ICE-80 Operator's Manual, 98-185 "Using the 8251 Universal Synchronous/Asynchronous Receiver/Trans mitter". AP-16. "8255 Programmable Peripheral Interface Applications , be programmed by the user's system software to select the desired asynchronous or synchronous serial , , provide a direct interface to tele types, CRTs, asynchronous and synchronous modems, and other RS232C
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intel IC 8255 SBC 8251 Fluke 8375 ic 8255 intel CT5002 schematic diagram of scada system AP-26 PL/M-80 AP-15

8251 microprocessor block diagram

Abstract: microprocessors interface 8086 to 8251   Available In EXPRESS and Military Versions The Intel® 8251A is the industry standard Universal Synchronous/Asynchronous Receiver/Transmitter (USART), designed (or data communications with Intel's .microprocessor , minimizes CPU overhead. â'¢ In asynchronous operations, the Receiver detects and handles "break" , rate from DC to 64K. FUNCTIONAL DESCRIPTION General The 8251A is a Universal Synchronous/Asynchronous Receiver/Transmitter designed for a wide range of Intel microcomputers such as 8048, 8080, 8085
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microprocessors interface 8086 to 8251 features of 8251 microprocessor operation of 8251 microprocessor microprocessors interface 8086 with 8251 intel 8251 uart intel 8251 USART control word format MCS-48 APX-86 20S222-26

USART 8251

Abstract: microprocessors interface 8086 to 8251 DESCRIPTION General The 8251A is a Universal Synchronous/Asynchronous Receiver/Transmitter designed for a , intel 8251A PROGRAMMABLE COMMUNICATION INTERFACE Synchronous and Asynchronous Operation , EXPRESS and Military Versions The Intel® 8251A is the industry standard Universal Synchronous/Asynchronous Receiver/Transmitter (USART), designed for data communications with Intersjnnicroprocessor , '¢ In asynchronous operations, the Receiver detects and handles "break" automatically, relieving the CPU
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serial port 8251 8251A programmable communication interface INTEL 8251A pin configuration of 8251 usart interface z 80 with 8251a usart block diagram 8251A

8251 IC FUNCTION

Abstract: block diagram 8251 TTL-compatible logic levels GENERAL DESCRIPTION The 8251 /Am9551 is a programmable serial data commu nication interface that provides a Universal Synchronous/ Asynchronous Receiver/Transmitter (USART) function. It is , 8251/Am9551 Programmable Communication Interface ¡APX86 Family MILITARY INFORMATION 8251/Am9551 DISTINCTIVE CHARACTERISTICS · · · · · Separate control and transmit register input buffers Synchronous or asynchronous serial data transfer Parity, overrun, and framing errors detected Half- or full-duplex signaling
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block diagram 8251 IC 8251 block diagram J941 Block Diagram of 8251 usart ic 8251 processor 8251 pin diagram 8251/A

8251 microprocessor block diagram

Abstract: intel 8251 USART industry standard Universal Synchronous/Asynchronous Receiver/Transmitter (USART), designed for data , from DC to 64K. FUNCTIONAL DESCRIPTION General The 8251A is a Universal Synchronous/Asynchronous , INTERFACE â  Synchronous and Asynchronous Operation â  Synchronous 5-8 Bit Characters; Internal or , Detection; Automatic Break Detect and Handling Synchronous Baud Rate-Baud -DC to 64K Asynchronous Baud , minimizes CPU overhead. â'¢ In asynchronous operations, the Receiver detects and handles "break"
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INTEL USART 8251 8251 intel Intel 8080 instruction set pin diagram 8251A 8251A D8251A 00734S4 T-75-37-07 007345S 00734SL D0734S7
Abstract: logic levels GENERAL DESCRIPTION The 8251/Am9551 is a programmable serial data commu­ nication interface that provides a Universal Synchronous/ Asynchronous Receiver/Transmitter (USART) function. It is , 8251/Am9551 Programmable Communication Interface ¡APX86 Family M ILITARY IN FO R M A TIO N Separate control and transmit register input buffers Synchronous or asynchronous serial data transfer , associated processor. This provides an unusual degree of flexibility and allows the 8251/ Am9551 to service -
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WF006490 TC003851

8251 IC FUNCTION

Abstract: intel 8251 The Intel® 8251A is the industry standard Universal Synchronous/Asynchronous Receiver/Transmitter , A. General The 8251A is a Universal Synchronous/Asynchronous Receiver/Transmitter designed for a , in tJ . 8251A PROGRAMMABLE COMMUNICATION INTERFACE â  Synchronous and Asynchronous Operation â  Asynchronous Baud Rateâ'"DC to 19.2K Baud â  Synchronous 5 -8 Bit Characters; Internal or , Transmitter and Receiver â  Asynchronous 5 -8 Bit Characters; Clock Rateâ'" 1, 16 or 64 Times Baud Rate
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USART 8251

Abstract: 8251 pin diagram TTL-compatible logic levels GENERAL DESCRIPTION The 8251/Am9551 is a programmable serial data communication interface that provides a Universal Synchronous/ Asynchronous Receiver/Transmitter (USART) function. It Is , synchronization > Synchronous or asynchronous serial data transfer â'¢ Odd parity, even parity, or no parity bit , 8251/Am9551 Programmable Communication Interface ¡APX86 Family MILITARY INFORMATION , processor. This provides an unusual degree of flexibility arid allows the 8251/ Am9551 to service a wide
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8251 pin configuration of 8251 teradyne 8251 pin 8251 UNIVERSAL SYNCHRONOUS ASYNCHRONOUS transmitter 8251 usart applications

USART 8251

Abstract: microprocessors interface 8086 to 8251 DESCRIPTION General The 8251A is a Universal Synchronous/Asynchronous Receiver/Transmitter designed for a , and Military Versions The Intel® 8251A is the industry standard Universal Synchronous/Asynchronous , iniel 8251A PROGRAMMABLE COMMUNICATION INTERFACE Synchronous and Asynchronous Operation , CPU overhead. â'¢ In asynchronous operations, the Receiver detects and handles "break" automatically , serial data out of the 8251 A. Receiver Buffer The Receiver accepts serial data, converts this serial
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28 pin configuration of 8251 QQ00D0Q00QG0

8251 microprocessor block diagram

Abstract: features of 8251 microprocessor the industry stan dard, 8251 Universal Synchronous/Asynchronous Receiv er/Transmitter (USART , PRODUCT OVERVIEW General The 8251A is a Universal Synchronous/Asynchronous Re ceiver/Transmitter designed , · · · Synchronous and Asynchronous Operation Synchronous 5 - 8 Bit Characters; Internal or External , Detection; Automatic Break Detect and Handling Synchronous Baud R a te -D C to 64K Baud Asynchronous Baud R , byte (asynchronous mode). RxRDY (Receiver Ready) This output indicates that the 8251A contains a
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I8251A b261a 8251AP AMD 8251 USART WF006180

8251 microprocessor block diagram

Abstract: I8251A the industry standard Universal Synchronous/Asynchronous Receiver/Transmitter (USART), designed for , COMMUNICATION INTERFACE Synchronous and Asynchronous Operation Synchronous 5 -8 Bit Characters; Internal or , Detection; Automatic Break Detect and Handling Synchronous Baud Rate-DC to 64K Baud Asynchronous Baud Rate , . FEATURES AND ENHANCEMENTS FUNCTIONAL DESCRIPTION General The 8251A is a Universal. Synchronous/Asynchro , , when off, holds RxRDY in the Reset Con dition. For Asynchronous mode, to set RxRDY, the Receiver must
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intel 8085 minimal system 8251 with 8086 intel PLD 007S727

am9551

Abstract: 955L CHARACTERISTICS · · · · · Separate control and transm it register input buffers Synchronous or asynchronous , nication interface that provides a Universal S ynchronous/ Asynchronous R eceiver/Transm itter (USART , synchronous mode and 4.5 times the receive or transmit rate in the asynchronous mode. The CLK frequency is , between data transfer baud rate and receiver or transm itter clock rate. Asynchronous serial data may be , data character. For synchronous and asynchronous modes, bits 4 and 5 determ ine w hether there will be
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am9551 955L M955L AM9551PC 02334B WF006520 WF006530 WF006560

8251 microprocessor block diagram

Abstract: features of 8251 microprocessor Versions The Intel® 8251A is the industry standard Universal Synchronous/Asynchronous Receiver , . FUNCTIONAL DESCRIPTION General The 8251A is a Universal Synchronous/Asynchronous Receiver/Transmitter , 8251A PROGRAMMABLE COMMUNICATION INTERFACE Synchronous and Asynchronous Operation Synchronous 5 , minimizes CPU overhead. · In asynchronous operations, the Receiver de tects and handles " break , out of the 8251 A. Receiver Control This functional block manages all receiver-related activities
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intel 8085 A control unit microprocessor 8251 applications
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