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Part Manufacturer Description Datasheet BUY
HXR8212-EVB Integrated Device Technology Inc BOARD-0, Box visit Integrated Device Technology
HXR8212-DNT Integrated Device Technology Inc WAFER-0, Box visit Integrated Device Technology
HXT8212-EVB Integrated Device Technology Inc BOARD-0, Box visit Integrated Device Technology
HXT8212-DNT Integrated Device Technology Inc WAFER-0, Box visit Integrated Device Technology
SN98212P Texas Instruments Dual General-Purpose Operational Amplifier 8-PDIP visit Texas Instruments
CD4099BKMSR Intersil Corporation 4000/14000/40000 SERIES, LOW LEVEL TRIGGERED D LATCH, TRUE OUTPUT, CDFP16, CERAMIC, DFP-16 visit Intersil

8212 latch

Catalog Datasheet MFG & Type PDF Document Tags

intel 8212

Abstract: D 8212 intel State Outputs â  Outputs Sink 15 mA The 8212 input/output port consists of an 8-bit latch with 3 , Latch Here the 8212 is used as the status latch for an 8080A microcomputer system. The input to the 8212 latch is directly from the8080A data bus. Timing shows that when the SYNC signal is true, which is , LATCH D> °0 8212 CLR ds2 md DS, =r¡3 â  INTA â'¢ WÃ â  STACK â  HLTA â  OUT . Ml â , inter 8212 8-BIT INPUT/OUTPUT PORT â  Fully Parallel 8-Bit Data Register and Buffer â
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8085 microprocessor realtime application

Abstract: fabrication of 8085 microprocessor . A data latch is required to avoid losing the data when the three-state bus drivers return to their high-impedance state. The-rising edge of STAT strobes the data into the 8212 latch and, after some propagation , CLR STG DO I Oil 002 012 8212 007 017 i8 018 OS? td DBO OBI CLK A0758I DB6 _ STAT 0B7 _ , available to latch the data internally, and becomes necessary when the AD7581 is used in 8085 systems and , would cause unnecessary transients at the memory latch. The decoder requires a read-strobe signal, which
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8085 microprocessor realtime application fabrication of 8085 microprocessor 8085 microprocessor realtime application any one 8085 microprocessor four channel data acquisition system 8212 latch

IC 8212

Abstract: f 8212 LATCH SETS SR FLIP FLOP (NO EFFECT ON OUTPUT BUFFER) 2-56 AFN-00731C 8212 ABSOLUTE MAXIMUM , Input Port 2-59 8212 808A Status Latch Here the 8212 Is used as the status latch fo r an 8080A m icro com p uter system. The inpu t to the 8212 latch is d ire c tly fro m the 8080A data bus. T im , latched in to the 8212. Note: The m ode signal is tied h igh so that the ou tput on the latch is active , ¡n te f 8212 8-BIT INPUT/OUTPUT PORT Fully Parallel 8-Bit Data Register and Buffer Service
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IC 8212 f 8212 F8212 SR flip flop IC processor 8212 sr flip flop APN-00731C 00731C

block and pin diagram of 8257

Abstract: IC 8212 internal block diagram the DMA address registers) to the 8212 latch via the data bus. These address bits will be transferred , ) device which, when coupled with a single Intel® 8212 I/O port device, provides a complete four-channel , memory address to the 8212 I/O port via the data bus (the 8212 places these address bits on lines A8-A15 , memory address into the 8212 device from the data bus. (AEN) Address Enable: This output is used to , \ DATA BUS \ DRQO DACK 0 8257 AND 8212 DRO 1 DACK t DIRQ 2 DACK 2 DflQ 3 DACK 3 SYSTEM RAM
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block and pin diagram of 8257 IC 8212 internal block diagram DMA Controller 8257 intel 8257 dma 8257 DIWA 200 MCS-85 TCY-100 T9-50 AFN-01840B

AR8161

Abstract: ARM DII 0238 an 8212 latch. The latch is interfaced to the BUS PORT on the 8049 and is enabled whenever the WR pin , 8049 to the outside world one 8212 latch was used. This latch was connected to the BUS PORT and is , this configuration, the 8212 was used to hold the data until read by the 8049. The connection of the 8212 to the 8049 is shown in Figure 3.4 and the parallel port timing diagram is shown in Figure 3.5. The 8212 parallel port was connected to the LINE PRINTER OUTPUT of an INTELLEC MICROCOM PUTER
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AR8161 ARM DII 0238 KEYBOARD CONTROLLER 8049 intel 8049 microcomputer b175 transistor b342 transistor AP-91 AFN-01364A-01

block and pin diagram of 8257

Abstract: IC 8212 internal block diagram w ith a single Intel® 1 8212 I/O po rt device, provides a com plete four-channel DM A co n tro lle r , eight bits of the m em ory address to the 8212 I/O port via the data bus (the 8212 places these address , ignifica nt eig h t-b its of the m em ory address (from one o f the DM A address registersi to the 8212 latch via the data bus. These address bits w ill be transferred at the beginning o f the DMA cycle: the , em ory address into the 8212 device from the data bus. (AEN) Address Enable This ou tput is used to
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ic 8257 block diagram i8257 d8257 bu 808 af intel 8257 interrupt controller pin diagram of 8257

B331 transistor

Abstract: transistor b331 and can tolerate much higher levels of current. The print head drivers are connected to an 8212 latch. The latch is interfaced to the BUS PORT on the 8049 and is enabled whenever the WR pin and the BIT 4 , 1 21 2 19 3 17 4 15 5 10 6 8 7 6 a> â C* DOe DO? Die Dl? DOe DOs 8212 Die nis DO4 DO3 DU Dli DO2 DO1 DI2 Dh DO1 DSi INT D11 ÃU2 Di' noi ÃI11 noi ni4 DOs 8212 Die noe Die DO , LINEFEED DRIVER 1 OPTO-TRIAC MOTOR DRIVER * THE 8212 AND THE 2716 WOULD NOT BE NEEDED IF AN 8049 WAS
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B331 transistor transistor b331 Transistor B28D A 42 B331 transistor A 92 B331 transistor A 42 B331 AP-27 AP-54

8085 hardware timing diagram manual

Abstract: 8085 opcode sheet free , as shown in Figure 2-6. This approach uses the 8212 latch to separate the address and data lines for , 'LS 00 AO A1 8212 A2 8 BIT ¿o LATCH ^ A4 A5 A6 A7 'LS 04 ss04 O IRQ RESET D0â'"D7 R/W RSO RS1 RS2 , .3-2 3.4 COUNTER LATCH 3.5 EXAMPLE COUNTER 3.5.1 Writing to a Timer Latch , : IN RXXX (READ INSTRUCTION) OUT WXXX (WRITE INSTRUCTION) Further, when writing to a timer latch or
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MC6840 8085 hardware timing diagram manual 8085 opcode sheet free 8085 opcode sheet opcode sheet 8085 8085 pin MC6840UM MC6800 MC6802 92RPM

8355 8755 intel microprocessor block diagram

Abstract: MCS-48 the eight bit address out on the bus and strobes it into the 8212 latch with the ALE (Address Latch , shown. The additional component required is the 8212 eight bit latch. This latch is loaded, when ever a , appropriate latch. The latches are loaded by the write pulse (WR) whenever the proper address is presented to , lower four addresses (A 3 -A0 ) are stored in a latch which addresses the multiplexer. The coincidence , F 3 14 I/O U N C O M M IT T E D D l5 d i4 8212 do D1 p 17 p 16 h s p 14 p 13
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8355 8755 intel microprocessor block diagram MCS-48 8755 intel microprocessor block diagram MCS48 instruction set MCS-48 Manual The Expanded MCS-48 System 98-413B MCS-48TM NL-10Q6

microprocessor 8212 block diagram

Abstract: F 8212 part of American Microsemi's 8080 support family.The 8212 can be used to implement latches, gat ed , system can be implemented with this device. The MCB8212/MCD8212 includes an 8-bit latch with output , -Bit data latch and buffer Service request flip-flop for generation and control of interrupts 0.25 mA input load current Outputs sink 15 mA Asynchronous latch clear 3.65V output for direct interface to , 3.65 -1 5 4.0 4.0 -7 5 20 8212 MCD8212 90 90 145 130 V V V V mA (¿A mA mA VF = 0.45V VF = 0.45V
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microprocessor 8212 block diagram 8212 microprocessor 8212 8212 functional block diagram 51406 MCB8212 D71T77S 00D0D2 TL/F/6624-11 17S-- MCBB212

IC 8212

Abstract: f 8212 structure versatility of the DAC-8212. Data loading into its 12-bit wide data latch is simplified by the use , entire 12-bit word is then loaded into the DAC-8212's data latch on the next write cycle. An alternate , in Die Form DUAL 12-BIT BUFFERED MULTIPLYING CMOS D/A CONVERTER DAC - 8212 WR and CS lines , FUNCTIONAL DIAGRAM ft GENERAL DESCRIPTION The DAC-8212 combines two identical 12-bit, multiplying , and track ing over the full operating temperature range. The DAC-8212 consists of two thin-film R
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DAC8212FV DAC8212HP dac8212 dac-8212 PMI IC 8212 internal pin diagram IC 8212 control word register 24-PIN DAC8212AV DAC8212BV DAC8212EV DAC8212GP

f 8212

Abstract: ented w ith the Am8212. The Am 8212 in p u t/o u tp u t p o rt consists o f an 8-latch w ith 3-state o , D 8212 P8212 A M 8 21 2 X C Am8212 M D (Mode) F U N C T IO N A L D E S C R IPTIO N (Cont'd , source o f the clock in p u t (C) to the data latch. Data Latch The 8 flip -flo p s th a t make up the data latch are o f a " D " type design. The o u tp u t (Q) o f the flip -flo p w ill fo llo w the , f clock (C) to the data latch is fro m the device selection logic (D 5 i â'¢ DS2 ). The d ata
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2sk105

Abstract: HD10116 Latch clock Latch output Clock output T h is the timing in which the upper level comparator compares V in and V ref and latch the result. T l is the timing in which the lower level comparator , Latch ou tpu t data delay C lo c k ou tpu t delay N ote) TA TB 4 10 5 40 22 5 4 40 ns ns ns ns , 8212 13012 56012 56012 56012 8212 13012 8212 13012 56012 56012 56012 56012 5612 5612 5612 5612 2.7k 12
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2SC2408 1S1587 HD10116 2sk105 Transformer - 12-0-12, 1 mA 358P LSE transformer RC 5612 FCX20220A-1/-2 NEB9640-HP 2SA1206 2SK105

POWER MODULE SVI 3101 D

Abstract: bc power module svi 3101 d RAM Refresh Controller New Product Announcement.5-99 I/O 8212 8-Bit I/O Port Functional Description.5-101 System Applications oi the 8212 .5-103 Data Sheet , array and the address latch or the incrementer/ decrements circuit. The address tatch receives data from , incrementer/ decrementar circuit. The incrementer/décrémenter circuit receives data from the address latch , -bit latch that, in turn, drives the data bus output buffers. The output buffers are switched off during
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POWER MODULE SVI 3101 D bc power module svi 3101 d SVI 3206 SVI 3101 POWER MODULE SVI 3101 temperature digital display JUMO Lan M

IC 8212

Abstract: 8212D A m 3 2 1 2 · A m 8212. The mode signal is tied high so that the output on the latch is active and , consists of an 8-latch w ith 3-state output buffers along w ith control and device selection logic, w hich , A M To p V ie w " i d m d · 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 Am 3212 Am 8212 19 , Latch M D (Mode) The 8 flip-flops that make up the data latch are of a " D " type design. The output , w ill occur when the clock (C ) returns low. The data latch is cleared by an asynchronous reset
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8212D p3212 U 3212 M D8212 3212 Buffer M8212 9080A MIL-STD-883

8288 bus controller by intel

Abstract: 8282 octal latch /Output Port 8212/J â'" 100 Priority Interrupt Control Unit 8214/J â'" 100 4-Bit Parallel Bidirectional , Driver 8226/E â'" 125 System Controller and Bus Driver 8228/Y â'" 100 Octal Latch 8282/R 1.0W â'" Octal Latch 8283/R 1.0W â'" Clock Generator and Driver 8284A/V 1.0W â'" Octal Bus Transceiver 8286/R 1.0W â
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8288 bus controller by intel 8282 octal latch microprocessor 8286 bus controller 8288 8216 INTEL intel 8216 20-LEAD 28-LEAD Q-40-LEAD 8212/J

intel 8216

Abstract: 8282 octal latch System Controller and Bus Driver Octal Latch Octal Latch Clock Generator and Driver Octal Bus Transceiver Octal Bus Transceiver Bus Controller Bus Arbiter 8080A/Q 8212/J 8214/J 8216/E 8224/E 8226/E 8228/Y
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intel 8282 latch Intel 8214 8286 transceiver intel 8288 latch 8080a Intel 8283 E-16-LEAD 8287/R 8288/R 8289/R OS714
Abstract: -Bit N-Channel Microprocessor 8080A/Q 1.7W 8-Bit Input/Output Port 8212/J â'" 100 Priority , Driver 8226/E â'" 125 System Controller and Bus Driver 8228/Y â'" 100 Octal Latch 8282/R 1.0W â'" Octal Latch 8283/R 1.0W â'" Clock Generator and Driver 8284A/V -
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R-20-LEAD

IC LA 4127

Abstract: 8212D Am3212/Am8212 F U N C T IO N A L D E S C R IP T IO N (C ont'd) Data Latch The 8 flip -flo p s th a t m ake up th e data latch are o f a " D " typ e design. The o u tp u t (Q) o f th e flip - f lo p w ill , occur w hen the c lo c k (C) re tu rn s lo w . The d ata latch is cleared b y an asynch ro n o us reset , enables th e b u ffe r to tra n s m it th e data fro m th e o u tp u ts o f th e data latch (Q) or , e th e source o f th e c lo c k in p u t (C) to th e data latch. When M D is high ( o u tp u t m ode
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IC LA 4127 la 4127 LIC-436

intel 8212

Abstract: Signetics 54F432 Latch Multi-Mode Buffered Latch, INV (3-State) Military Logic Products , 8212 except that 54F432 has inverting outputs DESCRIPTION The 54F432 has 8 data latches with 3 , equivalent to the Intel 8212 except that the 54F432 has inverting outputs. ORDERING INFORMATION , 291 853-1225 F01393 Signetics Military Logic Products Product Specification Latch , Specification Latch 54F432 FUNCTIONAL DESCRIPTION This high-performance eight-bit parallel ex pandable
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intel 8212 54F432/BLA 54F432/BKA 54F432/B3A
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