80C528/83C528 8XC528 80C51 83C528 80C528 87C528 80C52 7/A15 6/A14 5/A13 4/A12 - Datasheet Archive

 

80C528/83C528 CMOS single-chip 8-bit microcontroller Product specification IC20 Data Handbook Philips Semiconductors 1995 Feb 02

 

INTEGRATED CIRCUITS 80C528/83C528 80C528/83C528 CMOS single-chip 8-bit microcontroller Product specification IC20 Data Handbook Philips Semiconductors 1995 Feb 02 Philips Semiconductors Product specification CMOS single-chip 8-bit microcontrollers DESCRIPTION The 8XC528 8XC528 single-chip 8-bit microcontroller is manufactured in an advanced CMOS process and is a derivative of the 80C51 80C51 microcontroller family. The 8XC528 8XC528 has the same instruction set as the 80C51 80C51. Three versions of the derivative exist: · 83C528 83C528 - 32k bytes mask programmable ROM · 80C528 80C528 - ROMless version of the 83C528 83C528 · 87C528 87C528 - 32k bytes EPROM (described multi-source, two-priority-level, nested interrupt structure, two serial interfaces (UART and I2C-bus), and on-chip oscillator and timing circuits. In addition, the 8XC528 8XC528 has two software selectable modes of power reduction - idle mode and power-down mode. The idle mode freezes the CPU while allowing the RAM, timers, serial port, and interrupt system to continue functioning. The power-down mode saves the RAM contents but freezes the oscillator, causing all other chip functions to be inoperative. in a separate data sheet) 80C528/83C528 80C528/83C528 FEATURES · 80C51 80C51 instruction set ­ 32k × 8 ROM (83C528 83C528) ­ ROMless (80C528 80C528) ­ 512 × 8 RAM ­ Memory addressing capability 64k ROM and 64k RAM ­ Three 16-bit counter/timers ­ On-chip watchdog timer with oscillator ­ Full duplex UART ­ I2C serial interface ­ Four 8-bit I/O ports · Power control modes: This device provides architectural enhancements that make it applicable in a variety of applications in consumer, telecom and general control systems, especially in those systems which need large ROM and RAM capacity on-chip. ­ Idle mode ­ Power-down mode ­ Warm start from power-down · CMOS and TTL compatible · Extended temperature ranges · ROM code protection · 7-source and 7-vector interrupt structure The 8XC528 8XC528 contains a 32k × 8 ROM (83C528 83C528), a 512 × 8 RAM, four 8-bit I/O ports, two 16-bit timer/event counters (identical to the timers of the 80C51 80C51), a 16-bit timer (identical to the timer 2 of the 80C52 80C52), a watchdog timer with a separate oscillator, a with 2 priority levels · Up to 3 external interrupt request inputs · Two programmable power reduction modes (Idle and Power-down) · Termination of Idle mode by any interrupt, external or WDT (watchdog) reset · XTAL frequency range: 1.2 MHz to 16 MHz PIN CONFIGURATIONS T2/P1.0 1 42 VDD 39 P0.0/AD0 T2EX/P1.1 2 41 P0.0/AD0 3 38 P0.1/AD1 P1.2 3 40 P0.1/AD1 P1.3 4 37 P0.2/AD2 P1.3 4 39 P0.2/AD2 P1.4 5 36 P0.3/AD3 P1.4 5 38 P0.3/AD3 P1.5 6 35 P0.4/AD4 P1.5 6 37 P0.4/AD4 SCL/P1.6 7 34 P0.5/AD5 SCL/P1.6 7 36 P0.5/AD5 SDA/P1.7 8 33 P0.6/AD6 SDA/P1.7 8 35 P0.6/AD6 RST 9 32 P0.7/AD7 RST 9 34 P0.7/AD7 T2/P1.0 2 P1.2 40 VDD 1 T2EX/P1.1 6 1 40 7 RxD/P3.0 10 TxD/P3.1 11 DUAL IN-LINE PACKAGE 31 EA RxD/P3.0 10 30 ALE NC* 11 SHRINK DUAL IN-LINE PACKAGE 39 LEADED CHIP CARRIER 17 29 18 28 44 34 33 EA 32 NC* INT0/P3.2 12 29 PSEN 31 ALE INT1/P3.3 13 28 P2.7/A15 7/A15 INT0/P3.2 13 30 PSEN T0/P3.4 14 27 P2.6/A14 6/A14 INT1/P3.3 14 29 P2.7/A15 7/A15 TxD/P3.1 12 T1/P3.5 15 26 P2.5/A13 5/A13 T0/P3.4 15 25 P2.4/A12 4/A12 T1/P3.5 16 27 P2.5/A13 5/A13 RD/P3.7 17 24 P2.3/A11 3/A11 WR/P3.6 17 23 P2.2/A10 2/A10 RD/P3.7 18 25 P2.3/A11 3/A11 XTAL1 19 22 P2.1/A9 XTAL2 19 24 P2.2/A10 2/A10 VSS 20 21 P2.0/A8 XTAL1 20 23 P2.1/A9 VSS 21 22 P2.0/A8 QUAD FLAT PACK 26 P2.4/A12 4/A12 XTAL2 18 33 28 P2.6/A14 6/A14 WR/P3.6 16 1 * DO NOT CONNECT 1995 Feb 02 2 11 23 12 22 Philips Semiconductors Product specification CMOS single-chip 8-bit microcontrollers CERAMIC AND PLASTIC LEADED CHIP CARRIER PIN FUNCTIONS 6 1 PLASTIC QUAD FLAT PACK PIN FUNCTIONS 44 40 7 39 33 PQFP 17 Pin 11 29 23 28 Function 34 1 PLCC 18 80C528/83C528 80C528/83C528 Pin 12 Function Pin 22 Pin Function 1 NC* 23 NC* 1 Function P1.5 23 P2.5/A13 5/A13 2 P1.0/T2 24 P2.0/A8 2 P1.6/SCL 24 P2.6/A14 6/A14 3 P1.1/T2EX 25 P2.1/A9 3 P1.7/SDA 25 P2.7/A15 7/A15 4 P1.2 26 P2.2/A10 2/A10 4 RST 26 PSEN 5 P1.3 27 P2.3/A11 3/A11 5 P3.0/RxD 27 ALE 6 P1.4 28 P2.4/A12 4/A12 6 NC* 28 NC* 7 P1.5 29 P2.5/A13 5/A13 7 P3.1/TxD 29 EA 8 P1.6/SCL 30 P2.6/A14 6/A14 8 P3.2/INT0 30 P0.7/AD7 9 9 P1.7/SDA 31 P2.7/A15 7/A15 P3.3/INT1 31 P0.6/AD6 10 RST 32 PSEN 10 P3.4/T0 32 P0.5/AD5 11 P3.0/RxD 33 ALE 11 P3.5/T1 33 P0.4/AD4 12 NC* 34 NC* 12 P3.6/WR 34 P0.3/AD3 13 P3.1/TxD 35 EA 13 P3.7RD 35 P0.2/AD2 14 P3.2/INT0 36 P0.7/AD7 14 XTAL2 36 P0.1/AD1 15 P3.3/INT1 37 P0.6/AD6 15 XTAL1 37 P0.0/AD0 16 P3.4/T0 38 P0.5/AD5 16 VSS 38 VDD 17 P3.5/T1 39 P0.4/AD4 17 NC* 39 NC* 18 P3.6/WR 40 P0.3/AD3 18 P2.0/A8 40 P1.0/T2 19 P3.7/RD 41 P0.2/AD2 19 P2.1/A9 41 P1.1/T2EX 20 XTAL2 42 P0.1/AD1 20 P2.2/A10 2/A10 42 P1.2 21 XTAL1 43 P0.0/AD0 21 P2.3/A11 3/A11 43 P1.3 22 VSS 44 VDD 22 P2.4/A12 4/A12 44 P1.4 * DO NOT CONNECT * DO NOT CONNECT LOGIC SYMBOL VDD VSS PORT 0 XTAL1 ADDRESS AND DATA BUS XTAL2 RST EA 1995 Feb 02 SCL SDA RxD TxD INT0 INT1 T0 T1 WR RD PORT 2 ALE PORT 3 SECONDARY FUNCTIONS PSEN PORT 1 T2 T2EX ADDRESS BUS 3 Philips Semiconductors Product specification CMOS single-chip 8-bit microcontrollers 80C528/83C528 80C528/83C528 ORDERING INFORMATION PHILIPS PART ORDER NUMBER PART MARKING PHILIPS NORTH AMERICA PART ORDER NUMBER ROMless ROM ROMless ROM Drawing Number TEMPERATURE oC RANGE AND PACKAGE FREQ MHz P80C528FBP P80C528FBP P83C528FBP/xxx P80C528FBP P80C528FBP N P83C528FBP P83C528FBP N SOT129-1 0 to +70, Plastic Dual In-line Package 16 P80C528FBA P80C528FBA P83C528FBA/xxx P80C528FBA P80C528FBA A P83C528FBA P83C528FBA A SOT187-2 0 to +70, Plastic Leaded Chip Carrier 16 P80C528FBB P80C528FBB P83C528FBB/xxx P80C528FBB P80C528FBB B P83C528FBB P83C528FBB B SOT307-2 0 to +70, Plastic Quad Flat Pack 16 P80C528FFP P80C528FFP P83C528FFP/xxx P80C528FFP P80C528FFP N P83C528FFP P83C528FFP N SOT129-1 ­40 to +85, Plastic Dual In-line Package 16 P80C528FFA P80C528FFA P83C528FFA/xxx P80C528FFA P80C528FFA A P83C528FFA P83C528FFA A SOT187-2 ­40 to +85, Plastic Leaded Chip Carrier 16 P80C528FFB P80C528FFB P83C528FFB/xxx P80C528FFB P80C528FFB B P83C528FFB P83C528FFB B SOT307-2 ­40 to +85, Plastic Quad Flat Pack 16 P80C528FHP P80C528FHP P83C528FHP/xxx P80C528FHP P80C528FHP N P83C528FHP P83C528FHP N SOT129-1 ­40 to +125, Plastic Dual In-line Package 16 P80C528FHA P80C528FHA P83C528FHA/xxx P80C528FHA P80C528FHA A P83C528FHA P83C528FHA A SOT187-2 ­40 to +125, Plastic Leaded Chip Carrier 16 P80C528FHB P80C528FHB P83C528FHB/xxx P80C528FHB P80C528FHB B P83C528FHB P83C528FHB B SOT307-2 ­40 to +125, Plastic Quad Flat Pack 16 SOT270-1 0 to +70, Plastic Shrink Dual In-Linr Package 16 P83C528FBR/xxx NOTE: 1. xxx denotes the ROM code number. 1995 Feb 02 4 Philips Semiconductors Product specification CMOS single-chip 8-bit microcontrollers 80C528/83C528 80C528/83C528 TEMPERATURE oC RANGE AND PACKAGE FREQ MHz SOT129-1 0 to +70, Plastic Dual In-line Package 16 P87C528EBF P87C528EBF FA 0590B 0590B 0 to +70, Ceramic Dual In-line Package w/Window 16 P87C528EBA P87C528EBA AA SOT187-2 0 to +70, Plastic Leaded Chip Carrier 16 P87C528EBL P87C528EBL KA 1472A 0 to +70, Ceramic Leaded Chip Carrier w/Window 16 P87C528EBB P87C528EBB B SOT307-2 0 to +70, Plastic Quad Flat Pack 16 P87C528EFP P87C528EFP N SOT129-1 ­40 to +85, Plastic Dual In-line Package 16 P87C528EFF P87C528EFF FA 0590B 0590B ­40 to +85, Ceramic Dual In-line Package w/Window 16 P87C528EFF P87C528EFF FA SOT187-2 ­40 to +85, Plastic Leaded Chip Carrier 16 P87C528EFL P87C528EFL KA 1472A ­40 to +85, Ceramic Leaded Chip Carrier w/Window 16 P87C528EFB P87C528EFB B SOT307-2 ­40 to +85, Plastic Quad Flat Pack 16 P87C528GBP P87C528GBP N SOT129-1 0 to +70, Plastic Dual In-line Package 20 P87C528GBF P87C528GBF FA 0590B 0590B 0 to +70, Ceramic Dual In-line Package w/Window 20 P87C528GBA P87C528GBA A SOT187-2 0 to +70, Plastic Leaded Chip Carrier 20 P87C528GBL P87C528GBL KA 1472A 0 to +70, Ceramic Leaded Chip Carrier w/Window 20 P87C528GFP P87C528GFP N SOT129-1 ­40 to +85, Plastic Dual In-line Package 20 P87C528GFF P87C528GFF FA 0590B 0590B ­40 to +85, Ceramic Dual In-line Package w/Window 20 P87C528GFA P87C528GFA A SOT187-2 ­40 to +85, Plastic Leaded Chip Carrier 20 1472A ­40 to +85, Ceramic Leaded Chip Carrier w/Window 20 EPROM P87C528EBP P87C528EBP N P87C528GFL P87C528GFL KA 1995 Feb 02 Drawing Number 5 Philips Semiconductors Product specification CMOS single-chip 8-bit microcontrollers 80C528/83C528 80C528/83C528 BLOCK DIAGRAM FREQUENCY REFERENCE COUNTERS T0 XTAL2 XTAL1 RAM OSCILLATOR AND TIMING PROGRAM MEMORY (32K x 8 ROM) DATA MEMORY (256 x 8) T1 T2 T2EX AUX­RAM DATA MEMORY (256 x 8) TWO 16-BIT 16-BIT TIMER/EVENT COUNTERS 16-BIT 16-BIT TIMER / EVENT COUNTER CPU INTERNAL INTERRUPTS INT0 INT1 EXTERNAL INTERRUPTS 1995 Feb 02 64K-BYTE 64K-BYTE BUS EXPANSION CONTROL CONTROL RST PROGRAMMABLE SERIAL PORT FULL DUPLEX UART SYNCHRONOUS SHIFT PROGRAMMABLE I/O SERIAL IN PARALLEL PORTS, ADDRESS/DATA BUS AND I/O PINS SERIAL OUT SHARED WITH PORT 3 6 BIT-LEVEL I2C INTERFACE SDA SCL WATCHDOG TIMER Philips Semiconductors Product specification CMOS single-chip 8-bit microcontrollers 80C528/83C528 80C528/83C528 PIN DESCRIPTION PIN NO. MNEMONIC DIP SDIL LCC QFP TYPE VSS VDD 20 40 21 42 22 44 16 38 I I 39­32 41­34 43­36 37­30 I/O Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. In this application, it uses strong internal pull-ups when emitting 1s. 1­8 1­8 2­9 40­44 1­3 I/O 1 2 7 8 1 2 7 8 2 3 8 9 40 41 2 3 I I I/O I/O Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups, except P1.6 and P1.7 which have open drain. Port 1 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 1 pins that are externally pulled low will source current because of the internal pull-ups. (See DC Electrical Characteristics: IIL). Port 1 can sink/source one TTL (4 LSTTL) inputs. T2 (P1.0): Timer/counter 2 external count input (following edge triggered). T2EX (P1.1): Timer/counter 2 trigger input. SCL (P1.6): I2C serial port clock line. SDA (P1.7): I2C serial port data line. P2.0­P2.7 21­28 22­29 24­31 18­25 I/O Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 2 pins that are externally being pulled low will source current because of the internal pull-ups. (See DC Electrical Characteristics: IIL). Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application, it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOV @Ri), port 2 emits the contents of the P2 special function register. P3.0­P3.7 10­17 10­18 11, 13­19 5, 7­13 I/O (11=NC) 10 11 12 13 14 15 16 17 10 12 13 14 15 16 17 18 11 13 14 15 16 17 18 19 5 7 8 9 10 11 12 13 I O I I I I O O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 3 pins that are externally being pulled low will source current because of the pull-ups. (See DC Electrical Characteristics: IIL). Port 3 also serves the special features of the SC80C51 SC80C51 family, as listed below: RxD (P3.0): Serial input port TxD (P3.1): Serial output port INT0 (P3.2): External interrupt INT1 (P3.3): External interrupt T0 (P3.4): Timer 0 external input T1 (P3.5): Timer 1 external input WR (P3.6): External data memory write strobe RD (P3.7): External data memory read strobe RST 9 9 10 4 I/O Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device. An internal diffused resistor to VSS permits a power-on reset using only an external capacitor to VDD. After a watchdog timer overflow, this pin is pulled high while the internal reset signal is active. ALE 30 31 33 27 I/O Address Latch Enable: Output pulse for latching the low byte of the address during an access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency, and can be used for external timing or clocking. Note that one ALE pulse is skipped during each access to external data memory. PSEN 29 30 32 26 O Program Store Enable: The read strobe to external program memory. When the device is executing code from the external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. PSEN is not activated during fetches from internal program memory. EA 31 33 35 29 I External Access Enable: EA must be externally held low during RESET to enable the device to fetch code from external program memory locations 0000H 0000H to 7FFFH. If EA is held high during RESET, the device executes from internal program memory unless the program counter contains an address greater than 7FFFH. EA is don't care after RESET. XTAL1 19 20 21 15 I Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits. XTAL2 18 19 20 14 O Crystal 2: Output from the inverting oscillator amplifier. P0.0­0.7 P1.0­P1.7 1995 Feb 02 NAME AND FUNCTION Ground: circuit ground potential. Power Supply: +5V power supply pin during normal operation, Idle mode and Power-down mode. 7 Philips Semiconductors Product specification CMOS single-chip 8-bit microcontrollers Table 1. SYMBOL 80C528/83C528 80C528/83C528 8XC524/8XC528 8XC524/8XC528 Special Function Registers DESCRIPTION DIRECT ADDRESS BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION MSB LSB RESET VALUE ACC* Accumulator E0H E7 E6 E5 E4 E3 E2 E1 E0 00H B* B register F0H F7 F6 F5 F4 F3 F2 F1 F0 00H DPTR: DPH DPL Data pointer (2 bytes): Data pointer high Data pointer low 83H 82H IE*# Interrupt enable A8H 00H 00H AF AE AD AC AB AA A9 A8 EA ES1 ET2 ES0 ET1 EX1 ET0 EX0 BF BE BD BC BB BA B9 B8 PS1 PT2 PS0 PT1 PX1 PT0 PX0 IP*# Interrupt priority B8H ­ 87 86 85 84 83 82 81 80 P0* Port 0 80H AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 97 96 95 94 93 92 91 90 P1* Port 1 90H SDA SEL ­ ­ ­ ­ T2EX T2 A7 A6 A5 A4 A3 A2 A1 A0 A14 A13 A12 A11 A10 A9 A8 00H x0000000B FFH FFH P2* Port 2 A0H A15 FFH B7 B6 B5 B4 B3 B2 B1 B0 P3* Port 3 B0H RD WR T1 T0 INT1 INT0 TxD RxD FFH PCON Power control 87H SMOD ­ ­ ­ GF1 GF0 PD IDL 0xxx0000B D7 D6 D5 D4 D3 D2 D1 D0 PSW* Program status word D0H CY AC F0 RS1 RS0 OV F1 P RCAP2H# RCAP2L# SBUF Capture high Capture low Serial data buffer CBH CAH 99H SCON* Serial controller 98H S1BIT# I2C D9H/RD SDI 0 0 0 0 0 WR SD0 X X X X X DAH INT X X X X X DF DE DD DC DB 00H 00H 00H xxxxxxxxB 9F S1INT# S1SCS*# Serial data Serial I2C interrupt Serial I2C control 9E 9D 9C 9B 9A 99 98 SM0 SM1 SM2 REN TB8 RB8 TI RI 00H 0 0 x0000000B X X 0xxxxxxxB X X 0xxxxxxxB DA D9 D8 Timer control CLH BB RBF WBF STR ENS xxxx0000B SC0 CLH X X X STR ENS 00xxxx00B 8E 8D 8C 8B 8A 89 88 TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 CF TCON* SCI SD0 8F Stack pointer SDI WR SP D8H/RD CE CD CC CB CA C9 C8 TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL2 81H 88H T2CON*# Timer 2 control C8H TH0 TH1 TH2# TL0 TL1 TL2# T3# Timer high 0 Timer high 1 Timer high 2 Timer low 0 Timer low 1 Timer low 2 Watchdog timer 8CH 8DH CDH 8AH 8BH CCH FFH TMOD Timer mode 89H WDCON# Watchdog control 07H A5H 00H 00H 00H 00H 00H 00H 00H 00H GATE C/T M1 M0 GATE C/T M1 M0 00H A5H * SFRs are bit addressable. # SFRs are modified from or added to the 80C51 80C51 SFRs. 1995 Feb 02 00H 8 Philips Semiconductors Product specification CMOS single-chip 8-bit microcontrollers Table 2. 80C528/83C528 80C528/83C528 Internal and External Program Memory Access with Security Bit Set ACCESS TO INTERNAL PROGRAM MEMORY ACCESS TO EXTERNAL PROGRAM MEMORY MOVC in internal program memory YES YES MOVC in external program memory NO YES INSTRUCTION ROM CODE PROTECTION TIMER 2 By setting a mask programmable security bit, the ROM content in the 83C528 83C528 is protected, i.e., it cannot be read out by any test mode or by any instruction in the external program memory space. The MOVC instructions are the only ones which have access to program code in the internal or external program memory. The EA input is latched during RESET and is `don't care' after RESET (also if security bit is not set). This implementation prevents reading from internal program code by switching from external program memory to internal program memory during MOVC instruction or an instruction that handles immediate data. Table 2 lists the access to the internal and external program memory by the MOVC instructions when the security bit has been set to logical one. If the security bit has been set to a logical 0 there are no restrictions for the MOVC instructions. Timer 2 is functionally equal to the Timer 2 of the 8052AH 8052AH. Timer 2 is a 16-bit timer/counter. These 16 bits are formed by two special function registers TL2 and TH2. Another pair of special function register RCAP2L and RCAP2H form a 16-bit capture register or a 16-bit reload register. Like Timer 0 and 1, it can operate either as a timer or as an event counter. This is selected by bit C/T2N in the special function register T2CON. It has three operating modes: capture, autoload, and baud rate generator mode which are selected by bits in T2CON. INTERNAL DATA MEMORY The internal data memory is divided into three physically separated segments: 256 bytes of RAM, 256 bytes of AUX-RAM, and a 128 bytes special function area. These can be addressed each in a different way. ­ RAM 0 to 127 can be addressed directly and indirectly as in the 80C51 80C51. Address pointers are R0 and R1 of the selected register bank. ­ RAM 128 to 255 can only be addressed indirectly as in the 80C51 80C51. Address pointers are R0 and R1 of the selected register bank. ­ AUX-RAM 0 to 255 is indirectly addressed in the same way as external data memory with the MOVX instructions. Address pointers are R0, R1 of the selected register bank and DPTR. An access to AUX-RAM 0 to 255 will not affect ports P0, P2, P3.6 and P3.7. An access to external data memory locations higher than 255 will be performed with the MOVX DPTR instructions in the same way as in the 8051 structure, so with P0 and P2 as data/address bus and P3.6 and P3.7 as write and read timing signals. Note that these external data memory cannot be accessed with R0 and R1 as address pointer. 1995 Feb 02 WATCHDOG TIMER T3 The watchdog timer consists of an 11-bit prescaler and an 8-bit timer formed by special function register T3. The prescaler is incremented by an on-chip oscillator with a fixed frequency of 1MHz. The maximum tolerance on this frequency is ­50% and +100%. The 8-bit timer increments every 2048 cycles of the on-chip oscillator. When a timer overflow occurs, the microcontroller is reset and a reset output pulse of 16 × 2048 cycles of the on-chip oscillator is generated at pin RST. The internal RESET signal is not inhibited when the external RST pin is kept low by, for example, an external reset circuit. The RESET signal drives port 1, 2, 3 into the high state and port 0 into the high impedance state. The watchdog timer is controlled by one special function register WDCON with the direct address location A5H. WDCON can be read and written by software. A value of A5H in WDCON halts the on-chip oscillator and clears both the prescaler and timer T3. After the RESET signal, WDCON contains A5H. Every value other than A5H in WDCON enables the watchdog timer. When the watchdog timer is enabled, it runs independently of the XTAL-clock. Timer T3 can be read on the fly. Timer T3 can only be written if WDCON contains the value 5AH. A successful write operation to T3 will clear the prescaler and WDCON, leaving the watchdog enabled and preventing inadvertent changes of T3. To prevent an overflow of the watchdog timer, the user 9 program has to reload the watchdog timer within periods that are shorter than the programmed watchdog timer internal. This time interval is determined by an 8-bit value that has to be loaded in register T3 while at the same time the prescaler is cleared by hardware. Watchdog timer interval = [256 * (T3)] 2048 on * chip oscillator frequency BIT-LEVEL I2C INTERFACE This bit-level serial I/O interface supports the I2C-bus. P1.6/SCL and P1.7/SDA are the serial I/O pins. These two pins meet the I2C specification concerning the input levels and output drive capability. Consequently, these pins have an open drain output configuration. All the four modes of the I2C-bus are supported: ­ master transmitter ­ master receiver ­ slave transmitter ­ slave receiver The advantages of the bit-level I2C hardware compared with a full software I2C implementation are: ­ the hardware can generate the SCL pulse ­ Testing a single bit (RBF respectively, WBF) is sufficient as a check for error free transmission. The bit-level I2C hardware operates on serial bit level and performs the following functions: ­ filtering the incoming serial data and clock signals ­ recognizing the START condition ­ generating a serial interrupt request SI after reception of a START condition and the first falling edge of the serial clock ­ recognizing the STOP condition ­ recognizing a serial clock pulse on the SCL line ­ latching a serial bit on the SDA line (SDI) ­ stretching the SCL LOW period of the serial clock to suspend the transfer of the next serial data bit Philips Semiconductors Product specification CMOS single-chip 8-bit microcontrollers ­ setting Read Bit Finished (RBF) when the SCL clock pulse has finished and Write Bit Finished (WBF) if there is no arbitration loss detected (i.e., SDA = 0 while SDO = 1) ­ setting a serial clock Low-to-High detected (CLH) flag ­ setting a Bus Busy (BB) flag on a START condition and clearing this flag on a STOP condition ­ releasing the SCL line and clearing the CLH, RBF and WBF flags to resume transfer of the next serial data bit ­ generating an automatic clock if the single bit data register S1BIT is used in master mode. The following functions must be done in software: ­ handling the I2C START interrupts ­ converting serial to parallel data when receiving ­ converting parallel to serial data when transmitting ­ comparing the received slave address with its own ­ interpreting the acknowledge information 80C528/83C528 80C528/83C528 ­ guarding the I2C status if RBF or WBF = 0. Additionally, if acting as master: ­ generating START and STOP conditions ­ handling bus arbitration ­ generating serial clock pulses if S1BIT is not used. Three SFRs control the bit-level I2C interface: S1INT, S1BIT and S1SCS. INTERRUPT SYSTEM The interrupt structure of the 8XC528 8XC528 is the same as that used in the 80C51 80C51, but includes two additional interrupt sources: one for the third timer/counter, T2, and one for the I2C interface. The interrupt enable and interrupt priority registers are IE and IP. IE: Interrupt Enable Register This register is located at address A8H. Refer to Table 3. IE SFR (A8H) 7 6 5 4 3 2 1 0 EA ES1 ET2 ES ET1 EX1 ET0 EX0 Table 3. Description of IE Bits MNEMONIC BIT FUNCTION EA IE.7 General enable/disable control: 0 = NO interrupt is enabled. 1 = ANY individually enabled interrupt will be accepted. ES1 IE.6 Enable bit-level I2C I/O interrupt ET2 IE.5 Enable Timer 2 interrupt ES IE.4 Enable Serial Port interrupt ET1 IE.3 Enable Timer 1 interrupt EX1 IE.2 Enable External interrupt 1 ET0 IE.1 Enable Timer 0 interrupt EX0 IE.0 Enable External interrupt 0 Table 4. Description of IP Bits MNEMONIC BIT FUNCTION ­ IP.7 Reserved. PS1 IP.6 Bit-level I2C interrupt priority level PT2 IP.5 Timer 2 interrupt priority level PS IP.4 Serial Port interrupt priority level PT1 IP.3 Timer 1 interrupt priority level PX1 IP.2 External Interrupt 1 priority level PT0 IP.1 Timer 0 interrupt priority level PX0 IP.0 External Interrupt 0 priority level 1995 Feb 02 10 IP: Interrupt Priority Register This register is located at address B8H. Refer to Table 4. IP SFR (B8H) 7 6 5 4 3 2 1 0 ­ PS1 PT2 PS PT1 PX1 PT0 PX0 The interrupt vector locations and the interrupt priorities are: Source Vector 0003H 0003H 002BH 002BH 0053H 0053H 000BH 000BH 0013H 0013H 001BH 001BH 0023H 0023H Priority within Level Address IE0 TF2+EXF2 SI (I2C) TF0 IE1 TF1 R1+T1 Highest Lowest Philips Semiconductors Product specification CMOS single-chip 8-bit microcontrollers OSCILLATOR CHARACTERISTICS 80C528/83C528 80C528/83C528 IDLE MODE XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier. The pins can be configured for use as an on-chip oscillator, as shown in the Logic Symbol. To drive the device from an external clock source, XTAL1 should be driven while XTAL2 is left unconnected. There are no requirements on the duty cycle of the external clock signal, because the input to the internal clock circuitry is through a divide-by-two flip-flop. However, minimum and maximum high and low times specified in the data sheet must be observed. In idle mode, the CPU puts itself to sleep while all of the on-chip peripherals stay active. The instruction to invoke the idle mode is the last instruction executed in the normal operating mode before the idle mode is activated. The CPU contents, the on-chip RAM, and all of the special function registers remain intact during this mode. The idle mode can be terminated either by any enabled interrupt (at which time the process is picked up at the interrupt service routine and continued), or by a hardware reset which starts the processor in the same manner as a power-on reset. RESET POWER-DOWN MODE A reset is accomplished by holding the RST pin high for at least two machine cycles (24 oscillator periods), while the oscillator is running. To insure a good power-up reset, the RST pin must be high long enough to allow the oscillator time to start up (normally a few milliseconds) plus two machine cycles. At power-up, the voltage on VDD and RST must come up at the same time for a proper start-up. In the power-down mode, the oscillator is stopped and the instruction to invoke power-down is the last instruction executed. The power-down mode can be terminated by a RESET in the same way as in the 80C51 80C51 or in addition by one of two external interrupts, INT0 or INT1. A termination with an external interrupt does not affect the internal data memory and does not affect the special function registers. This makes it possible to exit power-down without changing the port output levels. To terminate the power-down mode with an external interrupt INT0 or INT1 must be switched to level-sensitive and must be enabled. The external interrupt input Table 5. signal INT0 and INT1 must be kept low until the oscillator has restarted and stabilized. An instruction following the instruction that puts the device in the power-down mode will be executed. A reset generated by the watchdog timer terminates the power-down mode in the same way as an external RESET, and only the contents of the on-chip RAM are preserved. The control bits for the reduced power modes are in the special function register PCON. DESIGN CONSIDERATIONS At power-on, the voltage on VDD and RST must come up at the same time for a proper start-up. When the idle mode is terminated by a hardware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write when idle is terminated by reset, the instruction following the one that invokes idle should not be one that writes to a port pin or to external memory. Table 5 shows the state of I/O ports during low current operating modes. External Pin Status During Idle and Power-Down Modes PROGRAM MEMORY ALE PSEN PORT 0 PORT 1 PORT 2 PORT 3 Idle MODE Internal 1 1 Data Data Data Data Idle External 1 1 Float Data Address Data Power-down Internal 0 0 Data Data Data Data Power-down External 0 0 Float Data Data Data 1995 Feb 02 11 Philips Semiconductors Product specification CMOS single-chip 8-bit microcontrollers 80C528/83C528 80C528/83C528 ABSOLUTE MAXIMUM RATINGS1, 2, 3 PARAMETER RATING UNIT 0 to +70, or ­40 to +85, or ­40 to +125 °C ­65 to +150 °C ­0.5 to VDD +0.5 V Input, output current on any two pins ±10 mA Power dissipation (based on package heat transfer limitations, not device power consumption) 1.0 W Operating temperature under bias Storage temperature range Voltage on any other pin to VSS NOTES: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section of this specification is not implied. 2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima. 3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. DC ELECTRICAL CHARACTERISTICS Tamb = 0°C to +70°C (VDD = 5V ±20%), ­40°C to +85°C (VDD = 5V ±20%), or ­40°C to +125°C (VDD = 5V ±10%), VSS=0V TEST SYMBOL PARAMETER PART TYPE CONDITIONS LIMITS MIN MAX UNIT VIL Input low voltage, except EA, P1.6/SCL, P1.7/SDA 0°C to 70°C ­40°C to +85°C ­40°C to +125°C ­0.5 ­0.5 ­0.5 0.2VDD­0.1 0.2VDD­0.15 0.2VDD­0.25 V V V VIL1 Input low voltage to EA 0°C to 70°C ­40°C to +85°C ­40°C to +125°C ­0.5 ­0.5 ­0.5 0.2VDD­0.3 0.2VDD­0.35 0.2VDD­0.45 V V V VIL2 Input low voltage to P1.6/SCL, P1.7/SDA3 ­0.5 0.3VDD V VIH Input high voltage, except XTAL1, RST, P1.6/SCL, P1.7/SDA 0°C to 70°C ­40°C to +85°C ­40°C to +125°C 0.2VDD+0.9 0.2VDD+1.0 0.2VDD+1.0 VDD+0.5 VDD+0.5 VDD+0.5 V V V VIH1 Input high voltage, XTAL1, RST 0°C to 70°C ­40°C to +85°C ­40°C to +125°C 0.7VDD 0.7VDD+0.1 0.7VDD+0.1 VDD+0.5 VDD+0.5 VDD+0.5 V V V VIH2 Input high voltage, P1.6/SCL, P1.7/SDA3 6.0 V VOL Output low voltage, ports 1, 2, 3, except P1.6/SCL, P1.7/SDA1 IOL = 1.6mA4 0.45 V VOL1 Output low voltage, port 0, ALE, PSEN1 IOL = 3.2mA4 0.45 V VOL2 Output low voltage, P1.6/SCL, P1.7/SDA IOL = 3.0mA4 0.4 V VOH Output high voltage, ports 1, 2, 3 VOH1 0.7VDD VDD = 5V ±10%, IOH = ­60µA IOH = ­25µA IOH = ­10µA V V V VDD = 5V ±10%, IOH = ­800µA IOH = ­300µA IOH = ­80µA Output high voltage, Port 0 in external bus mode, ALE, PSEN, RST2 2.4 0.75VDD 75VDD 0.9VDD 2.4 0.75VDD 75VDD 0.9VDD V V V IIL Logical 0 input current, ports 1, 2, 3, except P1.6/SCL, P1.7/SDA 0°C to 70°C ­40°C to +85°C ­40°C to +125°C VIN = 0.45V ­50 ­75 ­75 µA µA µA ITL Logical 1-to-0 transition current, ports 1, 2, 3, except P1.6/SCL, P1.7/SDA 0°C to 70°C ­40°C to +85°C ­40°C to +125°C See note 5 ­650 ­750 ­750 µA µA µA 1995 Feb 02 12 Philips Semiconductors Product specification CMOS single-chip 8-bit microcontrollers 80C528/83C528 80C528/83C528 DC ELECTRICAL CHARACTERISTICS (Continued) Tamb = 0°C to +70°C (VDD = 5V ±20%), ­40°C to +85°C (VDD = 5V ±20%), or ­40°C to +125°C (VDD = 5V ±10%), VSS=0V TEST SYMBOL PARAMETER PART TYPE CONDITIONS LIMITS MIN MAX UNIT IIL1 Input leakage current, port 0, EA 0.45