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Part : KU80960CA25 Supplier : Intel Manufacturer : Rochester Electronics Stock : 969 Best Price : $54.48 Price Each : $54.48
Part : TA80960CA25 Supplier : Intel Manufacturer : Rochester Electronics Stock : 109 Best Price : $327.60 Price Each : $327.60
Part : VA80960CA16 Supplier : Intel Manufacturer : Rochester Electronics Stock : 4,634 Best Price : $156.87 Price Each : $156.87
Part : VA80960CA25 Supplier : Intel Manufacturer : Rochester Electronics Stock : 3,544 Best Price : $209.96 Price Each : $209.96
Part : A80960CA-33 Supplier : Intel Manufacturer : Bristol Electronics Stock : 10 Best Price : - Price Each : -
Part : A80960CA33 Supplier : Intel Manufacturer : Bristol Electronics Stock : 26 Best Price : - Price Each : -
Part : KU80960CA25 Supplier : Intel Manufacturer : Bristol Electronics Stock : 200 Best Price : - Price Each : -
Part : A80960CA25 Supplier : Intel Manufacturer : ComSIT Stock : 11 Best Price : - Price Each : -
Part : KU80960CA16 Supplier : Intel Manufacturer : ComSIT Stock : 25 Best Price : - Price Each : -
Part : KU80960CA16 Supplier : Intel Manufacturer : Chip One Exchange Stock : 29 Best Price : - Price Each : -
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80960CA Datasheet

Part Manufacturer Description PDF Type
80960CA-16 Intel 32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR Original
80960CA-16 Intel Processor, 32-Bit HIGH-PERFORMANCE EMBEDDED PROCESSOR Original
80960CA-25 Intel 32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR Original
80960CA-25 Intel Processor, 32-Bit HIGH-PERFORMANCE EMBEDDED PROCESSOR Original
80960CA-33 Intel 32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR Original

80960CA

Catalog Datasheet MFG & Type PDF Document Tags

VA80960CA25

Abstract: 80960CA D-Stepping KU 80960CA -25 KU 80960CA -16 SV914 SV913 SW033 SW032 D2 D2 A 80960CA-33 A 80960CA-25 A 80960CA-16 TA 80960CA-16 SV908 SV907 SV906 SW031 SW030 SW029 SW147 D2 D2 D2 , application to workaround this errata for the 80960CA. Intel will also provide switches for the development , 80960CA/CF SPECIFICATION UPDATE Release Date: June, 1997 Order Number: 272875-002 The 80960CA/CF may contain design defects or errors known as errata which may cause the 80960CA/CF to deviate
Intel
Original
i960 Cx Instruction Set Quick Reference a2610 80960CF A20A VA80960CA-25 272875 80960CA/CF
Abstract: a quick, global view of software and hardware design considerations for the 80960CA. For further , tech­ nical information and examples for designing em­ bedded systems using the 80960CA. â'" The , the low latency and high throughput interrupt service featured by the 80960CA. The interrupt latency , (Figure 3-1) refers to the resources which are available for executing code on the 80960CA. The , with on-chip peripherals. These SFRâ'™s are an architectural extension specific to the 80960CA. The -
OCR Scan
32-BIT 00000000H 000003FFH
Abstract: 80960CA-25, -16 2.5 Instruction Set Summary Table 1 summarizes the 80960CA instruction set by logical , valid output SPECIAL ENVIRONMENT 80960CA-25, -16 â  m e 1® Table 3 .80960CA Pin Descriptionâ , 80960CA-25, -16 in te i Table 4 .80960CA Pin Descriptionâ'" Processor Control Signals Name Type , 4ñ2bl?5 GlbRBfil SQb â  SPECIAL ENVIRONMENT 80960CA-25, -16 Table 4 .80960CA Pin Descriptionâ , lblBÃ" S 442 2-13 SPECIAL ENVIRONMENT 80960CA-25, -16 Table 5 .80960CA Pin Descriptionâ -
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Abstract: SPECIAL ENVIRONMENT 80960CA-25, -16 2.5 Instruction Set Summary Table 1 summarizes the 80960CA , SPECIAL ENVIRONMENT 80960CA-25, -16 irrtel Table 3 .80960CA Pin Descriptionâ'" External , ENVIRONMENT 80960CA-25, -16 Table 3 .80960CA Pin Descriptionâ'"External Bus Signals (Continued) Name , ENVIRONMENT 80960CA-25, -16 the component (i.e., pins facing down). Figure 3 shows the complete 80960CA , ENVIRONMENT 80960CA-25, -16 Table 7 .80960CA PGA Pinoutâ'"In Pin Order Pin Signal Pin Signal -
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i960 Cx Instruction Set Quick Reference

Abstract: i960 Cx Processor Instruction Set Quick Reference x 80960CA -25 SV914 SW033 D2 x 80960CA -16 SV913 SW032 D2 x 80960CA-33 SV908 SW031 D2 x 80960CA-25 SV907 SW030 D2 x 80960CA-16 SV906 SW029 D2 x 80960CA-16 SW147 x80960CA-16 1 NOTES: 1. x80960CA16,S W147 will no longer be offered , prevent this code sequence in their application to workaround this errata for the 80960CA. Intel will , document are now indicated with an "x". 80960CA/CF Processor Specification Update 5 Preface
Intel
Original
i960 Cx Processor Instruction Set Quick Reference de sw033 80960CF-40 80960C

80960CA-33

Abstract: ALI 3105 Four-Channel DMA Controller F_CX001A Figure 1. 80960CA Block Diagram 1 80960CA-33, -25, -16 2.1 , while the processor is in the ONCE mode. 4 80960CA-33, -25, -16 Table 3. 80960CA Pin , . 80960CA-33, -25, -16 Table 3. 80960CA Pin Description - External Bus Signals (Sheet 3 of 3) Type , structures from non-supervisor requests. 7 80960CA-33, -25, -16 Table 4. 80960CA Pin Description - , installed processor transparent in the board. 8 80960CA-33, -25, -16 Table 4. 80960CA Pin
Intel
Original
ALI 3105 FCX-03 CX050A

80960CA

Abstract: 0ns TITLE 50ns 100ns 150ns 200ns PCI9060 FLASH EPROM READ (80960CA), 1 WORD [PRD , 200ns PCI9060 FLASH EPROM WRITE (80960CA), 1 WORD [PWR_960.TD] (07/12/94) STATE A 3 2 , STATE 100ns 200ns 300ns PCI9060 STATIC RAM READ (80960CA), 4 WORDS, WITH WAIT STATES [SRDW , STATIC RAM READ (80960CA), 4 WORDS, NO WAIT STATES [SRD_960.TD] (07/18/94) A D D D D A , RAM WRITE (80960CA), 4 WORDS, WITH WAIT STATES [SWRW_960.TD] (07/18/94) A 1 D 1 1 D
PLX Technology
Original
PCLK1-33

va80960ca25

Abstract: va80960 SW032 D2 A 80960CA-33 SV908 SW031 D2 A 80960CA-25 SV907 SW030 D2 A 80960CA-16 SV906 SW029 D2 SW147 VA80960CA-161 TA 80960CA-16 NOTE: 1. TA80960CA16,S W147 , prevent this code sequence in their application to workaround this errata for the 80960CA. Intel will , document. It contains all identified errata published prior to this date. 80960CA/CF Processor , 80960CA 32-Bit High-Performance Embedded Processor datasheet 270727 80960CF-40, -33, -25, -16 32
Intel
Original
va80960

VA80960CA25

Abstract: VA80960CA-16 SW032 D2 A 80960CA-33 SV908 SW031 D2 A 80960CA-25 SV907 SW030 D2 A 80960CA-16 SV906 SW029 D2 SW147 VA80960CA-16* TA 80960CA-16 * TA80960CA16,S W147 will no , prevent this code sequence in their application to workaround this errata for the 80960CA. Intel will , 80960CA/CF SPECIFICATION UPDATE Release Date: July, 1996 Order Number: 272875-001 The 80960CA , 80960CA/CF's behavior to deviate from published specifications are documented in this specification
Intel
Original
Multi-Channel DMA Controller TA80960

Intel 85C508

Abstract: 85C508 interface to the 80960CA's bus. It operates in pipelined or non-pipelined modes. Internally, the 27960CX is , example illustrates 8-, 16- and 32-bit wide 27960CX interfaces to the 80960CA. The designs offer a simple , is required. With the 80960CA's maximum valid address delay of 14 ns at 33 MHz, 9 ns remains for 55 , Byte Data Burst Access No Glue Interface to 80960CA High Performance Clock to Data Out â'" Zero Wait State Data to Data Burst â'" Up to 33 MHz 80960CA Performance Asynch Microcontroller Reset Function â
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Intel 85C508 85C508 cl-001 intel PLD 111-E
Abstract: Wfwl HEW LETT m PACKARD LrJk H P E2432A Intel 80960CA/CF Preprocessor Interface For use with HP logic analyzers The HP E2432A preprocessor interface for the Intel 80960CA/CF is a mechani­ cal and electrical interface between the Intel 80960CA/CF and various HP logic analyzers for , : Intel 80960CA/CF, 40-MHz, 168-pin PGA Capabilities: â'¢The 80960CA/CF microproces­ sor can operate , can be used to measure the duration of these transactions. â'¢The 80960CA bus is configurable in 16 -
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40-MH 74FCT 5091-5665E

intel PLD

Abstract: the 80960CA's bus. It operates in pipe lined or non-pipelined modes. Internally, the 27960CX Is , to the 80960CA. The designs offer a simple "no-glue" interface. A non-buffered 27960CX system , minimum CS setup time of 7 ns (tsvCH) at 33 MHz is required. With the 80960CA's maximum valid ad; dress , Synchronous 4 Byte Data Burst Access No Glue Interface to 80960CA High Perform ance Clock to Data Out - Zero Wait State Data to Data Burst - Up to 33 MHz 80960CA Perform ance Asynch Microcontroller Reset
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OCR Scan
01G1335 G1G1333

VXXXX

Abstract: 29023 no-glue, synchronous burst interface to the 80960CA's bus. It operates in pipe lined or non-pipelined , 27960CX This example illustrates 8-, 16- and 32-bit wide 27960CX interfaces to the 80960CA. The designs , setup time of 5 ns ( t s v C H ) at 33 MHz is 290236-8 required. With the 80960CA's maximum valid , Access No Glue Interface to 80960CA High Performance Clock to Data Out - Zero Wait State Data to Data Burst - Up to 33 MHz 80960CA Performance Asynch Microcontroller Reset Function - Returns to Known
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VXXXX 29023 5204 eprom

MCC68k

Abstract: mvme167 80960SA-16 80960SB-16 80960KA-25 80960KB-25 80960CA-33 80960CF-33 Figure 4. Intel i960 CPU , 1.00 0.54 0.00 80960SA-16 80960SB-16 80960KA-25 80960KB-25 80960CA-33 80960CF-33 , .11 Intel 80960CA vs. IDT R3051E, R3052E , . 15 Table 16. Intel 80960CA Default Optimization . 16 Table 17. Intel 80960CA Maximum Optimization
Intel
Original
MCC68k mvme167 intel 1302 ROM amd 29030 80386 intel microprocessor qt960 C5-233 860TM 287TM 386TM 387TM 486TM
Abstract: Figure 1. 80960CA Block Diagram 4fl2bl7S D l b b S n 573 1-157 80960CA-33, -25, -16 2.1 , 80960CA-33, -25,-16 2.5 Instruction Set Summ ary Table 1 summarizes the 80960CA instruction set by , 80960CA-33, -25,-16 intei Table 3. 80960CA Pin Description â'" External Bus Signals Name A31:2 , 80960CA-33, -25, -16 Table 3. 80960CA Pin Description â'" External Bus Signals (Continued) Name Type , agents. â  4fl5Lil?5 OlbL.524 R3G â  80960CA-33, -25, -16 Table 3. 80960CA Pin Description -
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VA80960CA25

Abstract: i960 Cx Instruction Set Quick Reference SW032 D2 A 80960CA-33 SV908 SW031 D2 A 80960CA-25 SV907 SW030 D2 A 80960CA-16 SV906 SW029 D2 SW147 VA80960CA-161 TA 80960CA-16 NOTE: 1. TA80960CA16,S W147 , prevent this code sequence in their application to workaround this errata for the 80960CA. Intel will , identified errata published prior to this date. 80960CA/CF Processor Specification Update 1 Preface , was not previously published. Affected Documents/Related Documents Title Order # 80960CA 32
Intel
Original

Non-Pipelined Single-Cycle processor

Abstract: 80960CA Supply Voltage Parameter 80960CA-25 80960CA-16 4 50 4 50 5 50 5 50 V V fCLK2x Input Clock Frequency (2-x Mode) 80960CA-25 80960CA-16 0 0 50 32 MHz MHz fCLK1x Input Clock Frequency (1-x Mode) 80960CA-25 80960CA-16 8 8 25 16 MHz MHz TC Case , Table 11 Operating Conditions (80960CA-25 -16) Table 12 DC Characteristics Table 13 80960CA AC , 8 SPECIAL ENVIRONMENT 80960CA-25 -16 Table 3 80960CA Pin Description External Bus Signals
Intel
Original
Non-Pipelined Single-Cycle processor 270710

27960CX

Abstract: 80960CA , synchronous burst interface to the 80960CA's bus. It operates in pipelined or non-pipelined modes. Internally , -, 16- and 32-bit wide 27960CX interfaces to the 80960CA. The designs offer a simple "no-glue" interface , is required. With the 80960CA's maximum valid address delay of 14 ns at 33 MHz, 9 ns remains for 55 V , Burst Access No Glue Interface to 80960CA High Performance Clock to Data Out â'" Zero Wait State Data to Data Burst â'" Up to 33 MHz 80960CA Performance Asynch Microcontroller Reset Function â'" Returns to
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N27960CX 3A353

NRED 61

Abstract: HT21X .80960CA Die Photo 3-167 October 1992 Order N um ber 270727-005 80960CA-33, -25, -16 32-Bit High , CONTROLLER INTERRUPT Figure 2 .80960CA Block Diagram 3-170 80960CA-33, -25, -16 2.1. T h e , : Instructions marked by (*) are 80960CA extensions to the 80960 instruction set. 3-172 80960CA-33, -25 , used. Figure 3. Example Pin Description Entry 3-173 80960CA-33, -25, -16 Table 2 .80960CA Pin , . The NXda wail states cannot be extended. 3-174 80960CA-33, -25, -16 Table 2 .80960CA Pin
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NRED 61 HT21X

270710

Abstract: CX041A ( ) R( - ) 4 80960CA-33, -25, -16 Table 3. 80960CA Pin Description - External Bus Signals , effectively make an installed processor transparent in the board. 80960CA-33, -25, -16 Table 4. 80960CA , . 10 80960CA-33, -25, -16 3.3 3.3.1 80960CA Mechanical Data 80960CA PGA Pinout Tables 6 , Up) 14 80960CA-33, -25, -16 3.3.2 80960CA PQFP Pinout See Section 4.0, ELECTRICAL , ^ 80960CA-33, -25, -16 32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR * Two Instructions/Clock
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CX041A 8Q96QCA-33

29023

Abstract: Synchronous 4 Byte Data Burst Access No Glue Interface to 80960CA High Performance Clock to Data Out Time - Zero Wait State Data to Data Burst - Up to 33 MHz 80960CA Performance Asynch Microcontroller Reset , 80960CA - Next Addressing Overlaps Last Data Byte CHMOS-IIIE for High Performance and Low Power - 125 mA , to 4 Mbit (512K x 8). The synchronous 4 byte burst access provides a no glue interface to the 80960CA , overlap the previous data, further optimizing bus bandwidth in 80960CA applications. The internal state
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29023

Abstract: access. The 27960CX provides a no glue synchronous burst interface to the 80960CA bus. Internally the , bandwidth in 80960CA applications. An asynchronous m icrocontroller RESET feature puts the outputs in the , Architecture The 27960CX provides a no-glue, synchronous burst interface to the 80960CA's bus. It operates in , width in 80960CA appli cations. In the pipelined mode, with a non-buffered interface, the 27960CX , read bandwidth of 88 Mbytes/ sec. Performance capability of the 27960CX in dif ferent 80960CA systems
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