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8086 interfacing with 8254 peripheral

Catalog Datasheet MFG & Type PDF Document Tags

interfacing of 8237 with 8086

Abstract: interfacing of 8237 with 8085 . A Model 30 compatible system board may be implemented with the GC100, 8086, and 12 other devices , Controller, 8254 Interval Timer, 8255 Peripheral Interface, 8288 Bus Controller, 8259 Interrupt Controller , ¤ â'¢â'¢ 53-05" GC100 Functional Description The GC100 operates as a peripheral on the 8088, or the 8086 , an INTEL 8086, When low, the GC100 is con-figured to operate with an INTEL 8088. NMI 30/34 o , DMA, timers, peripheral interface, Interrupt controller, bus controller and support circuitry. â
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interfacing of 8237 with 8086 interfacing of 8237 with 8085 8255 Programmable Interrupt Controller 8255 interfacing with 8086 A5E224M interfacing of 8253 devices with 8085 377747S T-5Z-33-05 E5530 000DDL

USART 6402

Abstract: advantages of master slave jk flip flop power saving or interfacing with 2V and 3.3V systems. 5V tolerant input and output cells are also , 8042 8048 8051 8052 8086 Z80 Standard Microprocessor Peripheral Cores â  â  â  â , capability with a very high density architecture on a 0.35nm process. The broad cell library includes a , delay for 2-input NAND with two loads (3.3V) BENEFITS â  Low power, 0.06nW /M Hz/gate at 2V , gates and tracks with sign o ff quality CAE design libraries for QuickSim II, Verilog XL and VITAL
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USART 6402 advantages of master slave jk flip flop GSC200 82077SL IEEE1284 82365SL 79C90

2-bit half adder

Abstract: microprocessors architecture of 8251 3.3V I/O capability can be used for power saving or interfacing with 2V and 3.3V systems. 5V tolerant , Standard Microprocessor Peripheral Cores · · · · · · · · 82C206 8237A 8253 8254 6845 146818 , product combining low power, mixed voltage capability with a very high density architecture on a 0.35µm , gates 97ps gate delay for 2-input NAND with two loads (3.3V) Low power, 0.06µW/MHz/gate at 2V supply , Full set of I/O cells for direct pad synthesis Accurate delay modelling for gates and tracks with sign
Zarlink Semiconductor
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2-bit half adder microprocessors architecture of 8251 USART 8251 interfacing with 8051 microcontroller microprocessors interface 8086 to 8251 USART 8251 interfacing DS4830 85C30

8251 usart architecture and interfacing

Abstract: microprocessors interface 8086 to 8251 interfacing with 2V and 3.3V systems. 5V tolerant input and output cells are also available to offer the , Standard Microprocessor Peripheral Cores · · · · · · · · 82C206 8237A 8253 8254 6845 146818 8259A 8255 , combining low power, mixed voltage capability with a very high density architecture on a 0.35µm process. The , gate delay for 2-input NAND with two loads (3.3V) Low power, 0.06µ W/MHz/gate at 2V supply (NAND , I/O cells for direct pad synthesis Accurate delay modelling for gates and tracks with sign off
Zarlink Semiconductor
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8251 usart architecture and interfacing

79C90

Abstract: interfacing with 2V and 3.3V systems. 5V tolerant input and output cells are also available to offer the , Cores 8042 8048 8051 8052 8086 Z80 Standard M icroprocessor Peripheral Cores â  â  â , cell product combining low power, mixed voltage capability with a very high density architecture on a , -input NAND with two loads (3.3V) BENEFITS â  Low power, 0.06|xW/MHz/gate at 2V supply (NAND , "¢ megacell libraries â  Accurate delay modelling for gates and tracks with sign o ff quality CAE
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microprocessors architecture of 8251

Abstract: USART 8251 interfacing with 8051 microcontroller saving or interfacing with 2V and 3.3V systems. 5V tolerant input and output cells are also available , Microprocessor Cores s s 8042 8048 s 8051 s 8052 s 8086 s Z80 Standard Microprocessor Peripheral , combining low power, mixed voltage capability with a very high density architecture on a 0.35µm process , 97ps gate delay for 2-input NAND with two loads (3.3V) Low power, 0.06µW/MHz/gate at 2V supply (NAND , of I/O cells for direct pad synthesis Accurate delay modelling for gates and tracks with sign off
Mitel Semiconductor
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Peripheral interface 8255 8251 uart vhdl 8255 interface with 8086 Peripheral ISO 8253-3 UART 8251 USART 8251

2-bit half adder

Abstract: USART 8251 interfacing with 8051 microcontroller 3.3V I/O capability can be used for power saving or interfacing with 2V and 3.3V systems. 5V tolerant , Standard Microprocessor Peripheral Cores · · · · · · · · 82C206 8237A 8253 8254 6845 146818 , product combining low power, mixed voltage capability with a very high density architecture on a 0.35µm , gates 97ps gate delay for 2-input NAND with two loads (3.3V) Low power, 0.06µW/MHz/gate at 2V supply , Full set of I/O cells for direct pad synthesis Accurate delay modelling for gates and tracks with sign
Zarlink Semiconductor
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6402 uart vhdl source code for 8086 microprocessor 8253 usart programming DAC 8048 microprocessors architecture of 8253 82530

8086 interfacing with 8254 peripheral

Abstract: 8086 microprocessor pin description with the Intel 8254 programmable interval timer and contains three identical timers (CH0 ­ CH2) CH0 and , interface and is therefore capable of directly interfacing to many ISA peripheral control devices The , ACKnowledge Used in closed-loop handshake with AFD to transfer data to the host Peripheral device drive , September 1995 NS486 TM SXF Optimized 32-Bit 486-Class Controller with On-Chip Peripherals for , peripheral I O controllers tailored for embedded control systems It is ideally suited for a wide variety of
National Semiconductor
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8086 interfacing with 8254 peripheral 8086 microprocessor pin description interfacing of lcd with 8086 graphic lcd module 320x240 intel 8086 instruction set interfacing of memory devices with 8086 486-C NS486SXF 486TM

NS486 SXF

Abstract: PAGE 27 National Semiconductor CAT 84 NS486SXL programmable interval timer is compatible with the Intel 8254 programmable interval timer and , therefore capable of directly interfacing to many ISA peripheral control devices. The interface is , -Ciass Controller with On-Chip Peripherals for Embedded Systems General Description The NS486SXL is a highly integrated embedded system controller incorporating an Intel486â"¢-class 32-bit processor along with all of , the second member of the NS486 family. Features â  100% compatible with VxWorksâ"¢, VRTXâ"¢, QNXâ
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NS486 SXF PAGE 27 National Semiconductor CAT 84 pic timing diagram pic 8086 PAGE 29 National Semiconductor CAT 84 intel 8259A

cs1674

Abstract: NS486SXL programmable interval timer is compatible with the Intel 8254 programmable interval timer and contains three , December 1997 NS486TMSXL Optimized 32-Bit 486-Class Controller with On-Chip Peripherals for , incorporating an Intel486TM-class 32-bit processor along with all of the necessary System Service Elements , 100% compatible with VxWorksTM, VRTXTM, QNXTM Neutrino, pSOS + ® , and other popular real-time executives and operating system kernels n Intel486 instruction set compatible (protected mode only) with
National Semiconductor
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cs1674 IrDA Infra Red Integrated Circuits ETS-910 interface 8254 with 8086 timer 8254 circuit MC146818RTC 486TM-

interfacing lcd with 8086

Abstract: interfacing of lcd with 8086 interface and is therefore capable of directly interfacing to many ISA peripheral control devices The , handshake with AFD to transfer data to the host Peripheral device drive Active low Peripheral Error Asserted , NS486SXF Optimized 32-Bit 486-Class Controller with On-Chip Peripherals for Embedded Systems ADVANCE INFORMATION February 1997 NS486 TM SXF Optimized 32-Bit 486-Class Controller with On-Chip , and a set of peripheral I O controllers tailored for embedded control systems It is ideally suited for
National Semiconductor
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interfacing lcd with 8086 Circuit Diagram of Microtek 14 Monochrome NS486SXF-25

25-megabyte

Abstract: interfacing 8259 with 8086 NS486SXF programmable interval timer is compatible with the Intel 8254 programmable interval timer and , February 1997 NS486 TM SXF Optimized 32-Bit 486-Class Controller with On-Chip Peripherals for , peripheral I O controllers tailored for embedded control systems It is ideally suited for a wide variety of , Y Y Y Y 100% compatible with VxWorks VRTX QNX Neutrino pSOS a TM and other popular real-time executives and operating system kernels Intel486 instruction set compatible (protected mode only) with
National Semiconductor
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25-megabyte interfacing 8259 with 8086 480x320 C1996 DS1287 IEEE-1284
Abstract: communication systems With its powerful embedded â'˜486-class processor comprehensive set of onchip peripheral , Timer The NS486SXF programmable interval timer is compatible with the Intel 8254 programmable interval , closed-loop handshake with AFD to transfer data to the host Peripheral device drive Active low PE 96 , NS486SXF NS486(TM)SXF Optimized 32-Bit 486-Class Controller with On-Chip Peripherals for , -Class Controller with On-Chip Peripherals for Embedded Systems General Description The NS486SXF is a highly Texas Instruments
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SNOS774A
Abstract: timer is compatible with the Intel 8254 programmable interval timer and contains three identical timers , ISA-compatible interface and is therefore capable of directly interfacing to many ISA peripheral control devices , handshake with AFD to transfer data to the host Peripheral device drive Active low Peripheral Error Asserted , NS486SXF NS486(TM)SXF Optimized 32-Bit 486-Class Controller with On-Chip Peripherals for Embedded Systems Literature Number: SNOS774A NS486SXF Optimized 32-Bit 486-Class Controller with Texas Instruments
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NEC 71055

Abstract: bat 102H transistor ADVANCED CHIP SET SETUP CI2 PERIPHERAL SETUP AUTO CONFIGURATION WITH DEFAULTS CHANGE PASSWORD AUTO , covers PCBs with the following Revision N° A All rights reserved. No part of this publication may be , . 7 STACKING AND EMBEDDING THE APEX SYSTEM . 8 USING THE APEX WITH A , PERIPHERAL SETUP .16 , 30 Using the Peripheral Setup
Blue Chip Technology
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NEC 71055 bat 102H transistor keyboard interfacing with 8255 microprocessors AMIBIOS HIFLEX SETUP UTILITY VERSION 1.3 interfacing keyboard matrix with 8255 CX486SLC H8FE-1004-AS

7 segment display using 8086

Abstract: intel 82230 , the 8086 is equipped with a strap pin (MN/MX) which defines the system con­ figuration. The , with the MULTIBUS® ar, chitecture. When the MN/MX pin is strapped to Vcc. the 8086 generates bus , System Timing 2-9 8086 Status bits S3 through S7 are multiplexed with highorder address bits and , order, or include company purchase order with this form ($100 minimum). We also accept VISA, MasterCard , creations, along with the applications and products created by Intel customers. Intel C orp o ra tion m
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7 segment display using 8086 intel 82230 80C88A 80287XL 02760-M 2-71979T8

Intel 486 SL Microprocessor SuperSet System Design

Abstract: 240486 .4-3 4.1.3 Interfacing with 8-, 16-, and 32-Bit Memories , on request. Information in this document is provided in connection with Intel products. No , .4-35 4.3.8.2 Running Invalidate Cycles Concurrently with Line Fills , .4-52 4.4.3.1 Snoop Collision with a Current Cache Line Operation , CONTENTS CHAPTER 7 PERIPHERAL SUBSYSTEM 7.1 PERIPHERAL/PROCESSOR BUS INTERFACE
Intel
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Intel 486 SL Microprocessor SuperSet System Design 240486 p24t pentium overdrive INTEL 845 MOTHERBOARD CIRCUIT diagram intel486 snoop ahead gigabyte 845 MOTHERBOARD CIRCUIT diagram

led 7 segment LDS 5161 AK

Abstract: 7-segment 4 digit LFD 5522 7.1.4 Interfacing with 8-, 16- and 32bit Memories . 5-95 7.1.5 Dynamic Bus Sizing during Cache Line , Total Pay by check; money order, or include company purchase order with this form ($100 minimum). We , . This series o f covers shows a few o f these creations, eking with the applications and products , Intelâ'™s FASTPATH are not affiliated with Kinetics, a division of Excelan, Inc. or its FASTPATH trade , customer support is extensive. It cap start with assistance during your development effort to network
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led 7 segment LDS 5161 AK 7-segment 4 digit LFD 5522 AKO 701 434 82360SL MIP 411 diagrama ako 451 692 K27970 X287751 02780-M X1773790D X52-5-561-1279 X52-73-17-5333

8251 intel microcontroller architecture

Abstract: vhdl source code for 8086 microprocessor . WWW site addresses are included with each partner's contact information. For additional details on , Peripheral component interconnect Pulse-code modulation Personal Computer Memory Card International , and Verilog HDL-to improve productivity. With the advent of 100,000-gate programmable logic devices , used in third-party EDA tools prior to MAX+PLUS II design processing, or with test vectors to check , off-device I/O pin delays for Altera devices. When a megafunction is used with other logic or megafunctions
Altera
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8251 intel microcontroller architecture 8251 usart verilog coding for asynchronous decade counter verilog code for 8254 timer verilog code for median filter verilog code for iir filter

Transistor morocco 9740

Abstract: Ablebond 8360 with short bursts of house-keeping activity while dozing or in stand-by state. - Peripheral activity , FAB PROCESS DESCRIPTION 2.1 PROCESS HIGHLIGHTS 0.35 µm transistor gate with lightly doped drain , resistors Twin retrograde well CMOS process Poly Buffer Locos isolation with 5000Å initial field oxide , reliability tests were performed on 3 different diffusion lots. Each of the diffusion lot was assembled with , x86 processor, fully compatible with standard x86 processors, and combines it with powerful chipset
STMicroelectronics
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STPCD0166BTC3 STPCD0175BTC3 388BGA Transistor morocco 9740 Ablebond 8360 con hdr hrs ablebond Q98001 SIP101 388BGA/
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