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Part : ING80386SX25 Supplier : Rochester Electronics LLC Manufacturer : Rochester Electronics Stock : - Best Price : - Price Each : -
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80386SX Datasheet

Part Manufacturer Description PDF Type
80386SX Intel Microprocessor - Datasheet Reference Original
80386SX-16 Intel Microprocessor, 16-Bit Data Bus, 16MHz Processor, 100-QFP Original
80386SX-20 Intel Microprocessor, 16-Bit Data Bus, 20MHz Processor, 100-QFP Original
80386SX-25 Intel Microprocessor, 16-Bit Data Bus, 25MHz Processor, 100-QFP Original
80386SX-33 Intel Microprocessor, 16-Bit Data Bus, 33MHz Processor, 100-QFP Original
80386SXSA25 Intel Microprocessor, 16-Bit Data Bus, 25MHz Processor, 100-QFP Original
80386SXSA33 Intel Microprocessor, 16-Bit Data Bus, 33MHz Processor, 100-QFP Original
80386SXSA40 Intel Microprocessor, 16-Bit Data Bus, 40MHz Processor, 100-QFP Original

80386SX

Catalog Datasheet MFG & Type PDF Document Tags

80386SX-16

Abstract: microprocessor 80286 internal architecture 80386SX16. The 80C286 not only outperforms the 80386SX at similar operating frequencies, it also provides a , PERPERPERFORMANCE FORMANCE FORMANCE 80386SX 80C286 80386SX-16 INCREASE INCREASE INCREASE # CLOCK # CLOCK , 80386SX/ 80C286 80C286-16 FASTER THAN OR EQUAL TO 80386SX-16 AAA 3 4 1.33 AAD , from the 80C286 requirement of fewer clock cycles to execute the same instructions as the 80386SX. , 80386SX. There is no performance advantage gained by simply moving a system design from an 80C286 to an
Harris Semiconductor
Original
microprocessor 80286 internal architecture 80286 Microprocessor 80286 microprocessor features architecture of microprocessor 80386 HARRIS 80286 80386 microprocessor AN121 80386SX/

80286

Abstract: 80386SX-16 performance increases of 170%-250% over the 80386SX16. The 80C286 not only outperforms the 80386SX at similar , EXECUTE ON 80386SX 80386SX/ 80C286 80C286-16 FASTER THAN OR EQUAL TO 80386SX-16 AAA 3 4 , TO EXECUTE ON 80386SX 80386SX/ 80C286 80C286-16 FASTER THAN OR EQUAL TO 80386SX-16 2 , fewer clock cycles to execute the same instructions as the 80386SX. The Intersil 80C286 is available , 80386SX. There is no performance advantage gained by simply moving a system design from an 80C286 to an
Intersil
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80286 80C286-20 80C286-25 80C86 microprocessor 80286 Number of registers size microprocessor 80286 ISO9000

task switching in 80386 microprocessor

Abstract: ARCHITECTURE OF 80286 performance increases of 170%-250% over the 80386SX16. The 80C286 not only outperforms the 80386SX at similar , EXECUTION TIME (µs) 80386SX-16 TIME (µs) 80386SX-16 TIME (µs) 80386SX-16 TIME (µs) 80386SX # , 80386SX/ 80C286 80C286-16 FASTER THAN OR EQUAL TO 80386SX-16 LGDT 11 11 1.00 LIDT , EXECUTE ON 80386SX 80386SX/ 80C286 80C286-16 FASTER THAN OR EQUAL TO 80386SX-16 3 80C286 , requirement of fewer clock cycles to execute the same instructions as the 80386SX. The Intersil 80C286 is
Intersil
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task switching in 80386 microprocessor ARCHITECTURE OF 80286 task switching in 80286 microprocessor microprocessor 80286 flag register 8086 interrupt structure architecture of 80286 microprocessor

a872 TRANSISTOR equivalent

Abstract: d472 TRANSISTOR sensed at power-up. No extra logic is required to interface with the 80386SX. The variation in processor reset propagation delay is controlled to meet the strict reset timing of the 80386SX. 1.3.2 WD7710LP , and clock speed may be controlled by the keyboard processor, transparently to the 80286 or 80386SX. , or 80386SX. AO is address bit AO for the 80286, BLE# for the 80386SX. AD is controlled by SAO (AT , PERQ extend signal to the 80386SX for IRQ13 handling. Used only for the 80386SX. 35 NPRST 0
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a872 TRANSISTOR equivalent d472 TRANSISTOR transistor d472 d472 TRANSISTOR equivalent IT191 WD90C90 WD771 OIWD771 WD7710 WD7710/WD7710LP OIWD771OLP WD7710IWD7710LP

T472

Abstract: T456 AC Operat­ ing Characteristics for the 80386SX Page Mode and 80386SX CPU Mode. The parameters that , SPECIFICATIONS FOR WD7855LV A.4 80386SX PAGE MODE TIMING SYMBOL MAX 20 MHz CHARACTERISTIC MAX , TABLE A-3. 80386SX - PAGE MODE MEMORY TIMING 1/5/93 193 WD7855/LV ELECTRICAL SPECIFICATIONS FOR WD7855LV This table covers the 80386SX CPU timing. The WD7855LV parameters that differ from , 3 4 ns TABLE A-4. 80386SX CPU TIMING 194 1/5/93
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T472 T456 WD7855

80387SX

Abstract: 41256 88C286 can be used in any 80286 and 80386SX based systems. The 88C286 chip set consists of four chips , ODDOQOb 3 Wkf~z5Z'33"Oi: SOLUTIONS 80386SX MOTHER BOARD DRAM INSTALLATION v 1) SOLUTIONS 386SX MOTHERBOARD , MOTHER BOARD * JUMPER CONNECTERS FUNCTION DESCRIPTION : PIPELINE : SHORT = 80386SX RUNS PIPELINE MODE OPEN a 80386SX RUNS NONPIPELINE MODE N9CLOCK : SHORT s 80387SX RUNS SYNC. WITH 80386SX CPU SPEED OPEN s 80387SX RUNS ASYNC. WITH 80386SX CPU SPEED N9SELECT : SHORT = 80387SX CO PROCESSOR IS NOT INSTALLED OPEN =
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88C212 88C215 41256 41256 dram ibm at motherboard 80286 80286 pin configuration SYSL06IC 145M0 88C211 88C2Q6
Abstract: PROCESSOR ADDRESS BIT 1 (80386SX MODE) A20GATE 196 I SMIADS SXBHE ; SX BUS HIGH ENABLE (80386SX MODE) RDY486 I SMIACT SXBLE ; SX BUS LOW ENABLE (80386SX MODE) CLKTEST 197 I HOLDA SXM ; 80386SX OR , ) SUSP ; SXLOWEN (80386SX MODE) SXLOWEN ; SXSWPEN (80386SX MODE) SXSWPEN ; SYSTEM CLOCK SYSCLK -
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WD8110LVZZ 80486SX/DX VIEW110 CLK14 MEMCS16 IOCS16

atmel 924

Abstract: 80386SX core logic AT40281 Features · · · · · · · · · · · · One-Chip PC/AT Compatible Core Logic Controller for 80386SX Systems operating up to 33 MHz One 160-Pin Quad Flatpack, 1-Micron CMOS Technology CPU Interface and ISA Bus Control Direct Mapped Posted Write Cache Controller with Burst Cache Fill Numeric , core logic controller for 80386SX PC/AT systems operating up to 33 MHz. The chip integrates system , board design for both cache and cacheless high performance, yet low cost, 80386SX PC/AT systems. Pin
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atmel 924 80386SX core logic 160-P AT40206IPC AT40281-16 AT40281-20 AT40281-25 AT40281-33

386SX

Abstract: 80386SX CHIPS & TECHNOLOGIES INC 57E D â  CS8285 PEAKsx CHIPSet â'¢ Close-coupled design with SCATsx â'¢ 16KB/32KB Direct-Mapped and two-way set associative cache â'¢ Integrated internal tag RAM and comparators â'¢ Caches AT I/O channel memory as well as system DRAM â'¢ Interfaces to 80386sx â , /from the expansion bus at 24mA â'¢ 120 pin QFP The PEAKsx CHIPSet supports high performance 80386sx , Block Diagram LOCAL BUS k A LD15:0 80386SX LA23.0 - LD15:0 - 80387SX LD15:0 CACHE SRAM SYSTEM
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82C836 82C835 Chips and Technologies 386sx chipset Cache Controller vlsi 386sx CHIPS TECHNOLOGIES SCATsx
Abstract: AT40283 Features â'¢ One-Chip PC/AT Compatible Core Logic Controller for 80386SX Systems operating up to 33 MHz â'¢ One 160-Pln Quad Fiatpack, 1-Mlcron CMOS Technology â'¢ CPU Interface and ISA Bus Control â'¢ Numeric Co-processor Support â'¢ OS/2 Alternate Hot Reset Support â'¢ Prog rammable , integrated single-chip core logic controller for 80386SX PC/AT systems operating up to 33MHz. The chip , , 80386SX PC/AT system. AT40283 Core Logic Controller Block Diagram dlmEE Ordering Information CPU -
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AT40283-16 AT40283-20 AT40283-25 AT40283-33

386sx

Abstract: AT40283 Features · · · · · · · · · · · One-Chip PC/AT Compatible Core Logic Controller for 80386SX Systems operating up to 33 MHz One 160-Pin Quad Flatpack, 1-Micron CMOS Technology CPU Interface and ISA Bus Control Numeric Co-processor Support OS/2 Alternate Hot Reset Support Programmable Clock , for 80386SX PC/AT systems operating up to 33MHz. The chip integrates system control functions , , 80386SX PC/AT system. Pin Configuration 9-26 AT40283 AT40283 Core Logic Controller Block
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AT4Q283

laptop MOTHERBOARD Chip Level MANUAL

Abstract: VL82c311 designed to perform in 80286- and 80386SX-based systems with clock speeds of 25 MHz and below, and , to 20 MHz or in 80386SX-based systems up to 25 MHz Two 160-lead plastic quad flatpacks, 1.0 and 1.5 , use in 80286 or 80386SX microprocessor-based systems with clock speeds from 12 to 25 MHz. The TOPCAT , 80386SX microprocessor-based PC/AT system. This chip also provides the data conversion necessary for 16 , Evaluation Boards - VLTC286-SB1 - 12 to 25 MHz 80286 - VLTC386SX-DB -16/20 MHz 80386SX daughter board
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laptop MOTHERBOARD Chip Level MANUAL VL82c311 topcat ibm schematics 80286 VL82C106 80286 microprocessor schematics 286/386SX VL82C320A VL82C335

SL9251

Abstract: SL9251 80386SX Page Interleave Memory Controller ADVANCE FEATURES â'¢ Supports 80386SX based AT Designs. â'¢ Up to 25 MHz Performance. â'¢ Enhanced Fast Page Mode/Page Interleave. â , 's 80386SX microprocessor. It is a member of VIA 's FlexSet fam ily which utilizes the same core logic , the 80386SX (SL9250). Boards designed using the SL9250 can be used with the new SL9251 without , 80386SX based designs. The Page interleave option can be enabled or disabled using the configuration
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00A0000 00FFFFF GATEA20 AT/386SX

d472 TRANSISTOR

Abstract: transistor d472 automatically sensed at power up. No extra logic is required to interface with the 80386SX. The variation in processor reset propagation delay is controlled to meet the strict reset timing of the 80386SX. 1.3.2 , and clock speed may be controlled by the keyboard processor, transparently to the 80286 or 80386SX. , 80286 or 80386SX. AO is address bit AO for the 80286, BLE# for the 80386SX, and is controlled by SAO , PERQ extend signal to the 80386SX for IRQ13 handling. Used only for the 80386SX. 35 NPRST
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WD76C10A WD76C10ALP WD76C10ALV t2146 floppy disk chip Liming T78 5v i8042 WD76C1 WD76C10AILPILV A23-A1
Abstract: ­ matically sensed at power-up. No extra logic is required to interface with the 80386SX. The varia­ tion , 80386SX. 1.3.2 WD7710LP / WD7710LV The WD7710 is designed for use in a high perfor­ mance desktop , clock speed may be con­ trolled by the keyboard processor, transparently to the 80286 or 80386SX. , Non-Page Mode 01 Timing . .T - 5 2 - 3 3 - 0 5 ^7 12.1.4 80386SX Page Mode Timing . 120 12.1.5 80386SX Non-Page Mode 00 andMode 01 T im in g . 125 -
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WD7710/LP/LV T-52-33-05 D15-D0 T-52-3

386SX

Abstract: IPC SYSTEM DIAGRAM AT40283 Features â'¢ One-Chip PC/AT Compatible Core Logic Controller for 80386SX Systems operating up to 33 MHz â'¢ One 160-Pin Quad Flatpack, 1-Micron CMOS Technology â'¢ CPU Interface and ISA Bus Control â'¢ Numeric Co-processor Support â'¢ OS/2 Alternate Hot Reset Support â'¢ Programmable , for 80386SX PC/AT systems operating up to 33MHz. The chip integrates system control functions , cost, 80386SX PC/AT system. Pin Configuration AT40283 1074177 000573*} 434 This Material
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IPC SYSTEM DIAGRAM RASCO GDDS73 AT4G283 AT40206 1D74177 DG0574 AT402831
Abstract: AT40281 Features â'¢ â'¢ â'¢ â'¢ â'¢ â'¢ â'¢ â'¢ â'¢ â'¢ â'¢ â'¢ One-Chip PC/AT Compatible Core Logic Controller for 80386SX Systems operating up to 33 MHz One 160-Pin Quad Flatpack, 1-Micron CMOS Technology CPU Interface and ISA Bus Control Direct Mapped Posted Write Cache Controller with , Description The Atmel AT40281 is a highly integrated single-chip core logic controller for 80386SX PC/AT , single board design for both cache and cacheless high performance, yet low cost, 80386SX PC/AT systems -
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block diagram of bios

Abstract: bus ISA AT40283 Features · One-Chip PC/AT Compatible Core Logic Controller for 80386SX Systems operating up to 33 MHz · One 160-Pin Quad Flatpack, 1-Micron CMOS Technology · CPU Interface and ISA Bus , Integrated Peripheral Controller Peripheral Data Bus ISA Data Bus ISA Address Bus 80386SX CPU , highly integrated single-chip core logic controller for 80386SX PC/AT systems operating up to 33MHz. The , components, the AT40283 implements a high performance, yet low cost, 80386SX PC/AT system. Pin
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block diagram of bios bus ISA dram Memory Controller 25 Mhz

dd127d

Abstract: dd127d5 with the 80386SX. The variation in processor reset propagation delay is controlled to meet the strict reset timing of the 80386SX. 1.3 GENERAL DESCRIPTION The WD7910 is designed for use in a high , keyboard processor, transparently to the 80286 or 80386SX. The System Activity Monitor (SAM) provided by , .125 13.1.3 80286 Non-Page Mode 01 Timing .129 13.1.4 80386SX Page Mode Timing .132 13.1.5 80386SX Non-Page Mode 00 And Mode 01 Timing.137 13.2 AT Bus Timing
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dd127d dd127d5 wd90c30 d872 8c72 western digital 40000h WD791Q WD7910LP WD7910/WD7910LP 10CHRDY

386SX

Abstract: 80386SX AT40281 Features â'¢ One-Chip PC/AT Compatible Core Logic Controller for 80386SX Systems operating up to 33 MHz One 160-Pin Quad Flatpack, 1-Micron CMOS Technology CPU Interlace and ISA Bus Control Direct Mapped Posted Write Cache Controller with Burst Cache Fill Numeric Co-processor Support OS , 80386SX PC/AT systems operating up to 33 MHz. The chip integrates system control functions including reset , both cache and cacheless high performance, yet low cost, 80386SX PC/AT systems. Pin Configuration
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DDD5735 isa pin diagram 1D7M17 1G74177
Abstract: '" 8 Independently Programmable Channels DRAM Refresh Controller Military 80386SX Shutdown Detect , -Bit Programmable Interval Timers â'" M82C54 Compatible Optimized for Use with the Military 80386SX , that integrates system functions necessary in a Military 80386SX environment. It has eight channels of , possible on the Military 80386SX bus. System support peripherals inte­ grated into theM 82370 provide , Pin Descriptions The 82370 provides all of the signals necessary to interface an 80386SX host -
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M82370 M8259A 132-P M82380 ADDR2-31 271167-B1
Abstract: designed for theOaKHonzonchip set running with 80286 and 80386SX microprocessors. Thechip provides all the , ADDRESS 8US.' These are address bus lines corresponding to A23-A0 of the S0286/80386SX and 80287/80387SX , : These are the bidirectional data bus lines corresponding to D15-D0 of the 80286/80386SX CPU. BUS CYCLE , coming from 80386SX. This input is also used to detect the presence of a 80386SX. - BUS INTERFACE " , phase of TS. If an 80386SX is used. ALE is generated at the 1st phase of TS. ALE is active high and the -
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OTI-051 OTI-O51 S0286/80386SX 80286/80386SX SD0-SD15 0TI-Q51

intel 82370

Abstract: M82370 functions necessary in a Military 80386SX environment. It has eight channels of high performance 32-bit DMA , 80386SX bus. System support peripher als integrated into the Military 82370 provide Interrupt Control , Descriptions The 82370 provides all of the signals necessary to interface an 80386SX host processor. It has a , incremented, decremented or held constant, and cover the entire 16-bit physical address space of the 80386SX , modes, the current count can be latched and read by the 80386SX at any time, making these very versatile
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intel 82370 M8237 60386 27116 148237 271167-A8 A0DR2-31 D0-07 271167-A9

ht321

Abstract: . 132 13.1.4 80386SX Page Mode Timing 13.1.5 80386SX Non-Page Mode 00 And Mode 01 T im in g , . 80386SX - Page Mode Memory T im in g . 80386SX - , . 177 183 80386SX CPU T im in g . . . , . 131 80386SX - Page Mode, First Access Read/Write .133 80386SX - Page Mode, Page Miss Read/Write
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ht321

OT104

Abstract: OTI041 Notebook PC subsystem is a set of highly integrated, semi-custom ICs designed from 80286 and 80386SX , 160 -pin PJQFP. The OTI041 features the following functions: Supports 80286 and 80386SX processors , circuit designed for the OakNoteTM running with the 80286/80386SX microprocessor. The chip integrates all , signal coming from 80386SX. This input is also used to detect the presence of 386SX. BUS CYCLE STATUS , cycle is memory or I/O access. CPU CLOCK : ACMOS driven clock signal to the 80286/80386SX CPU. The
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OTI042 OT104 OTI-041 Oak Technology 80386 microprocessor interface keyboard 386SX notebook OTI043 OTIQ43 A0000-AFFFF

block diagram of 80386 microprocessor

Abstract: 80386 microprocessor pin out diagram (FE6500) or the 80386SX Clock, Resets, and Parity Latch Control 16,20, and 25 MHz Clock Speeds to , . 34 9.0 THE FE6010 IN 80386 AND 80386SX ENVIRONMENTS , compatible with both the 80386 and the 80386SX microprocessors. In the following description, any references to the system microprocessor refer to both the 80386 and the 80386SX, unless specifi cally stated , implementation on an 80386 system versus an 80386SX system. ARBITRATION CONTROL The Arbitration Control block in
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block diagram of 80386 microprocessor 80386 microprocessor pin out diagram microprocessor 80386 pin out diagram pvga1 80387 80386 microprocessor functional block diagram 80387/80387SX 132-L FE6022 A00RESS FE6Q10
Abstract: W D 7 6 0 0 A A N D W D 7 6 0 0 A L P CHI P SETS \ Systems Logic fo r 80386SX and 80286 PC/AT Desktop and Laptop Compatibles TI k- W estern Digital s W D 7600A /L P System s V Logic chip set- provide all the necessary logic to F E A T U R E S builil ;i highly integrated D esktop or L aptop IBM PC /A T com patible system board qsing either a 16- â'¢ Supports 80386SX or , inputs and bytes total), and an Integrated D isk E lectronics 80386SX and 80286 System A ctivity -
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WD75C10

Abstract: '¢ Interfaces with 80286 or 80386SX CPUs. 1.3 â'¢ Supports memory in four banks with 64 Kbit, 256 Kbit, 1 , , using an 80286 or 80386SX processor of up to 25 M Hz. The WD76C1 OALP has the features of the WD76C10A , 80286 or 80386SX processor. With the exception of the 80286 modes, the WD76C10ALV has all the , of EMS memory. â'¢ Maintains controlled propagation delay for 80386SX reset. â'¢ Employs an , other extended character sets. The WD76C10A interfaces with either an 80286 or 80386SX processor. The
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WD75C10 WD76C10A/LP/LV WD76C10ALP/LV WD76C1OALV WD76C1OA/LP/LV

d472 TRANSISTOR

Abstract: d472 TRANSISTOR equivalent Non-Page Mode 01 Timing 13.1.4 80386SX Page Mode Timing 13.1.5 80386SX Non-Page Mode 00 And Mode 01 , Timing 80286 - Non-page Mode 00 Memory Timing 80286 - Non-page Mode 01 Memory Timing 80386SX - Page Mode Memory Timing . . 80386SX - Non-page Mode 00 and Mode 01 Memory Timing ADVANCED INFORMATION 11 , 80386SX CPU Timing ADVANCED INFORMATION 11125/91 · · · · · · 8-142 8-154 8-159 8-164 , Non-page Mode 01,0 Wait State Read (4072H = 3560H) 80386SX - Page Mode, First Access ReadlWrite 80386SX -
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IMS T414 wd90c10 t410 TRANSISTOR K544 SPB105 IS020 WD7910IWD7910LP WD791 O/WD791
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