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8 bit 74166

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Abstract: Signetics 74166 Shift Register 8-Bit Serial/Parallel-ln, Serial-Out Shift Register Product , asynchronous parallel data load DESCRIPTION The ' 166 is an 8-bit shift register that has fully synchronous , .) 74166 TEST CONDITIONS1 Min Typ2 3.4 0.2 0.4 -1 .5 1.0 40 -1 .6 -1 8 90 -5 7 127 Max V V V mA ma UNIT , . When PE is HIGH, data is entered into internal bit position Q0 from Serial Data Input (Ds), and the , Ds input of the suc ceeding stage. TYPE 74166 TYPICAL (« A X 35MHz TYPICAL SUPPLY CURRENT ... OCR Scan
datasheet

5 pages,
155.75 Kb

TPNT 74166 pin diagram 74166 applications 74166 8 bit 74166 ttl 74166 TEXT
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Abstract: Signetics 74166 Shift Register Logic Products 8-Bit Serial/Parallel-ln, Serial-Out Shift , ) 74166 35MHz 90mA ORDERING CODE PACKAGES COMMERCIAL RANGE Vcc = SV±5%; TA = 0°C to +70°C Plastic DIP N74166N N74166N Plastic SO N74166D N74166D DESCRIPTION The '166 is an 8-bit shift register that has fully , Specification Shift Register 74166 LOGIC DIAGRAM (7) _ , register. When PE is HIGH, data is entered into internal bit position Q0 from Serial Data Input (Ds), and ... OCR Scan
datasheet

5 pages,
150.87 Kb

1N3064 1N916 74LS N74166D N74166N 74166 74166 pin diagram 74166 applications ttl 74166 8 bit 74166 TEXT
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Abstract: Signetics Logic Products 74166 Shift Register 8-Bit Serial/Parallel-ln, Serial-Out Shift , Reset • See '165 for asynchronous parallel data load DESCRIPTION The ' 166 is an 8-bit shift , 74166 LOGIC DIAGRAM ( ) -Pin number Voc - Pin 16 GND - Pin 8 MODE SELECT —FUNCTION TABLE , is entered into the register. When PE is HIGH, data Is entered into internal bit position Q0 from , SUPPLY CURRENT (TOTAL) 74166 35MHz 90mA ORDERING CODE PACKAGES COMMERCIAL RANGE VCC = 5V±5%! Ta = 0 ... OCR Scan
datasheet

5 pages,
156.83 Kb

1N3064 1N916 74166 pin diagram 74LS 8 bit 74166 MR 306 127 N74166D N74166N 74166 ttl 74166 TEXT
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Abstract: Signetics 74166 Shift Register 8-Bit Serial/Parallel-ln, Serial-Out Shift Register Product , = 0°C to +70°C N74166N N74166N N74166D N74166D DESCRIPTION T h e ' 166 is an 8 -bit shift register that has , unless otherwise noted.) 74166 TEST CONDITIONS1 Min Typ2 3.4 0.2 0.4 -1 .5 1.0 40 -1 .6 -1 8 90 -5 7 127 , '165 for asynchronous parallel data load NOTE: TYPE 74166 TYPICAL Im a x 35MHz TYPICAL SUPPLY , entered into the register. W hen PE is H IG H , data is entered into internal bit position Qo from Serial ... OCR Scan
datasheet

5 pages,
156.18 Kb

74166 shift register IC of ic 74166 IC 74166 TEXT
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Abstract: SN54166 SN54166, SN54LS166A SN54LS166A, SN74166 SN74166, SN74LS166A SN74LS166A PARALLEL LOAD 8-BIT SHIFT REGISTERS O C T O B E R 197 6 R , '1 6 6 a n d 'L S 1 6 6 A 8-bit shift registers are com pati ble w ith m o st other T T L logic , _1 1 _1 1 _1 \ 1 3 2 1 20 19 \ SN54166 SN54166, SN54LS166A SN54LS166A. SN74166 SN74166, SN74LS166A SN74LS166A PARALLEL LOAD 8 BIT SHIFT , , SN54LS166A SN54LS166A, SN74166 SN74166, SN74LS166A SN74LS166A PARALLEL LOAD 8-BIT SHIFT REGISTERS schematics of inputs and outputs E , * 2-531 TTL Devices SN54166 SN54166, SN54LS166A SN54LS166A, SN74166 SN74166, SN74LS166A SN74LS166A PARALLEL LOAD 8 BIT SHIFT REGISTERS ... OCR Scan
datasheet

7 pages,
326.88 Kb

of ic 74166 IC 74166 SN54166 SN54LS166A SN74166 SN74LS166A TEXT
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Abstract: , S fci; 7 ') TiWSJni*: ? -f"/ -133- 8-Bit Shift Register i i«a AA IN iKi] OUT N LS ALS ALSK F , 74166 PARALLEL PARALLEL INPUTS SMtFV INPUT OUTPUT m * » Vcc 10 AO M Qm G F t CLEAR jwlnruMinnSM \LiiiiijAtJiiii±fiin±r PARALLEL INPUTS A. tl m if Clear Shift/Load CK CK Inhibit H H L , «A 11 nax ALL L 1.6 0. 4 0.1 0. 04 ■A IOH max ALL H 0. 8 0.4 0.4 1 24 24 4 4 «A I OL max ALL L 16 8 8 20 24 24 4 4 ■A a«, N LS ALS ALSK F S AS AC ACT I1C HCU ... OCR Scan
datasheet

2 pages,
30.35 Kb

8 bit 74166 74165a TEXT
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Abstract: MHz 305 X X 54/74163 4-Bit Binary Counter, Sync. Clear 32 MHz 305 X X 54/74164 8-Bit Parallel-Out Serial Shift Register (S.I.P.O.) 36 MHz 167 X X 54/74165 Parallel-Load 8-Bit Shift Register (P.I.S.O.) 26 MHz 210 X X 54/74166 8-Bit Shift Register with Clear (P.I.S.0.) 35 MHz 360 X X 54 , MHs 195 X X 54/74195 4-Bit Parallel Access Shift Register 39 MHz 195 X X 54/74198 8-Bit Right/Left Shift Register (P.I.P.O.) 35 MHz 360 X X 54/74199 8-Bit Shift Register (P.I.P.O.) 35 MHz ... OCR Scan
datasheet

1 pages,
43.21 Kb

74154 demultiplexer multiplexor 74156 7483 16 bit full adder 74150 demultiplexer 74194 universal shift register 74174 shift register 74194 shift register 7483 bcd adder 74151 adder Multiplexer 74152 4 bit 7483 binary adder bcd adder with 74283 74150 multiplexer 74155 demultiplexer 7483 8 bit binary adder 7483 4 bit binary adder 74198 shift register 74153 full adder 74151 demultiplexer 7483 4 bit binary full adder TEXT
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Abstract: 166 £>(D7^Y 54/74166 8-BIT SHIFT REGISTER D E SC R IPTIO N - The '166 is an 8-bit, serial- or parallel-in, serial-out shift register using edge triggered D-type flip-flops. Serial and parallel entry are synchronous, w ith state changes initiated by the rising edge of the clock. An asynchronous Master Reset overrides other inputs and clears all flipflops. The circu it can be clocked from tw o , Serial Data (Ds) input to Qo and all data in the register is shifted one bit position (i.e., Qo-»-Qi, Q 1 ... OCR Scan
datasheet

3 pages,
142.6 Kb

74166 pin diagram of ic 74166 IC 74166 TEXT
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Abstract: /Seriahout 54/74166 8 D 8S s 35 20 360 D176 4L,7B,9B 6 Parallel-in/Serial-out 54LS/74LS165 54LS/74LS165 8 D 8A s 40 19 , 4L,6B,9B 7 Dual 4-Bit D Latch 9308 8xD 2xL 2x2 AND 15 19 12 300 D151 4M,6N,9N 8 Dual 4-Bit D Latch , 14 8-Bit D Flip-Flop(3S) 54LS(2)/74LS374 /74LS374 8xD — K-T) 10 23 23 135 D86 9Z 15 8-Bit D Latch 54LS(2)/74LS373 /74LS373 8xD — 1(H) 15 24 16 120 D85 9Z 16 8-Bit D Latch 54LS(2)/74LS573 /74LS573 8xD — 1(L) — — — — D179 9Z 17 8-Bit Addr Latch 9334 1xD L 1(L) 3 addr bits 11 18 28 280 D134 4L,7B,9B 18 8-Bit Addr ... OCR Scan
datasheet

3 pages,
113.07 Kb

MUX 74LS151 74151 mux 74LS502 fairchild 9322 74298 quad 2 in mux pin diagram of 74153 74157 D flip-flop 74175 pin 74152 mux D154 4 bit shift register 7494 pin diagram quad D flip-flop 74175 pin MUX 74151 54LS/74LS170 54LS/74LS670 mux 74153 54LS/74LS170 54LS/74LS670 CI 74151 54LS/74LS170 54LS/74LS670 74LS152 54LS/74LS170 54LS/74LS670 74174 shift register 54LS/74LS170 54LS/74LS670 74157 mux 54LS/74LS170 54LS/74LS670 MUX 74157 54LS/74LS170 54LS/74LS670 74153 mux 54LS/74LS170 54LS/74LS670 54LS/74LS170 54LS/74LS170 54LS/74LS670 54LS/74LS670 TEXT
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Abstract: /Serial-out 54/74165 8 D 8A s 26 19 210 D175 4L,7B,9B 5 Parallel-in/Seriahout 54/74166 8 D 8S s 35 20 360 , 2xL 2x2 AND 15 19 12 300 D151 4M,6N,9N 8 Dual 4-Bit D Latch 93L08 93L08 8xD 2xL 2x2 AND 30 32 32 100 D151 , 13 6-Bit D Flip-Flop 54LS/74LS174 54LS/74LS174 6 L 1 Lr) 20 21 — 80 D152 4L,6B,9B 14 8-Bit D Flip-Flop(3S) 54LS(2)/74LS374 /74LS374 8xD — K-T) 10 23 23 135 D86 9Z 15 8-Bit D Latch 54LS(2)/74LS373 /74LS373 8xD — 1(H) 15 24 16 120 D85 9Z 16 8-Bit D Latch 54LS(2)/74LS573 /74LS573 8xD — 1(L) — — — — D179 9Z 17 8-Bit Addr Latch ... OCR Scan
datasheet

3 pages,
111.81 Kb

8 bit 74166 7475 data latch 93L08 ttl 7491 D145 D147 74298 quad 2 in mux D151 74ls175 pin diagram 74LS279 D flip-flop 74175 pin 7475 d-flip flop 9374 74LS173 4 bit 3 state quad register 93L14 54LS/74LS279 74174 shift register 93L14 54LS/74LS279 7477 D latch 93L14 54LS/74LS279 latch 74ls574 93L14 54LS/74LS279 4 bit shift register 7494 pin diagram 93L14 54LS/74LS279 quad D flip-flop 74175 pin 93L14 54LS/74LS279 7475 D flip-flop 93L14 54LS/74LS279 93L14 93L14 54LS/74LS279 54LS/74LS279 TEXT
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Archived Files

Abstract Saved from Date Saved File Size Type Download
* * * - 74AC151 74AC151 - * 8-Input Multiplexers * * NS FACT Advanced CMOS Logic Data Book, 1989 * jds * * * - 74ACT151 74ACT151 - * 8-Input Multiplexers * * NS FACT Advanced CMOS Logic Data Book, 1989 * * * - 74F151 74F151 - * 8-Input Multiplexers * * Philips FAST TTL Logic Series Data Book, 1992 * * * - 74F151A 74F151A - * 8-Input Multiplexers * * Philips FAST TTL Logic Series Data Book, 1992 * * * - 74F151B 74F151B - * 1-OF-8 Data Selectors/Multiplexers * * The F Logic Data Book, 1994, TI Pages
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Spice Models 18/04/2010 337.13 Kb LIB dig150.lib
*- * 7430 8-input Positive-Nand Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/26 DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(8) DPWR DGND + A B C D E F G H Y + D_30 IO_STD *- * 7475 4-bit bistable latches (dual 2-bit common clock) * * The TTL Data Book, Vol 2, 1985, TI * 7477 4-bit bistable latches * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/28/89 Update interface : MNTYMXDLY=0 IO_LEVEL=0 * There are actually 2 2-bit latches(per 1 control) in the real IC. The model * here
/datasheets/files/spicemodels/misc/7400.lib
Spice Models 19/12/2001 282.17 Kb LIB 7400.lib
*- * 7430 8-input Positive-Nand Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/26 DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(8) DPWR DGND + A B C D E F G H Y + D_30 IO_STD *- * 7475 4-bit bistable latches (dual 2-bit common clock) * * The TTL Data Book, Vol 2, 1985, TI * 7477 4-bit bistable latches * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/28/89 Update interface : MNTYMXDLY=0 IO_LEVEL=0 * There are actually 2 2-bit latches(per 1 control) in the real IC. The model * here
/datasheets/files/spicemodels/misc/spice_model_cd/mixed part list/spice-models-collection/7400.lib
Spice Models 29/07/2012 282.15 Kb LIB 7400.lib
No abstract text available
/download/48664731-299145ZC/bae65022linux.tgz
Kaleidoscope 22/08/2005 11421.08 Kb TGZ bae65022linux.tgz