NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Catalog Datasheet Results | Type | Document Tags |
| Abstract: Signetics 74166 Shift Register Logic Products 8-Bit Serial/Parallel-ln, Serial-Out Shift , ) 74166 35MHz 90mA ORDERING CODE PACKAGES COMMERCIAL RANGE Vcc = SV±5%; TA = 0°C to +70°C Plastic DIP N74166N N74166N Plastic SO N74166D N74166D DESCRIPTION The '166 is an 8-bit shift register that has fully synchronous , 74166 LOGIC DIAGRAM (7) _ , When PE is HIGH, data is entered into internal bit position Q0 from Serial Data Input (Ds), and the ... | OCR Scan |
5 pages, |
1N3064 1N916 74166 pin diagram 74LS N74166D N74166N 74166 74166 applications ttl 74166 8 bit 74166 datasheet abstract |
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| Abstract: Signetics Logic Products 74166 Shift Register 8-Bit Serial/Parallel-ln, Serial-Out Shift , • See '165 for asynchronous parallel data load DESCRIPTION The ' 166 is an 8-bit shift register , entered into the register. When PE is HIGH, data Is entered into internal bit position Q0 from Serial Data , connected to the Ds input of the succeeding stage. TYPE TYPICAL fMAX TYPICAL SUPPLY CURRENT (TOTAL) 74166 , the register asynchronously, forcing all bit positions to a LOW state. PIN CONFIGURATION LOGIC ... | OCR Scan |
5 pages, |
N74166N N74166D MR 306 127 8 bit 74166 74LS 1N916 1N3064 74166 ttl 74166 datasheet abstract |
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| Abstract: MHz 305 X X 54/74163 4-Bit Binary Counter, Sync. Clear 32 MHz 305 X X 54/74164 8-Bit Parallel-Out Serial Shift Register (S.I.P.O.) 36 MHz 167 X X 54/74165 Parallel-Load 8-Bit Shift Register (P.I.S.O.) 26 MHz 210 X X 54/74166 8-Bit Shift Register with Clear (P.I.S.0.) 35 MHz 360 X X 54 , MHs 195 X X 54/74195 4-Bit Parallel Access Shift Register 39 MHz 195 X X 54/74198 8-Bit Right/Left Shift Register (P.I.P.O.) 35 MHz 360 X X 54/74199 8-Bit Shift Register (P.I.P.O.) 35 MHz ... | OCR Scan |
1 pages, |
7483 parallel adder 74174 shift register 7483 4-bits parallel adder 74154 demultiplexer 74151 multiplexer 7483 bcd adder multiplexor 74156 74194 shift register 74194 universal shift register Multiplexer 74152 4 bit 7483 binary adder bcd adder with 74283 datasheet abstract |
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| Abstract: /74165 8 D 8A s 26 19 210 D175 4L,7B,9B 5 Parallel-in/Seriahout 54/74166 8 D 8S s 35 20 360 D176 4L,7B , - 65 D156 4L,6B,9B 7 Dual 4-Bit D Latch 9308 8xD 2xL 2x2 AND 15 19 12 300 D151 4M,6N,9N 8 Dual , 80 D152 4L,6B,9B 14 8-Bit D Flip-Flop(3S) 54LS(2)/74LS374 /74LS374 8xD - K-T) 10 23 23 135 D86 9Z 15 8-Bit D Latch 54LS(2)/74LS373 /74LS373 8xD - 1(H) 15 24 16 120 D85 9Z 16 8-Bit D Latch 54LS(2)/74LS573 /74LS573 8xD - 1(L) - - - - D179 9Z 17 8-Bit Addr Latch 9334 1xD L 1(L) 3 addr bits 11 18 28 280 D134 4L,7B,9B 18 8-Bit Addr ... | OCR Scan |
3 pages, |
D148 D149 D150 D151 FLIP FLOP 7475 74LS175 Register 7475 TTL 7475 93L08 74ls175 pin diagram 74298 quad 2 in mux D flip-flop 74175 pin 74LS279 7475 d-flip flop 93L14 54LS/74LS279 93L14 abstract |
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| Abstract: / -133- 8-Bit Shift Register i i«a AA IN iKi] OUT N LS ALS ALSK F S AS AC ACT HC HCU HCT BC BCT «H , 74166 PARALLEL PARALLEL INPUTS SMtFV INPUT OUTPUT m * » Vcc 10 AO M Qm G F t CLEAR jwlnruMinnSM \LiiiiijAtJiiii±fiin±r PARALLEL INPUTS A. tl m if Clear Shift/Load CK CK Inhibit H H L t_T L > V h H L D - K H H X H â- t. - 'L- K' "U- L X X X ? 'I ? * CK = LOTMBSKCK Inhibits- H il+4 t f-ti'lbit->7 I- , 04 â- A IOH max ALL H 0. 8 0.4 0.4 1 24 24 4 4 «A I OL max ALL L 16 8 8 20 24 ... | OCR Scan |
1 pages, |
8 bit 74166 74165a datasheet abstract |
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| Abstract: /Seriahout 54/74166 8 D 8S s 35 20 360 D176 4L,7B,9B 6 Parallel-in/Serial-out 54LS/74LS165 54LS/74LS165 8 D 8A s 40 19 , 19 12 300 D151 4M,6N,9N 8 Dual 4-Bit D Latch 93L08 93L08 8xD 2xL 2x2 AND 30 32 32 100 D151 4M,6N,9N 9 , 54LS/74LS174 54LS/74LS174 6 L 1 Lr) 20 21 - 80 D152 4L,6B,9B 14 8-Bit D Flip-Flop(3S) 54LS(2)/74LS374 /74LS374 8xD - K-T) 10 23 23 135 D86 9Z 15 8-Bit D Latch 54LS(2)/74LS373 /74LS373 8xD - 1(H) 15 24 16 120 D85 9Z 16 8-Bit D Latch 54LS(2)/74LS573 /74LS573 8xD - 1(L) - - - - D179 9Z 17 8-Bit Addr Latch 9334 1xD L 1(L) 3 addr bits 11 18 28 ... | OCR Scan |
3 pages, |
93L09 93L22 D154 D155 4 bit shift register 7494 pin diagram D157 D156 74LS502 74151 mux quad D flip-flop 74175 pin 74152 mux 74157 MUX 74151 D flip-flop 74175 pin 54LS/74LS170 54LS/74LS670 54LS/74LS170 abstract |
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| Abstract: 166 ^54/74166 8-BIT SHIFT REGISTER DESCRIPTION-The '166 is an 8-bit, serial- or parallel-in, serial-out shift register using edge triggered D-type flip-flops. Serial and parallel entry are synchronous, with state changes initiated by the rising edge of the clock. An asynchronous Master Reset overrides , 16 GND = Pin 8 4-230 This Material Copyrighted By Its Respective Manufacturer 166 FUNCTIONAL , shifted one bit position (i.e., Qo-»Qi, Q1 Q2, etc.) on the rising edge of the clock. MODE SELECT TABLE ... | OCR Scan |
3 pages, |
8 bit 74166 74166FC 74166DC 54166FM 54166DM 74166PC datasheet abstract |
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| Abstract: Counter (0163) 42 21 74164 8-Bit Parallel-Out Serial Shift Register (0164) 35 22 74165 Parallel-LOAD 8-Bit Shift Register (0165) 57 23 74166 8-Bit Shift Register (0166) 52 24 74169 Synchronous 4-Bit , 8-Bit Shift Register (0091) 34 4 7492 Divide-by-twelve Counter (0092) 23 5 7493 4-Bit Binary Counter (0093) 18 6 7494 4-Bit Shift Register (0094) 32 7 7495 4-Bit Shift Register (0095) 28 8 74138 , Parallel-Access Shift Register (0195) 29 34 74259 8-Bit Addressable Latches (0259) 37 35 74280 9-Bit Odd/Even ... | OCR Scan |
8 pages, |
74151 adder Ci 74153 bcd counter using t flip flop diagram counter schematic diagram 74161 TTL 74139 7493 binary counter diagram CI 74151 counter 74190 74181 74175 clock inverter 74169 binary counter 74151 demultiplexer 74195 TTL shift register MSM60300 MSM60700 MSM60300 abstract |
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| Abstract: Figure 8 shows, a flip-flop (CNTEN) is set when SDFS goes high, which in turn enables a 6-bit counter. , system described below is as follows: 1. The AD1847 AD1847 is to be interfaced to a 16-bit parallel bus. 2. , from reading the specs on the AD1847 AD1847 interface, the bulk of the system is composed of six 16-bit shift , Serial-ln-Parallel-Out registers). An additional 16-bit register contains outgoing control information (to be sent to the , design, the shift registers only need to receive (SIPOs) or transmit (PISOs) the first three 16-bit words ... | OCR Scan |
10 pages, |
AD1847 8 bit 74166 74164 counter 74164 220H h242 200H pin diagram of 74163 ic 74164 data sheet IC 74164 ic 74163 16- bit up counter pin diagram of ic 74163 74166 applications h242 regulator AN-387 AD1847 AN-387 abstract |
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| Abstract: system described below is as follows: 1. The AD1847 AD1847 is to be interfaced to a 16-bit parallel bus. 2. The , specs on the AD1847 AD1847 interface, the bulk of the system is composed of six 16-bit shift registers. Three , Figure 1. System Block Diagram Serial-ln-Parallel-Out registers). An additional 16-bit register contains , (SIPOs) or transmit (PISOs) the first three 16-bit words of a frame. The first word contains control , signals that control the AD1847 AD1847 data stream. As Figure 8 shows, a flip-flop (CNTEN) is set when SDFS goes ... | OCR Scan |
10 pages, |
TR116 220H AD1847 AN-387 ci 74273 EPM7160LC84 ic 74163 16- bit up counter IC 74166 of ic 74166 200H ic 74273 74273 IC pins and their function in ic 74163 AN-387 abstract |
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| Data Sheet Abstract: SN54166 SN54166 SN54166 SN54166, SN54LS166A SN54LS166A SN54LS166A SN54LS166A, SN74166, SN74LS166A SN74LS166A SN74LS166A SN74LS166A:PARALLEL-LOAD 8-BIT SHIFT REGISTERS SN54166 SN54166 SN54166 SN54166, SN54LS166A SN54LS166A SN54LS166A SN54LS166A, SN74166, SN74LS166A SN74LS166A SN74LS166A SN74LS166A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SDLS063 SDLS063 SDLS063 SDLS063 - OCTOBER 1976 - REVISED MARCH 1988 PRODUCTION Conversion description The '166 and 'LS166A LS166A LS166A LS166A 8-bit shift registers are compatible with most otherTTL logic inputs, includingthe clock, and sets all flip-flops to zero. Title: PARALLEL-LOAD 8-BIT SHIFT REGISTERS www.datasheetarchive.com/files/texas-instruments/sc/psheets/abstract/datasht/sdls063.htm |
Texas Instruments | 01/06/1998 | 6.85 Kb | HTM | sdls063.htm |
| .INFO> SN54166 SN54166, SN54LS166A SN54LS166A SN54LS166A SN54LS166A, SN74166, SN74LS166A SN74LS166A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SDLS063 SDLS063 .SUMMARY>description The '166 and 'LS166A LS166A LS166A LS166A 8-bit shift registers are compatible with most other TTL logic families ="LEFT" COLWIDTH="0.73in"> www.datasheetarchive.com/files/texas-instruments/asl_data/aslbooks/graphics/sdls063/sdls063.fea |
Texas Instruments | 16/12/1996 | 9.24 Kb | FEA | sdls063.fea |
| internal ( ( 8, 9,10,11), (12,13, 1, 2) ) ; } part 7481 : default dil14 { newattr "$comment" = "16 Bit 14 { newattr "$comment" = "8 Bit Shift Register" ; newattr "$ttlout" = "TP" ; pin (ck 24b { newattr "$comment" = "Dual 8 Bit Bistable Latch" ; pin (g,d1,q1,d2,q2,d3,q3,d4,q4) ; net " = "8 Bit Shift Register SIPO" ; newattr "$ttlout" = "TP" ; pin (/clr,clk,a "$comment" = "8 Bit PISO Shift Register" ; newattr "$ttlout" = "TP" ; pin (shld,clkinh,clk,ser,a www.datasheetarchive.com/download/48664731-299145ZC/bae65022linux.tgz |
Kaleidoscope | 22/08/2005 | 11421.08 Kb | TGZ | bae65022linux.tgz |
| * *$ *- * 7482 2-BIT BINARY FULL ADDERS * * THE TTL DATA BOOK, VOL 2, STANDARD, S, LS, TTL, 1985, TI * NH 8 + tphlty=8ns tphlmx=15ns _LEVEL={IO_LEVEL} .ends * .model D_02 ugate ( + tplhty=12ns tplhmx=22ns + tphlty=8ns tphlmx=15ns tplhmx=45ns + tphlty=8ns tphlmx=15ns * .model D_04 ugate ( + tplhty=12ns tplhmx=22ns + tphlty=8ns tphlmx=15ns www.datasheetarchive.com/files/spicemodels/misc/spice_model_cd/mixed part list/spice-models-collection/7400.lib |
Spice Models | 29/07/2012 | 282.15 Kb | LIB | 7400.lib |
| * *$ *- * 7482 2-BIT BINARY FULL ADDERS * * THE TTL DATA BOOK, VOL 2, STANDARD, S, LS, TTL, 1985, TI * NH 8 + tphlty=8ns tphlmx=15ns _LEVEL={IO_LEVEL} .ends * .model D_02 ugate ( + tplhty=12ns tplhmx=22ns + tphlty=8ns tphlmx=15ns tplhmx=45ns + tphlty=8ns tphlmx=15ns * .model D_04 ugate ( + tplhty=12ns tplhmx=22ns + tphlty=8ns tphlmx=15ns www.datasheetarchive.com/files/spicemodels/misc/7400.lib |
Spice Models | 19/12/2001 | 282.17 Kb | LIB | 7400.lib |
| LIBRARY range 74150-74166 * * - 74150 /15/94 * .SUBCKT 74150 E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 + A B C D GBAR W + E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 + A B C D GBAR W_O + D0_GATE IO & B & C & dbar & g)} + a8 = {(E8 & abar & bbar & cbar & D & g)} + a9 = {(E9 & A & bbar | a1 | a2 | a3 | a4 | a5 | a6 | a7) } + Wb = { (a8 | a9 | a10 | a11 | a12 | a13 | a14 | a15 www.datasheetarchive.com/files/spicemodels/misc/modelos/spice_complete/dig150.lib |
Spice Models | 18/04/2010 | 337.13 Kb | LIB | dig150.lib |
| Products Group | | IBIS model of 74LVT162373 74LVT162373 74LVT162373 74LVT162373 | 3.3V 16-BIT D-TYPE TRANSPARENT LATCH WITH 30O TERMINATION .44e-9 0.846e-12 7 VCC POWER 47.4e-3 3.10e-9 0.844e-12 8 lvt_in 49.2e-3 2.25e-9 0.687e-12 36 2D0 lvt_in 47.8e-3 2.17e-9 0.656e-12 37 1D7 lvt_in 47.8e-3 2.17e-9 0.512e-12 38 1D6 max R_pkg 69.35e-03 46.8e-03 91.9e-03 L_pkg 5.31e-09 3.33e-09 7.29e www.datasheetarchive.com/files/nxp/misc/support/models/lvt16/ibis/lvt162373.ibs |
NXP | 01/07/2006 | 131.51 Kb | IBS | lvt162373.ibs |
| Products Group | | IBIS model of 74LVT162244B 74LVT162244B 74LVT162244B 74LVT162244B | 3.3V 16-BIT BUFFER/LINE DRIVER; NON-INVERTING WITH BUS .44e-9 0.846e-12 7 VCC POWER 47.4e-3 3.10e-9 0.844e-12 8 lvt_in 49.2e-3 2.25e-9 0.687e-12 36 3A0 lvt_in 47.8e-3 2.17e-9 0.656e-12 37 2A3 lvt_in 47.8e-3 2.17e-9 0.512e-12 38 2A2 max R_pkg 69.35e-03 46.8e-03 91.9e-03 L_pkg 5.31e-09 3.33e-09 7.29e www.datasheetarchive.com/files/nxp/misc/support/models/lvt16/ibis/lvt162244b.ibs |
NXP | 01/07/2006 | 131.54 Kb | IBS | lvt162244b.ibs |