74VHC14 VHC14 VHC04 74HC14 74VHC14M MS-012 74VHC14SJ 74VHC14MTC 74VHC140N MTC14

Hex Schmitt Inverter Features General Description High Speed: tPD = 5.5ns (typ.) at VCC = 5V Low power dissipation: ICC =

74VHC14 74VHC14 Hex Schmitt Inverter Features General Description High Speed: tPD = 5.5ns (typ.) at VCC = 5V Low power dissipation: ICC = 2µA (max.) at TA = 25°C The VHC14 VHC14 is an advanced high speed CMOS Hex Schmitt Inverter fabricated with silicon gate CMOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. Pin configuration and function are the same as the VHC04 VHC04 but the inputs have hysteresis between the positive-going and negativegoing input thresholds, which are capable of transforming slowly changing input signals into sharply defined, jitter-free output signals, thus providing greater noise margin than conventional inverters. High noise immunity: VNIH = VNIL = 28% VCC (min.) Power down protection is provided on all inputs Low noise: VOLP = 0.8V (max.) Pin and function compatible with 74HC14 74HC14 An input protection circuit ensures that 0V to 7V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5V to 3V systems and two supply systems such as battery back up. This circuit prevents device destruction due to mismatched supply and input voltages. Ordering Information Order Number Package Number Package Description 74VHC14M 74VHC14M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012 MS-012, 0.150" Narrow 74VHC14SJ 74VHC14SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74VHC14MTC 74VHC14MTC 74VHC140N 74VHC140N MTC14 MTC14 N14A 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153 MO-153, 4.4mm Wide 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001 MS-001, 0.300" Wide Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering number. All packages are lead free per JEDEC: J-STD-020B J-STD-020B standard. ©1993 Fairchild Semiconductor Corporation 74VHC14 74VHC14 Rev. 1.3.0 www.fairchildsemi.com 74VHC14 74VHC14 - Hex Schmitt Inverter February 2008 74VHC14 74VHC14 - Hex Schmitt Inverter Logic Symbol Connection Diagram IEEE/IEC Pin Description Pin Names Truth Table Description An Inputs A O On Outputs L H H L ©1993 Fairchild Semiconductor Corporation 74VHC14 74VHC14 Rev. 1.3.0 www.fairchildsemi.com 2 Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Rating VCC Supply Voltage 0.5V to +7.0V VIN DC Input Voltage 0.5V to +7.0V VOUT DC Output Voltage 0.5V to VCC + 0.5V IIK Input Diode Current 20mA IOK Output Diode Current ±20mA IOUT DC Output Current ±25mA ICC DC VCC / GND Current TSTG Storage Temperature TL ±50mA 65°C to +150°C Lead Temperature (Soldering, 10 seconds) 260°C Recommended Operating Conditions(1) The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol Parameter VCC Supply Voltage VIN Rating Input Voltage VOUT 0V to +5.5V Output Voltage TOPR 2.0V to +5.5V 0V to VCC Operating Temperature 40°C to +85°C Note: 1. Unused inputs must be held HIGH or LOW. They may not float. ©1993 Fairchild Semiconductor Corporation 74VHC14 74VHC14 Rev. 1.3.0 www.fairchildsemi.com 3 74VHC14 74VHC14 - Hex Schmitt Inverter Absolute Maximum Ratings TA = 40°C to +85°C TA = 25°C Symbol VP Parameter VCC Positive Threshold Voltage Conditions Min. Typ. Max. Min. Units V 3.0 2.20 2.20 4.5 3.15 3.15 5.5 Negative Threshold Voltage 3.85 3.85 3.0 0.90 4.5 Hysteresis Voltage 0.90 1.35 1.35 5.5 VN Max 1.65 V 1.65 3.0 1.20 0.30 1.20 0.40 1.40 0.40 1.40 5.5 HIGH Level Output Voltage 0.30 4.5 VH 0.50 1.60 0.50 1.60 2.0 VIN =VIL IOH = 50µA 1.9 2.0 1.9 3.0 2.9 3.0 2.9 4.5 VOH 4.4 4.5 4.4 IOH = 4mA 4.5 LOW Level Output Voltage 2.0 2.58 IOH = 8mA 3.0 VOL V 3.94 VIN = VIH IOL = 50µA V 2.48 3.80 0.0 0.1 0.1 3.0 0.0 0.1 0.1 4.5 0.0 0.1 0.1 0.36 0.44 3.0 IOL = 4mA 4.5 IOL = 8mA V Input Leakage Current ICC 0.36 0.44 05.5 VIN = 5.5V or GND IIN ±0.1 ±1.0 µA VIN = VCC or GND 2.0 20.0 µA Quiescent Supply Current 5.5 Noise Characteristics TA = 25°C Symbol Parameter VCC Conditions Typ. Limits Units Quiet Output Maximum Dynamic VOL 5.0 CL = 50 pF 0.4 0.8 V VOLV(2) Quiet Output Minimum Dynamic VOL 5.0 CL = 50 pF 0.4 0.8 V (2) Minimum HIGH Level Dynamic Input Voltage 5.0 CL = 50 pF 3.5 V VILD(2) Maximum LOW Level Dynamic Input Voltage 5.0 CL = 50 pF 1.5 V VOLP VIHD (2) Note: 2. Parameter guaranteed by design. ©1993 Fairchild Semiconductor Corporation 74VHC14 74VHC14 Rev. 1.3.0 www.fairchildsemi.com 4 74VHC14 74VHC14 - Hex Schmitt Inverter DC Electrical Characteristics TA = 40°C to +85°C TA = 25°C Symbol VCC (V) Conditions 3.3 ± 0.3 5.0 ± 0.5 CIN Input Capacitance CPD Power Dissipation Capacitance Max. Min. Max. Units CL = 15pF 8.3 12.8 1.0 15.0 ns 10.8 16.3 1.0 18.5 CL = 15pF 5.5 8.6 1.0 10.0 CL = 50pF Propagation Delay Typ. CL = 50pF tPLH, tPHL Parameter 7.0 10.6 1.0 12.0 4 10 VCC (3) = Open Min. 10 21 ns pF pF Note: 3. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC (opr.) = CPD · VCC · fIN + ICC / 6 (per gate). ©1993 Fairchild Semiconductor Corporation 74VHC14 74VHC14 Rev. 1.3.0 www.fairchildsemi.com 5 74VHC14 74VHC14 - Hex Schmitt Inverter AC Electrical Characteristics 8.75 8.50 0.65 A 7.62 14 8 B 5.60 4.00 3.80 6.00 PIN ONE INDICATOR 1 1.70 7 0.51 0.35 1.27 0.25 1.27 LAND PATTERN RECOMMENDATION M C B A (0.33) 1.75 MAX 1.50 1.25 SEE DETAIL A 0.25 0.10 C 0.25 0.19 0.10 C NOTES: UNLESS OTHERWISE SPECIFIED A) THIS PACKAGE CONFORMS TO JEDEC MS-012 MS-012, VARIATION AB, ISSUE C, B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD GAGE PLANE FLASH OR BURRS. D) LANDPATTERN STANDARD: SOIC127P600X145-14M SOIC127P600X145-14M 0.36 E) DRAWING CONFORMS TO ASME Y14.5M-1994 5M-1994 F) DRAWING FILE NAME: M14AREV13 M14AREV13 0.50 X 45° 0.25 R0.10 R0.10 8° 0° 0.90 0.50 (1.04) SEATING PLANE DETAIL A SCALE: 20:1 Figure 1. 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012 MS-012, 0.150" Narrow Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ ©1993 Fairchild Semiconductor Corporation 74VHC14 74VHC14 Rev. 1.3.0 www.fairchildsemi.com 6 74VHC14 74VHC14 - Hex Schmitt Inverter Physical Dimensions 74VHC14 74VHC14 - Hex Schmitt Inverter Physical Dimensions (Continued) Figure 2. 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ ©1993 Fairchild Semiconductor Corporation 74VHC14 74VHC14 Rev. 1.3.0 www.fairchildsemi.com 7 74VHC14 74VHC14 - Hex Schmitt Inverter Physical Dimensions (Continued) 0.65 0.43 TYP 1.65 6.10 0.45 12.00° TOP & BOTTOM R0.09 min A. CONFORMS TO JEDEC REGISTRATION MO-153 MO-153, VARIATION AB, REF NOTE 6 B. DIMENSIONS ARE IN MILLIMETERS C. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH, AND TIE BAR EXTRUSIONS D. DIMENSIONING AND TOLERANCES PER ANSI Y14.5M, 1982 E. LANDPATTERN STANDARD: SOP65P640X110-14M F. DRAWING FILE NAME: MTC14REV6 MTC14REV6 1.00 R0.09min Figure 3. 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153 MO-153, 4.4mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ ©1993 Fairchild Semiconductor Corporation 74VHC14 74VHC14 Rev. 1.3.0 www.fairchildsemi.com 8 74VHC14 74VHC14 - Hex Schmitt Inverter Physical Dimensions (Continued) 19.56 18.80 14 8 6.60 6.09 1 7 (1.74) 8.12 7.62 1.77 1.14 3.56 3.30 0.35 0.20 5.33 MAX 0.38 MIN 3.81 3.17 0.58 0.35 8.82 2.54 NOTES: UNLESS OTHERWISE SPECIFIED THIS PACKAGE CONFORMS TO A) JEDEC MS-001 MS-001 VARIATION BA B) ALL DIMENSIONS ARE IN MILLIMETERS. DIMENSIONS ARE EXCLUSIVE OF BURRS, C) MOLD FLASH, AND TIE BAR EXTRUSIONS. D) DIMENSIONS AND TOLERANCES PER ASME Y14.5-1994 E) DRAWING FILE NAME: MKT-N14AREV7 MKT-N14AREV7 Figure 4. 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001 MS-001, 0.300" Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ ©1993 Fairchild Semiconductor Corporation 74VHC14 74VHC14 Rev. 1.3.0 www.fairchildsemi.com 9 ACEx® Build it NowTM CorePLUSTM CROSSVOLTTM CTLTM Current Transfer LogicTM EcoSPARK® EZSWITCHTM * TM PDP-SPMTM SyncFETTM ® Power220® ® Power247 The Power Franchise® POWEREDGE® Power-SPMTM PowerTrench® TinyBoostTM Programmable Active DroopTM TinyBuckTM ® QFET TinyLogic® QSTM TINYOPTOTM QT OptoelectronicsTM TinyPowerTM ® Quiet SeriesTM TinyPWMTM RapidConfigureTM TinyWireTM Fairchild® SMART STARTTM Fairchild Semiconductor® µSerDesTM ® SPM FACT Quiet SeriesTM UHC® STEALTHTM FACT® Ultra FRFETTM SuperFETTM FAST® UniFETTM SuperSOTTM-3 FastvCoreTM VCXTM ® ®* SuperSOTTM-6 FlashWriter SuperSOTTM-8 * EZSWITCHTM and FlashWriter® are trademarks of System General Corporation, used under license by Fairchild Semiconductor. FPSTM FRFET® Global Power ResourceSM Green FPSTM Green FPSTM e-SeriesTM GTOTM i-LoTM IntelliMAXTM ISOPLANARTM MegaBuckTM MICROCOUPLERTM MicroFETTM MicroPakTM MillerDriveTM Motion-SPMTM OPTOLOGIC® OPTOPLANAR® DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD'S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve the design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild Semiconductor. The datasheet is printed for reference information only. Rev. I32 ©1993 Fairchild Semiconductor Corporation 74VHC14 74VHC14 Rev. 1.3.0 www.fairchildsemi.com 10 74VHC14 74VHC14 - Hex Schmitt Inverter TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended to be an exhaustive list of all such trademarks.