74VCX162373 VCX162373 74VCX162373MTD MTD48 MO-153 DS500236 - Datasheet Archive

 

Revised November 1999 74VCX162373 Low Voltage 16-Bit Transparent Latch with 3.6V Tolerant Inputs and Outputs and 26 Series

 

Preliminary Revised November 1999 74VCX162373 74VCX162373 Low Voltage 16-Bit Transparent Latch with 3.6V Tolerant Inputs and Outputs and 26 Series Resistors in Outputs (Preliminary) General Description Features The VCX162373 VCX162373 contains sixteen non-inverting latches with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. The flip-flops appear to be transparent to the data when the Latch enable (LE) is HIGH. When LE is LOW, the data that meets the setup time is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the outputs are in a high impedance state. s 1.65V­3.6V VCC supply operation The VCX162373 VCX162373 is also designed with 26 resistors in the outputs. This design reduces line noise in applications such as memory address drivers, clock drivers and bus transceivers/transmitters. The 74VCX162373 74VCX162373 is designed for low voltage (1.65V to 3.6V) VCC applications with I/O compatibility up to 3.6V. The 74VCX162373 74VCX162373 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining low CMOS power dissipation. s 3.6V tolerant inputs and outputs s 26 series resistors in outputs s tPD (In to On) 3.3 ns max for 3.0V to 3.6V VCC 4.5 ns max for 2.3V to 2.7V VCC 9.0 ns max for 1.65V to 1.95V VCC s Power-off high impedance inputs and outputs s Support live insertion and withdrawal (Note 1) s Static Drive (IOH/IOL) ±12 mA @ 3.0V VCC ±8 mA @ 2.3V VCC ±3 mA @ 1.65V VCC s Uses patented noise/EMI reduction circuitry s Latch-up performance exceeds 300 mA s ESD performance: Human body model > 2000V Machine model > 200V Note 1: To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pull-up resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver. Ordering Code: Ordering Number 74VCX162373MTD 74VCX162373MTD Package Package Description Number MTD48 MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153 MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code. Logic Symbol Pin Descriptions Pin Names Description OEn Inputs O0­O15 DS500236 DS500236 Latch Enable Input I0­I15 © 1999 Fairchild Semiconductor Corporation Output Enable Input (Active LOW) LEn Outputs www.fairchildsemi.com 74VCX162373 74VCX162373 Low Voltage 16-Bit Transparent Latch November 1999 74VCX162373 74VCX162373 Preliminary Connection Diagram Truth Tables Inputs Outputs LE1 OE1 I0­I7 O0­O7 Z X H X H L L L H L H H L L X O0 Inputs Outputs LE2 OE2 I8­I15 O8­O15 Z X H X H L L L H L H H L L X O0 H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial (HIGH or LOW, inputs may not float) Z = High Impedance O0 = Previous O0 before HIGH-to-LOW of Latch Enable Functional Description The 74VCX162373 74VCX162373 contains sixteen edge D-type latches with 3-STATE outputs. The device is byte controlled with each byte functioning identically, but independent of the other. Control pins can be shorted together to obtain full 16-bit operation. The following description applies to each byte. When the Latch Enable (LEn) input is HIGH, data on the In enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its I input changes. When LEn is LOW, the latches store information that was present on the I inputs a setup time preceding the HIGH-to-LOW transition on LEn. The 3STATE outputs are controlled by the Output Enable (OEn) input. When OEn is LOW the standard outputs are in the 2state mode. When OEn is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches. Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 Preliminary Supply Voltage (VCC) -0.5V to +4.6V DC Input Voltage (VI) Recommended Operating Conditions (Note 4) -0.5V to +4.6V Power Supply Output Voltage (VO) Operating -0.5V to +4.6V Outputs 3-STATED Outputs Active (Note 3) -0.5V to VCC +0.5V Output Voltage (VO) -50 mA Output in Active States DC Output Diode Current (IOK) -50 mA VO > VCC +50 mA VCC = 3.0V to 3.6V ±12 mA VCC = 2.3V to 2.7V ±50 mA ±8 mA VCC = 1.65V to 2.3V DC VCC or GND Current per Supply Pin (ICC or GND) 0.0V to 3.6V Output Current in IOH/IOL DC Output Source/Sink Current Storage Temperature Range (TSTG) 0V to VCC Output in "OFF" State VO < 0V (IOH/IOL) 1.2V to 3.6V -0.3V to +3.6V Input Voltage DC Input Diode Current (IIK) VI < 0V 1.65V to 3.6V Data Retention Only ±3 mA Free Air Operating Temperature (TA) ±100 mA -40°C to +85°C Minimum Input Edge Rate (t/V) -65°C to +150°C VIN = 0.8V to 2.0V, VCC = 3.0V 10 ns/V Note 2: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The "Recommended Operating Conditions" table will define the conditions for actual device operation. Note 3: IO Absolute Maximum Rating must be observed. Note 4: Floating or unused inputs must be held HIGH or LOW. DC Electrical Characteristics (2.7V < VCC 3.6V) Symbol Parameter Conditions VCC (V) Min 2.0 VIH HIGH Level Input Voltage 2.7­3.6 VIL LOW Level Input Voltage 2.7­3.6 VOH HIGH Level Output Voltage Units V 0.8 V VCC - 0.2 V 2.7 2.2 V IOH = -8 mA 3.0 2.4 V IOH = -12 mA 3.0 2.2 V IOL = 100 µA 2.7­3.6 0.2 V 2.7 0.4 V IOL = 8 mA 3.0 0.55 V IOL = 12 mA LOW Level Output Voltage 2.7­3.6 IOH = -6 mA VOL IOH = -100 µA Max 3.0 0.8 V 2.7­3.6 ±5.0 µA 2.7­3.6 ±10 µA µA IOL = 6 mA II Input Leakage Current 0 VI 3.6V IOZ 3-STATE Output Leakage 0 VO 3.6V VI = V IH or VIL IOFF Power-OFF Leakage Current 0 (VI, VO) 3.6V 0 10 ICC Quiescent Supply Current VI = V CC or GND 2.7­3.6 20 µA VCC (VI, VO) 3.6V (Note 5) 2.7­3.6 ±20 µA VIH = VCC -0.6V 2.7­3.6 750 µA ICC Increase in ICC per Input Note 5: Outputs disabled or 3-STATE only. 3 www.fairchildsemi.com 74VCX162373 74VCX162373 Absolute Maximum Ratings(Note 2) 74VCX162373 74VCX162373 Preliminary DC Electrical Characteristics (2.3V VCC 2.7V) Symbol Parameter V CC (V) Conditions Min 1.6 VIH HIGH Level Input Voltage 2.3 - 2.7 VIL LOW Level Input Voltage VOH HIGH Level Output Voltage V V 3-STATE Output Leakage 2.3 1.8 V 2.3 1.7 IOL = 100 µA 2.3 - 2.7 0.2 V 2.3 0.4 V IOL = 8 mA IOZ V IOL = 6 mA Input Leakage Current V 2.0 IOH = -8 mA II VCC - 0.2 2.3 IOH = -6 mA LOW Level Output Voltage 2.3 - 2.7 IOH = -4 mA VOL IOH = -100 µA Units 0.7 2.3 - 2.7 Max 2.3 0.6 V 2.3 - 2.7 ±5.0 µA 2.3 - 2.7 ±10 µA µA 0 VI 3.6V 0 VO 3.6V VI = VIH or VIL V IOFF Power-OFF Leakage Current 0 (VI, VO) 3.6V 0 10 ICC Quiescent Supply Current VI = VCC or GND 2.3 - 2.7 20 µA VCC (VI, VO) 3.6V (Note 6) 2.3 - 2.7 ±20 µA Max Units Note 6: Outputs disabled or 3-STATE only. DC Electrical Characteristics (1.65V VCC < 2.3V) Symbol Parameter Conditions VCC (V) Min 0.65 × VCC VIH HIGH Level Input Voltage 1.65 - 2.3 VIL LOW Level Input Voltage 1.65 - 2.3 VOH HIGH Level Output Voltage IOH = -100 µA V 0.35 × VCC 1.65 - 2.3 VCC - 0.2 IOH = -3 mA 1.65 1.25 1.65 - 2.3 VOL LOW Level Output Voltage IOL = 100 µA II Input Leakage Current 0 VI 3.6V IOZ 3-STATE Output Leakage IOL = 3 mA V V V 0.2 V 1.65 V ±5.0 µA 1.65 - 2.3 0 VO 3.6V VI = VIH or VIL 0.3 1.65 - 2.3 ±10 µA µA IOFF Power-OFF Leakage Current 0 (VI, VO) 3.6V 0 10 ICC Quiescent Supply Current VI = VCC or GND 1.65 - 2.3 20 µA VCC (VI, VO) 3.6V (Note 7) 1.65 - 2.3 ±20 µA Note 7: Outputs disabled or 3-STATE only. www.fairchildsemi.com 4 Preliminary T A = -40°C to +85°C, CL = 30 pF, RL = 500 Symbol Parameter V CC = 3.3V ± 0.3V V CC = 2.5V ± 0.2V V CC = 1.8V ± 0.15V Min Max Min Max Min Units Max tPHL, tPLH Prop Delay In to On 0.8 3.3 1.0 4.5 1.5 9.0 tPHL, tPLH Prop Delay LE to On 0.8 3.6 1.0 4.9 1.5 9.8 ns tPZL, tPZH Output Enable Time 0.8 3.9 1.0 5.4 1.5 9.8 ns tPLZ, tPHZ Output Disable Time 0.8 4.0 1.0 4.4 1.5 7.9 ns tS Setup Time 1.5 1.5 2.5 tH Hold Time 1.0 1.0 1.0 ns tW Pulse Width 1.5 1.5 4.0 ns tOSHL Output to Output Skew tOSLH (Note 9) 0.5 0.5 ns ns 0.75 ns Note 8: For CL = 50PF, add approximately 300 ps to the AC maximum specification. Note 9: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Dynamic Switching Characteristics Symbol VOLP Parameter CL = 30 pF, VIH = VCC, VIL = 0V V CC (V) TA = +25°C Typical -0.25 -0.35 1.8 1.55 2.05 3.3 CL = 30 pF, VIH = VCC, VIL = 0V -0.15 2.5 Quiet Output Dynamic Valley VOH 1.8 3.3 VOHV 0.35 2.5 CL = 30 pF, VIH = VCC, VIL = 0V 0.25 Units 0.15 3.3 Quiet Output Dynamic Valley VOL 1.8 2.5 VOLV Quiet Output Dynamic Peak VOL Conditions 2.65 V V V Capacitance Symbol Parameter Conditions TA = +25°C Typical Units CIN Input Capacitance VCC = 1.8V, 2.5V or 3.3V, VI = 0V or VCC 6 pF COUT Output Capacitance VI = 0V or VCC, VCC = 1.8V, 2.5V or 3.3V 7 pF CPD Power Dissipation Capacitance 20 pF VI = 0V or VCC, f = 10 MHz, VCC = 1.8V, 2.5V or 3.3V 5 www.fairchildsemi.com 74VCX162373 74VCX162373 AC Electrical Characteristics (Note 8) 74VCX162373 74VCX162373 Preliminary AC Loading and Waveforms TEST SWITCH tPLH, tPHL Open tPZL, tPLZ 6V at VCC = 3.3 ± 0.3V; VCC x 2 at VCC = 2.5 ± 0.2V; 1.8V ± 0.15V tPZH, tPHZ GND FIGURE 1. AC Test Circuit FIGURE 3. 3-STATE Output HIGH Enable and Disable Times for Low Voltage Logic FIGURE 2. Waveform for Inverting and Non-Inverting Functions FIGURE 4. 3-STATE Output LOW Enable and Disable Times for Low Voltage Logic FIGURE 6. Setup Time, Hold Time and Recovery Time for Low Voltage Logic FIGURE 5. Propagation Delay, Pulse Width and tREC Waveforms Symbol VCC 3.3V ± 0.3V 2.5V ± 0.2V 1.8V ± 0.15V Vmi 1.5V VCC/2 VCC/2 Vmo 1.5V VCC/2 VCC/2 VX VOL +0.3V VOL +0.15V VOL +0.15V VY VOH -0.3V VOH -0.15V VOH -0.15V www.fairchildsemi.com 6 Preliminary 74VCX162373 74VCX162373 Low Voltage 16-Bit Transparent Latch Physical Dimensions inches (millimeters) unless otherwise noted 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153 MO-153, 6.1mm Wide Package Number MTD48 MTD48 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 7 www.fairchildsemi.com