74LVC10 |
|
Philips Semiconductors
|
Triple 3-input NAND gate |
|
Original |
PDF
|
74LVC109 |
|
Philips Semiconductors
|
Dual JK flip-flop with set and reset, positive-edge trigger |
|
Original |
PDF
|
74LVC109A |
|
Integrated Device Technology
|
3.3V CMOS DUAL J-K FLIP-FLOP WITH SET AND RESET, POSITIVE-EDGE TRIGGER, 5V TOLERANT I-O |
|
Original |
PDF
|
74LVC109A |
|
Philips Semiconductors
|
Dual J-k Positive Edge Triggered Flip-flop With Clear and Preset |
|
Original |
PDF
|
74LVC109D |
|
Philips Semiconductors
|
Dual J Inverted(K)Flip-flop with Set and Reset, Positive-Edge Trigger |
|
Original |
PDF
|
74LVC109D |
|
Unknown
|
Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. |
|
Scan |
PDF
|
74LVC109D |
|
Philips Semiconductors
|
Dual JK flip-flop with set and reset, positive-edge trigger |
|
Scan |
PDF
|
74LVC109D |
|
Philips Semiconductors
|
Dual JK flip-flop with set and reset, positive-edge trigger |
|
Scan |
PDF
|
74LVC109D,112 |
|
NXP Semiconductors
|
Dual JK(not) flip-flop with set and reset; positive-edge trigger - Description: 3.3V Dual J-/K Flip-Flop with Set and Reset; Positive-Edge Trigger ; Fmax: 330 MHz; Logic switching levels: TTL ; Output drive capability: +/- 24 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 4.0@3.3V ns; Voltage: 1.2-3.6; Package: SOT109-1 (SO16); Container: Tube |
|
Original |
PDF
|
74LVC109D,112 |
|
NXP Semiconductors
|
74LVC109 - IC LVC/LCX/Z SERIES, DUAL POSITIVE EDGE TRIGGERED J-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16, PLASTIC, SO-16, FF/Latch |
|
Original |
PDF
|
74LVC109D,118 |
|
NXP Semiconductors
|
Dual JK(not) flip-flop with set and reset; positive-edge trigger - Description: 3.3V Dual J-/K Flip-Flop with Set and Reset; Positive-Edge Trigger ; Fmax: 330 MHz; Logic switching levels: TTL ; Output drive capability: +/- 24 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 4.0@3.3V ns; Voltage: 1.2-3.6; Package: SOT109-1 (SO16); Container: Reel Pack, SMD, 13" |
|
Original |
PDF
|
74LVC109D,118 |
|
NXP Semiconductors
|
74LVC109 - IC LVC/LCX/Z SERIES, DUAL POSITIVE EDGE TRIGGERED J-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16, PLASTIC, SO-16, FF/Latch |
|
Original |
PDF
|
74LVC109DB |
|
Philips Semiconductors
|
Dual J Inverted(K)Flip-flop with Set and Reset, Positive-Edge Trigger |
|
Original |
PDF
|
74LVC109DB |
|
Unknown
|
Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. |
|
Scan |
PDF
|
|
74LVC109DB |
|
Philips Semiconductors
|
Dual JK flip-flop with set and reset, positive-edge trigger |
|
Scan |
PDF
|
74LVC109DB |
|
Philips Semiconductors
|
Dual JK flip-flop with set and reset, positive-edge trigger |
|
Scan |
PDF
|
74LVC109DB,112 |
|
NXP Semiconductors
|
Dual JK(not) flip-flop with set and reset; positive-edge trigger - Description: 3.3V Dual J-/K Flip-Flop with Set and Reset; Positive-Edge Trigger ; Fmax: 330 MHz; Logic switching levels: TTL ; Output drive capability: +/- 24 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 4.0@3.3V ns; Voltage: 1-2-3.6; Package: SOT338-1 (SSOP16); Container: Tube |
|
Original |
PDF
|
74LVC109DB,112 |
|
NXP Semiconductors
|
74LVC109 - IC LVC/LCX/Z SERIES, DUAL POSITIVE EDGE TRIGGERED J-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16, PLASTIC, SSOP2-16, FF/Latch |
|
Original |
PDF
|
74LVC109DB,118 |
|
NXP Semiconductors
|
Dual JK(not) flip-flop with set and reset; positive-edge trigger - Description: 3.3V Dual J-/K Flip-Flop with Set and Reset; Positive-Edge Trigger ; Fmax: 330 MHz; Logic switching levels: TTL ; Output drive capability: +/- 24 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 4.0@3.3V ns; Voltage: 1-2-3.6; Package: SOT338-1 (SSOP16); Container: Reel Pack, SMD, 13" |
|
Original |
PDF
|
74LVC109DB,118 |
|
NXP Semiconductors
|
74LVC109 - IC LVC/LCX/Z SERIES, DUAL POSITIVE EDGE TRIGGERED J-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16, PLASTIC, SSOP2-16, FF/Latch |
|
Original |
PDF
|