74LVC00A EIA/JESD22-A114-A EIA/JESD22-A115-A 74LVC00AD 74LVC00ADB SSOP14 - Datasheet Archive

 

DATA SHEET 74LVC00A Quad 2-input NAND gate Product specification Supersedes data of 2003 May 07 2003 Sep 04 Philips

 

INTEGRATED CIRCUITS DATA SHEET 74LVC00A 74LVC00A Quad 2-input NAND gate Product specification Supersedes data of 2003 May 07 2003 Sep 04 Philips Semiconductors Product specification Quad 2-input NAND gate 74LVC00A 74LVC00A FEATURES DESCRIPTION · 5 V tolerant inputs for interfacing with 5 V logic The 74LVC00A 74LVC00A is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. · Wide supply voltage range from 1.2 to 3.6 V · CMOS low power consumption Inputs can be driven from either 3.3 or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 and 5 V environment. · Direct interface with TTL levels · Inputs accept voltages up to 5.5 V · Complies with JEDEC standard no. 8-1A Schmitt-trigger action at all inputs makes the circuit tolerant for slower input rise and fall times. · ESD protection: HBM EIA/JESD22-A114-A EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A EIA/JESD22-A115-A exceeds 200 V. The 74LVC00A 74LVC00A provides the 2-input NAND function. · Specified from -40 to +85 °C and -40 to +125 °C. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf 2.5 ns. SYMBOL PARAMETER CONDITIONS tPHL/tPLH propagation delay nA, nB to nY CI input capacitance CPD power dissipation capacitance per gate CL = 50 pF; VCC = 3.3 V TYPICAL 2.1 ns 4.0 pF VCC = 3.3 V; notes 1 and 2 15 pF Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + (CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; N = total load switching outputs; (CL × VCC2 × fo) = sum of the outputs. 2. The condition is VI = GND to VCC. FUNCTION TABLE See note 1. INPUT OUTPUT nA nB nY L L H L H H H L H H H L Note 1. H = HIGH voltage level; L = LOW voltage level. 2003 Sep 04 UNIT 2 Philips Semiconductors Product specification Quad 2-input NAND gate 74LVC00A 74LVC00A ORDERING INFORMATION PACKAGE TYPE NUMBER TEMPERATURE RANGE PINS PACKAGE MATERIAL CODE -40 to +125 °C 14 SO14 plastic SOT108-1 74LVC00AD 74LVC00AD 74LVC00ADB 74LVC00ADB -40 to +125 °C 14 SSOP14 SSOP14 plastic SOT337-1 74LVC00APW 74LVC00APW -40 to +125 °C 14 TSSOP14 TSSOP14 plastic SOT402-1 74LVC00ABQ 74LVC00ABQ -40 to +125 °C 14 DHVQFN14 DHVQFN14 plastic SOT762-1 PINNING PIN SYMBOL DESCRIPTION 1 1A data input 2 1B data input 3 1Y data output 4 2A data input 5 2B data input 6 2Y data output 7 GND ground (0 V) 8 3Y data output 9 3A data input 10 3B data input 11 4Y data output 12 4A data input 13 4B data input 14 VCC supply voltage 2003 Sep 04 3 Philips Semiconductors Product specification Quad 2-input NAND gate 74LVC00A 74LVC00A 1A 1A 1 14 VCC VCC 1 handbook, halfpage handbook, halfpage 14 2 3 2A 4 2B 5 6 9 7 8 4A 2A 4 11 4Y 5 10 3B 2Y 3Y 12 6 9 3A 3A GND 3 10 3B 2Y 4B 1Y 12 4A 13 13 4B 1Y 2 2B 1B 1B 00 11 4Y GND(1) 7 MNA210 MNA210 Top view 8 GND 3Y MNA950 MNA950 (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig.1 Pin configuration SO14 and (T)SSOP14 SSOP14. Fig.2 Pin configuration DHVQFN14 DHVQFN14. handbook, halfpage handbook, halfpage 1 & 3 & 6 & 8 & 11 2 1 2 1A 1B 1Y 3 4 5 2A 2B 2Y 6 5 9 10 3A 3B 3Y 8 9 4 10 12 13 4A 4B 4Y 11 12 13 MNA212 MNA212 MNA246 MNA246 Fig.3 Logic symbol. 2003 Sep 04 Fig.4 Logic symbol (IEEE/IEC). 4 Philips Semiconductors Product specification Quad 2-input NAND gate handbook, halfpage 74LVC00A 74LVC00A A Y B MNA211 MNA211 Fig.5 Logic diagram (one gate). RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VCC supply voltage 1.2 3.6 V VI input voltage 0 5.5 V VO output voltage 0 VCC V Tamb operating ambient temperature tr, tf input rise and fall times for maximum speed performance for low-voltage applications 2.7 3.6 V -40 +125 °C VCC = 1.2 to 2.7 V 0 20 ns/V VCC = 2.7 to 3.6 V 0 10 ns/V LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT -0.5 +6.5 V - -50 mA VCC supply voltage IIK input diode current VI < 0 VI input voltage note 1 -0.5 +6.5 V IOK output diode current VO > VCC or VO < 0 - ±50 mA VO output voltage note 1 -0.5 VCC + 0.5 V IO output source or sink current VO = 0 to VCC - ±50 mA ICC, IGND VCC or GND current - ±100 mA Tstg storage temperature -65 +150 °C Ptot power dissipation - 500 mW Tamb = -40 to +125 °C; note 2 Notes 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. For SO14 packages: above 70 °C derate linearly with 8 mW/K. For SSOP14 SSOP14 and TSSOP14 TSSOP14 packages: above 60 °C derate linearly with 5.5 mW/K. For DHVQFN14 DHVQFN14 packages: above 60 °C derate linearly with 4.5 mW/K. 2003 Sep 04 5 Philips Semiconductors Product specification Quad 2-input NAND gate 74LVC00A 74LVC00A DC CHARACTERISTICS At recommended operating conditions; voltages are referenced to GND (ground = 0 V). TEST CONDITIONS SYMBOL PARAMETER MIN. OTHER TYP.(1) MAX. UNIT VCC (V) Tamb = -40 to +85 °C - - V - - V - - GND V 2.7 to 3.6 - - 0.8 V IO = -100 µA 2.7 to 3.6 VCC - 0.2 - - V IO = -12 mA 2.7 VCC - 0.5 - - V IO = -18 mA 3.0 VCC - 0.6 - - V IO = -24 mA VIH 3.0 VCC - 0.8 - - V HIGH-level input voltage 1.2 VCC 2.7 to 3.6 2.0 VIL LOW-level input voltage VOH HIGH-level output voltage VOL LOW-level output voltage 1.2 VI = VIH or VIL VI = VIH or VIL IO = 100 µA 2.7 to 3.6 - - 0.2 V IO = 12 mA 2.7 - - 0.4 V IO = 24 mA 3.0 - - 0.55 V ILI input leakage current VI = 5.5 V or GND 3.6 - ±0.1 ±5 µA ICC quiescent supply current VI = VCC or GND; IO = 0 3.6 - 0.1 10 µA ICC additional quiescent supply current per input pin VI = VCC - 0.6 V; IO = 0 5 500 µA 2003 Sep 04 6 2.7 to 3.6 - Philips Semiconductors Product specification Quad 2-input NAND gate 74LVC00A 74LVC00A TEST CONDITIONS SYMBOL PARAMETER MIN. OTHER TYP.(1) MAX. UNIT VCC (V) Tamb = -40 to +125 °C VIH HIGH-level input voltage 1.2 VCC 2.7 to 3.6 2.0 - - V - - V GND V - 0.8 V 2.7 to 3.6 VCC - 0.3 - - V IO = -12 mA 2.7 VCC - 0.65 - - V IO = -18 mA 3.0 VCC - 0.75 - - V IO = -24 mA VOL - IO = -100 µA VOH - 2.7 to 3.6 - VIL 3.0 VCC - 1 - - V LOW-level input voltage HIGH-level output voltage LOW-level output voltage 1.2 VI = VIH or VIL VI = VIH or VIL IO = 100 µA 2.7 to 3.6 - - 0.3 V IO = 12 mA 2.7 - - 0.6 V IO = 24 mA 3.0 - - 0.8 V ILI input leakage current VI = 5.5 V or GND 3.6 - - ±20 µA ICC quiescent supply current VI = VCC or GND; IO = 0 3.6 - - 40 µA ICC additional quiescent supply current per input pin VI = VCC - 0.6 V; IO = 0 2.7 to 3.6 - - 5000 µA Note 1. All typical values are measured at VCC = 3.3 V and Tamb = 25 °C. 2003 Sep 04 7 Philips Semiconductors Product specification Quad 2-input NAND gate 74LVC00A 74LVC00A AC CHARACTERISTICS GND = 0 V; tr = tf 2.5 ns. TEST CONDITIONS SYMBOL PARAMETER MIN. WAVEFORMS TYP. MAX. UNIT VCC (V) Tamb = -40 to +85 °C tsk(0) propagation delay nA, nB to nY skew - 12 - ns VCC = 2.7 1.0 2.4 5.1 ns VCC = 3.0 to 3.6 tPHL/tPLH 1.0 2.1(1) 4.3 ns VCC = 3.0 to 3.6 - - 1.0 ns - - - ns 1.0 - 6.5 ns see Figs 6 and 7 VCC = 1.2 note 2 Tamb = -40 to +125 °C tPHL/tPLH propagation delay nA, nB to nY see Figs 6 and 7 VCC = 1.2 skew note 2 VCC = 2.7 VCC = 3.0 to 3.6 tsk(0) 1.0 - 5.5 ns VCC = 3.0 to 3.6 - - 1.5 ns Notes 1. Typical value is measured at VCC = 3.3 V. 2. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. AC WAVEFORMS handbook, halfpage VI VM nA, nB input GND tPHL tPLH VOH VM nY output VOL tTHL tTLH MNA218 MNA218 VM = 1.5 V at VCC 2.7 V; VM = 0.5VCC at VCC < 2.7 V. VOL and VOH are typical output voltage drop that occur with the output load. Fig.6 The input nA, nB to output nY propagation delays. 2003 Sep 04 8 Philips Semiconductors Product specification Quad 2-input NAND gate 74LVC00A 74LVC00A S1 handbook, full pagewidth VCC VI PULSE GENERATOR RL 500 VO 2 × VCC open GND D.U.T. CL 50 pF RT RL 500 MNA368 MNA368 VCC VI tPLH/tPHL 1.2 V VCC open 2.7 V 2.7 V open 3.0 to 3.6 V 2.7 V open Definitions for test circuit: RL = Load resistor. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. Fig.7 Load circuitry for switching times. 2003 Sep 04 9 Philips Semiconductors Product specification Quad 2-input NAND gate 74LVC00A 74LVC00A PACKAGE OUTLINES SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index Lp 1 L 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.010 0.057 0.004 0.049 0.01 0.019 0.0100 0.35 0.014 0.0075 0.34 0.16 0.15 0.05 0.028 0.024 0.01 0.01 0.004 0.028 0.012 inches 0.069 0.244 0.039 0.041 0.228 0.016 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT108-1 076E06 076E06 MS-012 MS-012 2003 Sep 04 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 10 o 8 0o Philips Semiconductors Product specification Quad 2-input NAND gate 74LVC00A 74LVC00A SSOP14 SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm D SOT337-1 E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index Lp L 7 1 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 6.4 6.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 1.4 0.9 8 0o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT337-1 2003 Sep 04 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-150 MO-150 11 o Philips Semiconductors Product specification Quad 2-input NAND gate 74LVC00A 74LVC00A TSSOP14 TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 E D A X c y HE v M A Z 8 14 Q (A 3) A2 A A1 pin 1 index Lp L 1 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.72 0.38 8 0o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT402-1 2003 Sep 04 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-153 MO-153 12 o Philips Semiconductors Product specification Quad 2-input NAND gate 74LVC00A 74LVC00A DHVQFN14 DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT762-1 14 terminals; body 2.5 x 3 x 0.85 mm A B D A A1 E c detail X terminal 1 index area terminal 1 index area C e1 e 2 6 y y1 C v M C A B w M C b L 1 7 Eh e 14 8 13 9 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A(1) max. A1 b c D (1) Dh E (1) Eh e e1 L v w y y1 mm 1 0.05 0.00 0.30 0.18 0.2 3.1 2.9 1.65 1.35 2.6 2.4 1.15 0.85 0.5 2 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT762-1 - MO-241 MO-241 - 2003 Sep 04 13 EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 Philips Semiconductors Product specification Quad 2-input NAND gate 74LVC00A 74LVC00A DATA SHEET STATUS LEVEL DATA SHEET STATUS(1) PRODUCT STATUS(2)(3) Development DEFINITION I Objective data II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Production This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. DEFINITIONS DISCLAIMERS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Right to make changes Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 2003 Sep 04 14 Philips Semiconductors ­ a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com. SCA75 SCA75 © Koninklijke Philips Electronics N.V. 2003 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands R20/05/pp15 Date of release: 2003 Sep 04 Document order number: 9397 750 11929