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74LS78 Datasheet

Part Manufacturer Description PDF Type Ordering
74LS78 Fairchild Semiconductor Full Line Condensed Catalogue 1977
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2 pages,
65.91 Kb

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74LS78 Raytheon Electronics Dual J-K Negative-Edge-Triggered Flip-Flops
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2 pages,
83.44 Kb

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74LS78 Signetics Integrated Circuits Catalogue 1978/79
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27 pages,
898.48 Kb

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74LS78A Signetics Dual J-K Negative Edge Triggered Flip-Flop / Gated Full Adder
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1 pages,
38.5 Kb

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74LS78A Signetics Quad Bistable Latch / Dual J-K Negative Edge Triggered Flip-Flop
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1 pages,
41.34 Kb

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74LS78DC Fairchild Semiconductor Dual JK Flip-Flop
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3 pages,
80.46 Kb

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74LS78F Signetics Dual J-K Negative Edge Triggered Flip-Flop / Gated Full Adder
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1 pages,
38.5 Kb

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74LS78F Signetics Quad Bistable Latch / Dual J-K Negative Edge Triggered Flip-Flop
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1 pages,
41.34 Kb

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74LS78FC Fairchild Semiconductor Dual JK Flip-Flop
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3 pages,
80.46 Kb

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74LS78PC Fairchild Semiconductor Dual JK Flip-Flop
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3 pages,
80.46 Kb

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74LS78

Catalog Datasheet Results Type PDF Document Tags
Abstract: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D81 54LS/74LS541 54LS/74LS541 Vcc -.,., 1 -_ _ •- J r r* 5 Ii] Iii liJ L±J Iii LAJ Lil liJ liJ bsl QND D82 54LS/74LS78 J SD 0 CP K CD Q -13 lo- ft-12 6 i SD J 0 CP K CD Q D83 54LS/74LS168 54LS/74LS168, 54LS/74LS169 54LS/74LS169 9 3 4 5 6 mil PE Po Pi Pi P3 1 - U/D 7-0 10-0 CEP CET TC 2- CP Oo Qi 02 O3 D84 54LS/74LS490 54LS/74LS490 (each half) 4,12 p-15 1,15-Q 14 , Dual JK 54LS/74LS107 54LS/74LS107 J,K "L - X 60 12 20 D57a 3I,6A,9A 8 Dual JK 54LS/74LS78 J.K S X X 45 16 20 D82 3I ... OCR Scan
datasheet

3 pages,
65.92 Kb

CI 74196 74ls76 ci 7475 CI 74LS76 Fairchild 902 74LS78 74LS109 7475 data latch D147 74LS107 rs latch D146 7475 D latch 54LS/74LS541 54LS/74LS541 54LS/74LS541 abstract
datasheet frame
Abstract: CM O S/BiCM O S Gate Array LZ93/LZ95/LZ96/LZ97 LZ93/LZ95/LZ96/LZ97 Series 74LS Series Macro Cell Libraries (LZ93/LZ95/LZ96/LZ97 LZ93/LZ95/LZ96/LZ97 Series) Model No. 74LS00 74LS00 74LS02 74LS02 74LS04 74LS04 74LS08 74LS08 74LS10 74LS10 74LS11 74LS11 74LS20 74LS20 74LS21 74LS21 74LS27 74LS27 74LS28 74LS28 74LS30 74LS30 74LS32 74LS32 74LS37 74LS37 74LS40 74LS40 74LS42 74LS42 7443 7444 74LS48 74LS48 Model No. 74LS51 74LS51 74LS54 74LS54 74LS55 74LS55 74LS73 74LS73 74LS74 74LS74 74LS75 74LS75 74LS76 74LS76 7447 74LS78 74LS83 74LS83 74LS85 74LS85 74LS86 74LS86 74LS90 74LS90 74LS91 74LS91 74LS92 74LS92 74LS93 74LS93 74LS95 74LS95 74LS97 74LS97 Model No. 74LS107 74LS107 74LS109 74LS109 74LS112 74LS112 74LS113 74LS113 74LS114 74LS114 74LS125 74LS125 74LS126 74LS126 74LS137 74LS137 74LS138 74LS138 74LS139 74LS139 74LS147 74LS147 74LS148 74LS148 74LS151 74LS151 ... OCR Scan
datasheet

1 pages,
25.17 Kb

7447 74ls series 74LS00 74LS138 74LS148 74LS164 74ls192 74LS197 74LS244 74LS258 74ls32 74LS152 74LS04 74LS93 74LS356 LZ93/LZ95/LZ96/LZ97 LZ93/LZ95/LZ96/LZ97 LZ93/LZ95/LZ96/LZ97 abstract
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Abstract: 20 D57a 3I,6A,9A 8 Dual JK 54LS/74LS78 J.K S X X 45 16 20 D82 3I,6A,9A LATCHES/FLIP-FLOPS Item ... OCR Scan
datasheet

3 pages,
64.92 Kb

74196 TTL 74ls112 pin diagram 74LS114 74LS107 CI 74196 ci 7475 74279 Fairchild 902 fairchild 9314 74LS112 7475 data latch 74LS78 d147 7475 D latch 54H/74H78 54H/74H78 abstract
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Abstract: Dual JK 54LS/74LS107 54LS/74LS107 J,K "L - X 60 12 20 D57a 3I,6A,9A 8 Dual JK 54LS/74LS78 J.K S X X 45 16 20 D82 3I ... OCR Scan
datasheet

3 pages,
69.13 Kb

ttl 74ls109 CI 74109 7473 latch 7473 pin diagram 74LS76 logic diagram TTL 74109 74ls74 7475 D latch 74ls107 74LS109 74LS76 FAIRCHILD ci 74LS74 fairchild 9024 TTL 74ls76 datasheet abstract
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Abstract: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D81 54LS/74LS541 54LS/74LS541 Vcc -.,., 1 -_ _ •- J r r* 5 Ii] Iii liJ L±J Iii LAJ Lil liJ liJ bsl QND D82 54LS/74LS78 J SD 0 CP K CD Q -13 lo- ft-12 6 i SD J 0 CP K CD Q D83 54LS/74LS168 54LS/74LS168, 54LS/74LS169 54LS/74LS169 9 3 4 5 6 mil PE Po Pi Pi P3 1 - U/D 7-0 10-0 CEP CET TC 2- CP Oo Qi 02 O3 D84 54LS/74LS490 54LS/74LS490 (each half) 4,12 p-15 1,15-Q 14 13 12 11 Vcc = Pin 16 GND = Pin 8 MS CP MR Qo Ol 02 03 2,14 5,11 7,9 3,13 8,10 Vcc = Pin 16 GND ... OCR Scan
datasheet

2 pages,
67.45 Kb

74LS196 7490A 93L10 93s05 D120 D121 db 2X5 74177 ttl 7493 74LS374 74LS78 74293 74LS373 74LS490 74176 54LS/74LS541 54LS/74LS541 abstract
datasheet frame
Abstract: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D81 54LS/74LS541 54LS/74LS541 Vcc -.,., 1 -_ _ •- J r r* 5 Ii] Iii liJ L±J Iii LAJ Lil liJ liJ bsl QND D82 54LS/74LS78 J SD 0 CP K CD Q -13 lo- ft-12 6 i SD J 0 CP K CD Q D83 54LS/74LS168 54LS/74LS168, 54LS/74LS169 54LS/74LS169 9 3 4 5 6 mil PE Po Pi Pi P3 1 - U/D 7-0 10-0 CEP CET TC 2- CP Oo Qi 02 O3 D84 54LS/74LS490 54LS/74LS490 (each half) 4,12 p-15 1,15-Q 14 13 12 11 Vcc = Pin 16 GND = Pin 8 MS CP MR Qo Ol 02 03 2,14 5,11 7,9 3,13 8,10 Vcc = Pin 16 GND ... OCR Scan
datasheet

2 pages,
67.17 Kb

D190 D150 D Flip-Flop 74LS374 74LS373 74ls373 74298 74LS374 74ls373 D flip-flop 74175 pin 54LS/74LS541 54LS/74LS541 abstract
datasheet frame
Abstract: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D81 54LS/74LS541 54LS/74LS541 Vcc -.,., 1 -_ _ •- J r r* 5 Ii] Iii liJ L±J Iii LAJ Lil liJ liJ bsl QND D82 54LS/74LS78 J SD 0 CP K CD Q -13 lo- ft-12 6 i SD J 0 CP K CD Q D83 54LS/74LS168 54LS/74LS168, 54LS/74LS169 54LS/74LS169 9 3 4 5 6 mil PE Po Pi Pi P3 1 - U/D 7-0 10-0 CEP CET TC 2- CP Oo Qi 02 O3 D84 54LS/74LS490 54LS/74LS490 (each half) 4,12 p-15 1,15-Q 14 13 12 11 Vcc = Pin 16 GND = Pin 8 MS CP MR Qo Ol 02 03 2,14 5,11 7,9 3,13 8,10 Vcc = Pin 16 GND ... OCR Scan
datasheet

2 pages,
57.98 Kb

74LS168 93S16 counter 74162 D127 MS PACKAGE 9B 74191 logic diagram ttl 74191 TTL 74192 74LS162 74190 74LS190 pins TTL 93S16 presettable digital clock TTL 74ls193 54LS/74LS541 54LS/74LS541 abstract
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Abstract: +70° C Vcc = +5.0 V±10%, Ta = -55° C to +1250C 1250C Plastic DIP(P) A 74H78PC 74H78PC 9A B 74LS78PC Ceramic DIP (D) A 74H78DC 74H78DC 54H78DM 54H78DM 6A B 74LS78DC 54LS78DM 54LS78DM Flatpak (R A 74H78FC 74H78FC 54H78FM 54H78FM 3I B 74LS78FC , 78 ^4H/74H78 4H/74H78£V/ ^4LS/74LS78 ô / -/ a DUAL JK FLIP-FLOP (With Common Clear and Clock and Separate Set Inputs) DESCRIPTION -The 'H78 is a dual JK master/slave flip-flop with separate Direct Set inputs, a common Direct Clear input and a common Clock Pulse input. Inputs to the master section are ... OCR Scan
datasheet

3 pages,
80.46 Kb

54LS78DM 74H78DC 74H78FC 74H78PC 74LS78PC LS78 54H78DM 74LS78DC 74H78 datasheet abstract
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Abstract: 54LS/74LS78 DESCRIPTION The " 78" is a Dual JK Negative EdgeTriggered Flip-Flop featuring individual J, K, Set, common Clock and common Reset inputs. The Set (Sd ) and Reset (Rd > inputs, when LOW, set or reset the outputs as shown in the Truth Table regardless of the levels at the other inputs. A HIGH level on the Clock (CP) input enables the J and K inputs and data will be accepted. The logic levels at the J and K inputs may be allowed to change while the CP is HIGH and the flipflop will perform ... OCR Scan
datasheet

2 pages,
124.33 Kb

54LS/74LS78 54LS/74LS78 abstract
datasheet frame
Abstract: 54LS/74LS78 LOGIC SYMBOL DESCRIPTION The "78" is a Dual JK Negative Edge-Triggered FI/p-Flop featuring individual J, K, Set, common Clock and common Reset inputs. The Set (Sd> and Reset (Rd> inputs, when LOW, set or reset the outputs as shown in the Truth Table regardless of the levels at the other inputs. A HIGH level on the Clock (CP) input enables the J and K ORDERING CODE (See Section 9 for further Package and Ordering Information) PACKAGES PIN CONF. COMMERCIAL RANGES Vcc = SV ± 5%; TA = 0°C lo »70°C ... OCR Scan
datasheet

2 pages,
75.77 Kb

S54LS78W S54LS78F N74LS78N N74LS78F 54LS/74LS78 54LS/74LS78 abstract
datasheet frame
Abstract: 78 CO NNECTIO N DIAGRAMS PINOUT A ^ 4 H /7 4 H 7 8 £ V / DUAL JK FLIP-FLOP - 5 - C 5 v/54LS/74LS78 6 1> c ~ / (With Common Clear and Clock and Separate Set Inputs) DESCRIPTION - The 'H78 is a dual JK master/slave flip -flo p with separate Direct Set inputs, a common Direct Clear input and a common C lock Pulse input. Inputs to the master section are controlled by the clock pulse. The clock pulse also regulates the c ircu itry which connects the master and slave sections. The sequence of ... OCR Scan
datasheet

3 pages,
150.6 Kb

ic 74ls78 datasheet abstract
datasheet frame
Abstract: Dual JK 54LS/74LS107 54LS/74LS107 J,K "L - X 60 12 20 D57a 3I,6A,9A 8 Dual JK 54LS/74LS78 J.K S X X 45 16 20 D82 3I ... OCR Scan
datasheet

3 pages,
69.93 Kb

7477 D latch D148 D149 D150 D151 Fairchild 902 7475 FAIRCHILD 7475 D latch 74ls76 74LS279 74279 74109 D146 fairchild 9314 pin diagram 7475 datasheet abstract
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$CMP 74LS78 D Dual JK FlipFlop, preset , common clock & reset K TTL JK JKFF $ENDCMP # $CMP 74LS83 74LS83 74LS83 74LS83
www.datasheetarchive.com/files/kaleidoscope/cad/kicad - kicad/library/74xx.dcm
Kaleidoscope 10/10/2004 11.88 Kb DCM 74xx.dcm
EESchema-LIBRARY Version 2.2 Date: 10/10/2004-17:10:44 # # 74469 # DEF 74469 U 0 40 Y Y 1 0 N F0 "U" 0 0 70 H V C C F1 "74469" 0 -200 70 H V C C DRAW S -350 650 350 -650 0 1 0 N X CBO 14 650 -400 300 L 60 60 1 1 O X OE 13 650 -300 300 L 60 60 1 1 I X Q7 15 650 -100 300 L 60 60 1 1 T X VCC 24 0 650 0 D 60 60 1 1 W N X GND 12 0 -650 0 U 60 60 1 1 W N X Q6 16 650 0 300 L 60 60 1 1 T X Q5 17 650 100 300 L 60 60 1 1 T X Q4 18 650 200 300 L 60 60 1 1 T X Q3 19 650 300 300 L 60 60 1 1
www.datasheetarchive.com/files/kaleidoscope/cad/kicad - kicad/library/74xx.lib
Kaleidoscope 10/10/2004 110.31 Kb LIB 74xx.lib
No abstract text available
www.datasheetarchive.com/download/48664731-299145ZC/bae65022linux.tgz
Kaleidoscope 22/08/2005 11421.08 Kb TGZ bae65022linux.tgz
No abstract text available
www.datasheetarchive.com/download/48664731-299145ZC/bae65022linux.tgz
Kaleidoscope 22/08/2005 11421.08 Kb TGZ bae65022linux.tgz
No abstract text available
www.datasheetarchive.com/download/81196427-28964ZD/mpp-vx2.csv
Hitachi 04/11/2000 192.83 Kb CSV mpp-vx2.csv
No abstract text available
www.datasheetarchive.com/download/33044571-28965ZD/mpp.csv
Hitachi 26/08/2001 208.1 Kb CSV mpp.csv
No abstract text available
www.datasheetarchive.com/download/11697323-28963ZD/mpp-vx3.csv
Hitachi 16/10/2002 233.99 Kb CSV mpp-vx3.csv
tpdqlhty=11ns + tpdqlhmx=19ns tpdqhlty=9ns + tpdqhlmx=17ns + ) *$ *- * 74LS78A Dual J-K /28/89 Update interface and model names * .subckt 74LS78A CLK CLRBAR 1PREBAR 1J 1K 1Q 1QBAR
www.datasheetarchive.com/files/spicemodels/misc/spice_model_cd/mixed part list/spice-models-collection/74ls.lib
Spice Models 29/07/2012 571.07 Kb LIB 74ls.lib
tpdqlhty=11ns + tpdqlhmx=19ns tpdqhlty=9ns + tpdqhlmx=17ns + ) *$ *- * 74LS78A Dual J-K /28/89 Update interface and model names * .subckt 74LS78A CLK CLRBAR 1PREBAR 1J 1K 1Q 1QBAR
www.datasheetarchive.com/files/spicemodels/misc/74ls.lib
Spice Models 19/12/2001 571.09 Kb LIB 74ls.lib
* DIGITAL LIBRARY 7400- * * - 7400 - * Quad 2-Input Nand Gates * * The TTL Logic Data Book, 1988, TI Pages 2-3 to 2-7 * bss 2/2/94 * .SUBCKT 7400 1A 1B 1Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(2) DPWR DGND + 1A 1B 1Y + DLY_00 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .model DLY_00 ugate (tplhTY=11ns tplhMX=22ns tphlTY=7ns tphlMX=15ns) .ENDS 7
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Spice Models 18/04/2010 473.91 Kb LIB dig000.lib

Shortform Datasheet Search Results

Part Manufacturer Description Shortform Datasheet Ordering
74LS78DC N/A Dual J-K Flip-Flop

Shortform Datasheet

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74LS78J Raytheon Electronics Dual J-K Flip-Flop

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74LS78PC N/A Dual J-K Flip-Flop

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74LS78W Raytheon Electronics Dual J-K Flip-Flop

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NTE Electronics Cross Reference Results

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NTE74LS78 Buy 74LS78 Buy
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