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Part : NTE74LS78 Supplier : NTE Electronics Manufacturer : Newark element14 Stock : 41 Best Price : $1.40 Price Each : $1.81
Part : DM74LS78N Supplier : National Semiconductor Manufacturer : Bristol Electronics Stock : 275 Best Price : $1.2132 Price Each : $2.80
Part : SN74LS783N Supplier : Motorola Manufacturer : Bristol Electronics Stock : 22 Best Price : $5.04 Price Each : $10.08
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74LS78 Datasheet

Part Manufacturer Description PDF Type
74LS78 Fairchild Semiconductor Full Line Condensed Catalogue 1977 Scan
74LS78 Raytheon Dual J-K Negative-Edge-Triggered Flip-Flops Scan
74LS78 Signetics Integrated Circuits Catalogue 1978/79 Scan
74LS78A Signetics Dual J-K Negative Edge Triggered Flip-Flop / Gated Full Adder Scan
74LS78A Signetics Quad Bistable Latch / Dual J-K Negative Edge Triggered Flip-Flop Scan
74LS78DC Fairchild Semiconductor Dual JK Flip-Flop Scan
74LS78F Signetics Dual J-K Negative Edge Triggered Flip-Flop / Gated Full Adder Scan
74LS78F Signetics Quad Bistable Latch / Dual J-K Negative Edge Triggered Flip-Flop Scan
74LS78FC Fairchild Semiconductor Dual JK Flip-Flop Scan
74LS78PC Fairchild Semiconductor Dual JK Flip-Flop Scan

74LS78

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D81 54LS/74LS541 Vcc -.,., 1 â'"_ _ â'¢â'" J r r* 5 Ii] Iii liJ L±J Iii LAJ Lil liJ liJ bsl QND D82 54LS/74LS78 J SD 0 CP K CD Q -13 lo- ftâ'"12 6 i SD J 0 CP K CD Q D83 54LS/74LS168, 54LS/74LS169 9 3 4 5 6 mil PE Po Pi Pi P3 1 - U/D 7â'"0 10â'"0 CEP CET TC 2- CP Oo Qi 02 O3 D84 54LS/74LS490 (each half) 4,12 , /74LS78 J.K S X X 45 16 20 D82 3I,6A,9A LATCHES/FLIP-FLOPS Item Function DEVICE NO. Data Inputs Common -
OCR Scan
7475 D latch D146 D147 ci 7475 rs latch 74LS109 54LS/74LS78 54LS/74LS373 54LS/74LS374 54LS/74LS256 54S/74S114 54LS/74LS114
Abstract: CM O S/BiCM O S Gate Array LZ93/LZ95/LZ96/LZ97 Series 74LS Series Macro Cell Libraries (LZ93/LZ95/LZ96/LZ97 Series) Model No. 74LS00 74LS02 74LS04 74LS08 74LS10 74LS11 74LS20 74LS21 74LS27 74LS28 74LS30 74LS32 74LS37 74LS40 74LS42 7443 7444 74LS48 Model No. 74LS51 74LS54 74LS55 74LS73 74LS74 74LS75 74LS76 7447 74LS78 74LS83 74LS85 74LS86 74LS90 74LS91 74LS92 74LS93 74LS95 74LS97 Model No. 74LS107 74LS109 74LS112 74LS113 74LS114 74LS125 74LS126 74LS137 74LS138 74LS139 74LS147 74LS148 74LS151 -
OCR Scan
74LS152 74LS183 74LS248 74LS258 74LS275 74LS356 74ls series 74LS396 7447 74LS153 74LS155 74LS157 74LS158 74LS160A
Abstract: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D81 54LS/74LS541 Vcc -.,., 1 â'"_ _ â'¢â'" J r r* 5 Ii] Iii liJ L±J Iii LAJ Lil liJ liJ bsl QND D82 54LS/74LS78 J SD 0 CP K CD Q -13 lo- ftâ'"12 6 i SD J 0 CP K CD Q D83 54LS/74LS168, 54LS/74LS169 9 3 4 5 6 mil PE Po Pi Pi P3 1 - U/D 7â'"0 10â'"0 CEP CET TC 2- CP Oo Qi 02 O3 D84 54LS/74LS490 (each half) 4,12 pâ'"15 1,15â'"Q 14 13 12 11 Vcc = Pin 16 GND = Pin 8 MS CP MR Qo Ol 02 03 2,14 5,11 7,9 3,13 8 -
OCR Scan
74LS191 D129 74162 74160 pin 74192 pin diagram of 74163 93L16 93S16 54LS/74L 54LS/74LS161 54LS/74LS162 54LS/74LS163
Abstract: ERCIAL GRADE Vcc = +5.0 V ±5%, Ta = 0 °C to +70° C 74H78PC 74LS78PC 74H78DC 74LS78DC 74H78FC 74LS78FC , 78 CO NNECTIO N DIAGRAMS PINOUT A ^ 4 H /7 4 H 7 8 £ V / DUAL JK FLIP-FLOP - 5 Ö C 5 v/54LS/74LS78 6 1> c ~ / (With Common Clear and Clock and Separate Set Inputs) DESCRIPTION - The 'H78 is a dual JK master/slave flip -flo p with separate Direct Set inputs, a common Direct Clear input and a common C lock Pulse input. Inputs to the master section are controlled by the clock pulse. The -
OCR Scan
74ls786 ic 74ls78 54/74H 54/74LS CLS78
Abstract: Dual JK 54LS/74LS107 J,K "L â'" X 60 12 20 D57a 3I,6A,9A 8 Dual JK 54LS/74LS78 J.K S X X 45 16 20 D82 -
OCR Scan
CI 74196 fairchild 9314 7475 data latch Fairchild 902 d604l ci 9024 54H/74H78 54H/74H106 54S/74S112 54LS/74LS112 54H/74H108 54S/74S113
Abstract: to +70° C Vcc = +5.0 V±10%, Ta = -55° C to +1250C Plastic DIP(P) A 74H78PC 9A B 74LS78PC Ceramic DIP (D) A 74H78DC 54H78DM 6A B 74LS78DC 54LS78DM Flatpak (R A 74H78FC 54H78FM 3I B 74LS78FC , 78 ^4H/74H78£V/ ^4LS/74LS78 ô / -/ a DUAL JK FLIP-FLOP (With Common Clear and Clock and Separate Set Inputs) DESCRIPTION â'"The 'H78 is a dual JK master/slave flip-flop with separate Direct Set inputs, a common Direct Clear input and a common Clock Pulse input. Inputs to the master section are -
OCR Scan
74H78 TK27 74H54 LS78 4LS/74LS78
Abstract: D58 4L,6B,9B 7 Dual JK 54LS/74LS107 J,K "L â'" X 60 12 20 D57a 3I,6A,9A 8 Dual JK 54LS/74LS78 J.K S -
OCR Scan
74L576 TTL 7475 pin diagram 7475 74109 74LS279 74279 93L14 54LS/74LS279 54LS/74LS75 93L08 54LS/74LS77 54S/74S175
Abstract: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D81 54LS/74LS541 Vcc -.,., 1 â'"_ _ â'¢â'" J r r* 5 Ii] Iii liJ L±J Iii LAJ Lil liJ liJ bsl QND D82 54LS/74LS78 J SD 0 CP K CD Q -13 lo- ftâ'"12 6 i SD J 0 CP K CD Q D83 54LS/74LS168, 54LS/74LS169 9 3 4 5 6 mil PE Po Pi Pi P3 1 - U/D 7â'"0 10â'"0 CEP CET TC 2- CP Oo Qi 02 O3 D84 54LS/74LS490 (each half) 4,12 pâ'"15 1,15â'"Q 14 13 12 11 Vcc = Pin 16 GND = Pin 8 MS CP MR Qo Ol 02 03 2,14 5,11 7,9 3,13 8 -
OCR Scan
93L10 74LS93 P TTL 74LS93 TTL 74293 74293 pin diagram 74176 74LS490 54/7490A 54LS/74LS90 54/7493A 54LS/74LS93 54LS/74LS196 54LS/74LS197
Abstract: 54LS/74LS78 LOGIC SYMBOL DESCRIPTION The "78" is a Dual JK Negative Edge-Triggered FI/p-Flop featuring individual J, K, Set, common Clock and common Reset inputs. The Set (Sd> and Reset (Rd> inputs, when LOW, set or reset the outputs as shown in the Truth Table regardless of the levels at the other inputs. A HIGH level on the Clock (CP) input enables the J and K ORDERING CODE (See Section 9 for further Package and Ordering Information) PACKAGES PIN CONF. COMMERCIAL RANGES Vcc = SV ± 5%; TA = 0 -
OCR Scan
N74LS78N N74LS78F S54LS78F S54LS78W 54H/74H S4S/74S
Abstract: ro - Item Dual JK 54LS/74LS78 c_ Dual JK Dual JK Dual JK Dual JK 54LS/74LS76 -
OCR Scan
logic ic 7476 pin diagram logic ic 74LS76 pin diagram ic 74109 7476 Connection diagram IC 74196 74109 dual JK 54S/74S109 54LS/74LS109 54H/74H74 54S/74S74 54LS/74LS74 54H/74H73
Abstract: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D81 54LS/74LS541 Vcc -.,., 1 â'"_ _ â'¢â'" J r r* 5 Ii] Iii liJ L±J Iii LAJ Lil liJ liJ bsl QND D82 54LS/74LS78 J SD 0 CP K CD Q -13 lo- ftâ'"12 6 i SD J 0 CP K CD Q D83 54LS/74LS168, 54LS/74LS169 9 3 4 5 6 mil PE Po Pi Pi P3 1 - U/D 7â'"0 10â'"0 CEP CET TC 2- CP Oo Qi 02 O3 D84 54LS/74LS490 (each half) 4,12 pâ'"15 1,15â'"Q 14 13 12 11 Vcc = Pin 16 GND = Pin 8 MS CP MR Qo Ol 02 03 2,14 5,11 7,9 3,13 8 -
OCR Scan
D flip-flop 74175 pin 74ls373 74LS374 74298 D154 D150 54LS/74LS375 54LS/74LS298 54S/74S174 54LS/74LS174
Abstract: ) Flatpak , NATIONAL SEMICOND {LOGIC} D5E D | bSOllEE 0Dfc.37a4 3 I 78 54H/74H78 54LS/74LS78 DUAL JK FLIP-FLOP (With Common Clear and Clock and Separate Set Inputs) DESCRIPTIO N - The 'H78 is a dual JK master/slave flip -flo p w ith separate D irect Set Inputs, a com m on Direct Clear input and a com m on -
OCR Scan
Abstract: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D81 54LS/74LS541 Vcc -.,., 1 â'"_ _ â'¢â'" J r r* 5 Ii] Iii liJ L±J Iii LAJ Lil liJ liJ bsl QND D82 54LS/74LS78 J SD 0 CP K CD Q -13 lo- ftâ'"12 6 i SD J 0 CP K CD Q D83 54LS/74LS168, 54LS/74LS169 9 3 4 5 6 mil PE Po Pi Pi P3 1 - U/D 7â'"0 10â'"0 CEP CET TC 2- CP Oo Qi 02 O3 D84 54LS/74LS490 (each half) 4,12 pâ'"15 1,15â'"Q 14 13 12 11 Vcc = Pin 16 GND = Pin 8 MS CP MR Qo Ol 02 03 2,14 5,11 7,9 3,13 8 -
OCR Scan
74S140 74S40 ttl 741 1. IC 74IS244 74LS244 diagram Fairchild 96106 741 16 PIN 90CI9 54H/74H40 54LS/ 74LS245
Abstract: Dual JK 54LS/74LS78 J.K S X X 45 16 20 D82 3I,6A,9A LATCHES/FLIP-FLOPS Item Function DEVICE NO. Data -
OCR Scan
CI 7474 CI 7473 ci 7476 7474 D latch CI 74LS76 CI 74107 54LS/74LS73 54H/74H103 54H/74H76 54LS/74LS
Abstract: 54LS/74LS78 DESCRIPTION The " 78" is a Dual JK Negative EdgeTriggered Flip-Flop featuring individual J, K, Set, common Clock and common Reset inputs. The Set (Sd ) and Reset (Rd > inputs, when LOW, set or reset the outputs as shown in the Truth Table regardless of the levels at the other inputs. A HIGH level on the Clock (CP) input enables the J and K inputs and data will be accepted. The logic levels at the J and K inputs may be allowed to change while the CP is HIGH and the flipflop will perform -
OCR Scan
54S/74S
Abstract: D58 4L,6B,9B 7 Dual JK 54LS/74LS107 J,K "L â'" X 60 12 20 D57a 3I,6A,9A 8 Dual JK 54LS/74LS78 J.K S -
OCR Scan
CI 74LS90 ci 74193 ci 74ls193 ci 7492 CI 74176 sn 7492 ttl S4/74293 54LS/74LS293 S4/7493A 93S10 54LS/74LS160 93S05
Abstract: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D81 54LS/74LS541 Vcc -.,., 1 â'"_ _ â'¢â'" J r r* 5 Ii] Iii liJ L±J Iii LAJ Lil liJ liJ bsl QND D82 54LS/74LS78 J SD 0 CP K CD Q -13 lo- ftâ'"12 6 i SD J 0 CP K CD Q D83 54LS/74LS168, 54LS/74LS169 9 3 4 5 6 mil PE Po Pi Pi P3 1 - U/D 7â'"0 10â'"0 CEP CET TC 2- CP Oo Qi 02 O3 D84 54LS/74LS490 (each half) 4,12 pâ'"15 1,15â'"Q 14 13 12 11 Vcc = Pin 16 GND = Pin 8 MS CP MR Qo Ol 02 03 2,14 5,11 7,9 3,13 8 -
OCR Scan
74ls373 parallel port d92 02 74175 ttl pin diagram 74198 ttl 74ls175 pin diagram 74198 54LS/74LS194 93L34 54LS/74LS259
Abstract: 74LS78 74LS82 74LS83 74LS83A 74LS85 74LS86 74LS90 74LS91 74LS92 74LS93 74LS94 74LS95 74LS95B 74LS96 -
OCR Scan
74LS176 74LS286 74ls150 74LS177 74LS116 74ls198
Abstract: CO A < B ,A > B Others 20 80 60 20 60 120 160 40 20 20 60 40 54/74LS78 54 74 0.7 0.8 2 , /74LS78 54 J/K Input 74 Preset Clear Clock 54/74LS83A 54/74LS85 54/74LS86 54/74LS90 54 Any A or B 74 CO 54 -
OCR Scan
L-53ID-B-TNR2.54 54/74S508 74ls192 ic 74ls13 L-934SYD-TNR2.54 54/74LSOO 54/74LS01 54/74LS02 54/74LS03 54/74LS04 54/74LS05
Abstract: 74S74 7475 74LS75 7476. 74C76 74H76 74LS76A 74LS77 74H78 74LS78 7480 7481 7482 ' 7483 74LS83A 7485 74C85 -
OCR Scan
74LS324 7400 TTL 74LS327 80C96 7402, 7404, 7408, 7432, 7400 74251 multiplexer G0G513S 74C00 74H00 74S00 74H01 74LS01
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