NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Catalog Datasheet Results | Type | Document Tags |
| Abstract: , and a 74LS unit load (LSul) is 20fjA l,H and -0.4mA ),L PIN CONFIGURATION LOGIC SYMBOL LOGIC SYMBOL , Signetics 74LS244, S244 Buffers Logic Products FUNCTION TABLE H = HIGH voltage level L = LOW , Specification TYPE TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT (TOTAL) 74LS244 12ns 25mA 74S244 74S244 6ns , 74LS244D 74LS244D NOTE: For information regarding devices processed to Military Specifications, see the Signetics Military Products Data Manual. INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS DESCRIPTION 74S 74LS All ... | OCR Scan |
4 pages, |
N74LS244N 1N916 74LS 74LS244 buffer 1N3064 74S244 LOGIC DESCRIPTION 74LS244 74S244N LOGIC DESCRIPTION OF 74LS244 LOGIC OF 74LS244 74L5244 74LS244D 74LS244 20 PINS 74LS244 74LS244 74LS244 abstract |
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| Abstract: 74LS unit load (LSul) is 20(iA lIH and -0.4mA l,L. PIN CONFIGURATION LOGIC SYMBOL Ã-F, [T •ao Å' VbO E , Signetics 74LS244, S244 Buffers Logic Products FUNCTION TABLE H - HIGH voltage level L - LOW , Specification TYPE TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT (TOTAL) 74LS244 12ns 25mA 74S244 74S244 6ns , 74LS244D 74LS244D For information regarding devices processed to Military Specifications, see the Signetics Military Products Data Manual. INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS DESCRIPTION 74S 74LS All ... | OCR Scan |
4 pages, |
TTL 74LS244 74LS 74LS244 N 74S244 family 74ls of 74LS244 N74LS244 N74LS244N H 74L5244 74l8244 74LS244D 74LS244 LOGIC 74LS244 74LS244 20 PINS 74LS244 abstract |
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| Abstract: FDC37C93X FDC37C93X, FDC37C93XPM FDC37C93XPM, and FDC37C93XFR FDC37C93XFR Ultra I/O Controller. These three parts are pin for pin compatible , and pin names for all three parts PIN DESCRIPTION A2, A1, A0 (Device Address) - These three , First configuration is setting J1 to 3-2, J2 to 3-2, and J3 to 3-2. This configuration will use pins 32 , , J2 to 1-2, and J3 to N.C. (No Connection). This configuration will use pins 32, 33, 34 as N.C. , , Active High). This input is used to transmit serial data. This pin and a MODE pin are used to determine ... | Original |
6 pages, |
74LS244 74ls244 data sheet FDC37C93X FDC37C93XFR infrared transistor LOGIC DESCRIPTION OF 74LS244 nrx 34 LOGIC DESCRIPTION 74LS244 applications of 74LS244 74LS244 uses and functions FDC37C93XPM FDC37C93X abstract |
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| Abstract: programmer can load program code, part configuration, and EEPROM data into the PIC16C84 PIC16C84. In read back mode , into programming mode by forcing a low logic level on RB7 (pin 13) and RB6 (pin 12) while MCLR (pin 4 , After program/verification the MCLR pin is brought low to reset the target microcontroller and then , INTERFACE GND (pin 5) 4 2 2 U2 74LS244 DATA (RB7, pin 13) 18 10 7 19 D1 R5 750 , 22 uF 35V 3 17 U2 74LS244 CLOCK (RB6, pin 12) 3 11 12 Resistors: 1/4 watt, 5% ... | Original |
8 pages, |
1N4148 2N3904 2N3906 74LS244 74ls244 data sheet 74LS244 uses and functions AN589 LM340-5 LS244 PIC16C84 PIC16C84 MICROCHIP DATA BOOK DS30189 eeprom programmer schematic schematic circuit for bios programer AN589 abstract |
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| Abstract: PC87310 PC87310 is bidirectional and the control of data transfer direction is done by the POE pin In the PC , of the board configuration information schematics a board floor plan and a listing of the available , Configuration pin is associated with a bit in the Configuration Register The logic state on the CRPE pin , Configuration Register bit 5 cannot be controlled via external hardware and always resets to the enabled (0 , switches and jumpers SOFTWARE CONFIGURATION The Configuration Register on the PC87310 PC87310 (U1) allows all ... | Original |
18 pages, |
AN-676 74LS244 74LS125 motor driver ic 74LS245 NE558 welson PC87310 Saronix xtal series PDF IC 74LS32 datasheet NE-18A swb a12 74LS245 working of IC 74ls244 as buffer p20l8 PC87310 abstract |
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| Abstract: available in the part and their associated pin functions. There are two sections that describe some of the , decoders, Port 92 support, 24/48MHz output option, and the ability to relocate the configuration registers , /GP42 /GP42. nIDE1_OE: IDE1 enable, active low output. Connect to pin 19 of both the high and low byte buffer , nIOROP: IOR output, active low output. Connect to pin 25 of IDE1 and IDE2 header. GP46: General purpose , pin 23 of IDE1 and IDE2 header. GP47: General purpose I/O, input/output. See GPI/O Applications ... | Original |
14 pages, |
two pin ir receiver led SMC34C759 applications of 74LS244 2 two pin ir receiver 26 pins connector l1130 idE 34 pin HEADER connector 74LS244 20 pin XL93C46 74LS244 uses and functions buffer 74LS245 GP77 datasheet abstract |
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| Abstract: Interface FPC Specifications Figure Ba shows exterior views and pin numbering of the user interface FPC. , before using the memory unit. Chapter 1 Handling and Specifications This chapter provides information on the handling of the DSU-FR-20/30 DSU-FR-20/30 Emulator, and describes its specifications. Read this chapter before using the emulator, and check your unit against the specifications. Chapter 2 Connections This , CONTENTS CHAPTER1 Handling and Specifications ... | Original |
45 pages, |
MB2197-90 FH10A 74LS244 10BASE2 2pin connector CM71-00402-1E DSU-FR20/30 MB2197-01 CM71-00402-1E abstract |
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| Abstract: configuration, while Lattice/VantisPROTM supports the use of the TRST pin and ENABLE pin, it is not a , compliance, the BSCAN pin must be low. When this pin is high, the TAP controller pins are disabled and the , be low. When this pin is high, the TAP controller pins are disabled and the functional dedicated , controller pins are disabled, the device enters ISP programming mode and the I/O pins tri-state. The TOE pin , controller pins are disabled, the device enters ISP programming mode and the I/O pins tri-state. The TOE pin ... | Original |
6 pages, |
Vantis ISP cable ispLSI 8000V MACH355 MACH4-128 MACH445 MACH465 mach-355 74HC244 nec 1000EA 1000EA abstract |
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| Abstract: reset pin, TRST, and a program enable pin, ENABLE. This configuration is found on the MACH355 MACH355, MACH445 MACH445 , provided between the ispEN signal and ground when the ispEN or BSCAN device pin is connected to the ispEN , programming mode and the I/O pins tri-state. The TOE pin will disable the functional I/O pins when driven low. , controller pins are disabled, the device enters ISP programming mode and the I/O pins tri-state. The TOE pin , software that controls TOE, tie it to VCC to disable this pin. Figure 6 shows BSCAN/ispEN and TOE tied to ... | Original |
8 pages, |
22LV10 4000B 4A3 enter diode 74LS244 uses and functions EPEN ispMACH 4A Family MACH355 mach-355 mach4-128 FUNCTIONAL APPLICATION OF 74LS244 datasheet abstract |
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| Abstract: describes the configuration of the hardware system incorporating the memory unit and shows the names of its components and the major specifications. 2.1 System Configuration 2.2 Appearance and Part Names 2.3 General Specifications 7 CHAPTER 2 PRODUCT DESCRIPTION 2.1 System Configuration The memory , memory unit and shows the names of its components and the major specifications. Chapter 3 Functions , you use the memory unit as a general-purpose memory module, understand its specifications and follow ... | Original |
45 pages, |
MB2197-90 FR30 FR20 20 pin flat cable connector FCN-215Q050-G/0 CM71-00401-1E CM71-00401-1E abstract |
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| Abstract | Saved from | Date Saved | File Size | Type | Download |
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| is connected to 5V supply voltage through a jumper between pins 57 and 58. To connect another voltage source, first remove this jumper and then feed pin 58 with the new VLCD voltage. 3. For the Starter Kit board diagram on page 11). NOTE: The PA5, PA6, PA7 and RESET pins are used to perform programming disconnected, you can supply it through pins 14 and 16 of the connector, as long as the total load current does programming tool. OSCin is located on the application board, and must be directly connected to Pin 5 on the 16 www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/5745.htm |
STMicroelectronics | 02/04/1999 | 69.28 Kb | HTM | 5745.htm |
| mounted on PCB at XT1, C5 and C6 locations. Signal Pin Number Pin Number Signal 5V supply (1) 1 2 5V input pin is connected to 5V supply voltage through a jumper between pins 57 and 58. To connect another voltage source, first remove this jumper and then feed pin 58 with the new VLCD voltage. 3. For the can supply it through pins 14 and 16 of the connector, as long as the total load current does not programming tool. OSCin is located on the application board, and must be directly connected to Pin 5 on the www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/5745-v1.htm |
STMicroelectronics | 20/10/2000 | 77.38 Kb | HTM | 5745-v1.htm |
| is mounted on PCB at XT1, C5 and C6 locations. Signal Pin Number Pin Number Signal 5V supply input pin is connected to 5V supply voltage through a jumper between pins 57 and 58. To connect another voltage source, first remove this jumper and then feed pin 58 with the new VLCD voltage. 3 supported by the WGDB6 simula- tor. w The pins: NMI, PA0, PA1 and PA2 on the ST62T40B ST62T40B ST62T40B ST62T40B microcontroller board diagram on page 11). NOTE: The PA5, PA6, PA7 and RESET pins are used to perform programming www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/5745-v2.htm |
STMicroelectronics | 11/01/2000 | 71.16 Kb | HTM | 5745-v2.htm |
| is mounted on PCB at XT1, C5 and C6 locations. Signal Pin Number Pin Number Signal 5V supply input pin is connected to 5V supply voltage through a jumper between pins 57 and 58. To connect another voltage source, first remove this jumper and then feed pin 58 with the new VLCD voltage. 3 supported by the WGDB6 simula- tor. w The pins: NMI, PA0, PA1 and PA2 on the ST62T40B ST62T40B ST62T40B ST62T40B microcontroller board diagram on page 11). NOTE: The PA5, PA6, PA7 and RESET pins are used to perform programming www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/5745-v3.htm |
STMicroelectronics | 25/05/2000 | 71.11 Kb | HTM | 5745-v3.htm |