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Part Manufacturer Description Datasheet BUY
SN74LS192N Texas Instruments Synchronous up/down decade counters with dual clock 16-PDIP 0 to 70 visit Texas Instruments
SN74LS192N-10 Texas Instruments LS SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL DECADE COUNTER, PDIP16 visit Texas Instruments
SN74LS192N-00 Texas Instruments LS SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL DECADE COUNTER, PDIP16 visit Texas Instruments
SN74LS192J-00 Texas Instruments LS SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL DECADE COUNTER, CDIP16 visit Texas Instruments
SN74LS192D Texas Instruments Synchronous up/down decade counters with dual clock 16-SOIC 0 to 70 visit Texas Instruments

74LS192 pins

Catalog Datasheet MFG & Type PDF Document Tags

74LS190 pins

Abstract: 74LS192 PIN diagram CPi MR Oo Qi 02 03 12 13 9 5 4 8 VCC = Pin 14 GND = Pin 7 NC = Pins 1, 2, 3, 6 D124 S4/7493A, 54LS/74LS93 IT 2 3 12 9 8 11 Vcc Pin 5 GND = Pin 10 NC = Pins 4, 6, 7, 13 D127 9310, 93L10, 93S10 , D129 54/74192, 54L8/74LS192, 54/74193, 54LS/74LS193 11 15 1 10 9 A I III PL Po Pi P2 P3 CPU TCu , /Down 54/74192 10 A s 30 30 325 D129 4L,7B,9B 14 Up/Down 54LS/74LS192 10 A s 40 30 85 D129 4L,7B,9B 15
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74LS190 pins 74LS192 PIN diagram 74LS183 TTL 74ls163 74LS192 pins Synchronous 74163 54/7490A 54LS/74LS90 74LS92 S4/74293 54LS/74LS293 93L16

74LS160

Abstract: Synchronous 74163 /74163 54LS/74LS163 54LS/74LS168 54LS/74LS169 54/74192 54LS/74LS192 54/74193 54LS/74LS193 54/74190 , Pin 10 NC = 2, 3, 4, 13 Vcc = Pin 14 GND = Pin 7 NC = Pins 1, 2, 3, 6 D124 54/7493A, 54LS/74LS93 , = Pins 4, 6, 7, 13 Vcc = Pin 14 GND = Pin 7 Vcc = Pin 14 GND = Pin 7 D127 9310, 93L10 , , 54LS/74LS162, 54/74163, 54LS/74LS163 D129 54/74192, 54LS/74LS192, 54/74193, 54LS/74LS193 i 7
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93S16 93S05 74LS160 74192 74LS193 74LS191 pins Fairchild 74190 D129 54LS/74LS160 54LS/74LS161 54LS/74LS192 74LS190 74LS191

74LS183

Abstract: 74LS193 CPi MR Oo Qi 02 03 12 13 9 5 4 8 VCC = Pin 14 GND = Pin 7 NC = Pins 1, 2, 3, 6 D124 S4/7493A, 54LS/74LS93 IT 2 3 12 9 8 11 Vcc Pin 5 GND = Pin 10 NC = Pins 4, 6, 7, 13 D127 9310, 93L10, 93S10 , D129 54/74192, 54L8/74LS192, 54/74193, 54LS/74LS193 11 15 1 10 9 A I III PL Po Pi P2 P3 CPU TCu
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sn 7492 ttl TTL 74293 TTL 7490 54LS TTL 74LS93 74ls90 54LS/74LS196 54LS/74LS197 54L8/74LS192

ic 74192 pin configuration

Abstract: pin diagram of counter ic 74193 be loaded in parallel by activating the asyn chronous parallel load pin. 1 TYPE 74192 74LS192 '193 74LS193 PINS All All 74192, 74193, LS192, LS193 Counters TYPICAL fMAX 32MHz TYPICAL , 34 0.5 0.4 -1 .5 Max V V V V mA mA =m /jA =m#iA mA mA mA 74LS192, '193 UNIT < 0 1 HIGH-level
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ic 74192 pin configuration pin diagram of counter ic 74193 ic 74193 ic 74192 ic 74192 pin diagram 74192 ic N74192N N74LS192N N74193N N74LS193N N74LS193D 1N916

sn 7492 ttl

Abstract: 74293 pin diagram CPi MR Oo Qi 02 03 12 13 9 5 4 8 VCC = Pin 14 GND = Pin 7 NC = Pins 1, 2, 3, 6 D124 S4/7493A, 54LS/74LS93 IT 2 3 12 9 8 11 Vcc Pin 5 GND = Pin 10 NC = Pins 4, 6, 7, 13 D127 9310, 93L10, 93S10 , D129 54/74192, 54L8/74LS192, 54/74193, 54LS/74LS193 11 15 1 10 9 A I III PL Po Pi P2 P3 CPU TCu
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74293 pin diagram TTL 7493A 7493A 74162 74LS93 7490A 54LS/74LS290 54LS/74LS390 54LS/74LS393 54LS/74LS490

74192 pin configuration

Abstract: 74LS192 PIN CONFIGURATION asynchronous parallel load pin. TYPE TYPICAL fâ'žAX TYPICAL SUPPLY CURRENT 74192 32MHz 65mA 74LS192 32MHz , Products Data Manual. INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS DESCRIPTION 74 74LS All Inputs 1ul , unless otherwise noted.) PARAMETER TEST CONDITIONS1 74192, '193 74LS192, '193 UNIT Min Typ2 Max
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74192 pin configuration 74LS192 PIN CONFIGURATION TTL 74192 74192 four bit binary counter 74193 state diagram up counter 74193 pin configuration

74193 pin configuration

Abstract: ic 74192 Specification TYPE TYPICAL fMAX TYPICAL SUPPLY CURRENT 74192 32MHz 65mA 74LS192 32MHz 19mA 74193 32MHz 65 mA , OUTPUT LOADING AND FAN-OUT TABLE PINS DESCRIPTION 74 74LS All Inputs 1 ul 1 LSul All Outputs 10ul , range unless otherwise noted.) PARAMETER TEST CONDITIONS1 74192, '193 74LS192, '193 UNIT Min
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IC 74LS192 pin configuration of 74193 ttl 74193 74 LS 193 Logic DIAGRAM 74193 state diagram 74193 1N3064

CI 74LS90

Abstract: ci 74193 CPi MR Oo Qi 02 03 12 13 9 5 4 8 VCC = Pin 14 GND = Pin 7 NC = Pins 1, 2, 3, 6 D124 S4/7493A, 54LS/74LS93 IT 2 3 12 9 8 11 Vcc Pin 5 GND = Pin 10 NC = Pins 4, 6, 7, 13 D127 9310, 93L10, 93S10 , D129 54/74192, 54L8/74LS192, 54/74193, 54LS/74LS193 11 15 1 10 9 A I III PL Po Pi P2 P3 CPU TCu
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CI 74LS90 ci 74193 ci 74ls193 CI 74196 ci 7492 CI 74176 54S/74S109 54LS/74LS109 54LS/74LS76 54LS/74LS107 54LS/74LS78 93L14

IC 74LS192

Abstract: ic 74193 Signelics Counters Logic Products FEATURES · Synchronous reversible 4-bit binary counting · Asynchronous parallel load · Asynchronous reset (clear) · Expandable without external logic TYPE 74192 74LS192 74193 74LS193 7 4 1 9 2 , 7 4 1 9 3 , LS192, LS193 '192 Presettable BCD Decade Up/Down Counter , OUTPUT LOADING AND FAN-OUT TABLE PINS All All NOTE: W h e re a 7 4 u n it lo a d (ul) is u n d e rs to , -1 .5 Max V V V V mA mA =m¿¿A -m /iA mA mA mA 74LS192, ' 193 UNIT V qh HIGH-level output voltage
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74192 counter of ic 74ls193 74LS193 function table ic 74LS193 pin diagram pin configuration of ic 74192 74LS192 table N74LS19

74LS167

Abstract: F199 transistor Number Comprexityt Cell2 Propagation Delay Max. Number of Signal Pins Output Options Supply ^Voltage , supply and ground pins, 6: Two speed versions, standard and high speed (H-version), available. PACKAGE , between the input and output pins of the circuit. This assures that the computerized layout for the , 74LS183 22 26 F190 74LS190 71 85 F191 74LS191 68 82 F192 74LS192 62 74 F193 74LS193 58 74 F194
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74LS167 74S168 74LS382 74LS396 F199 transistor 74LS514 74LS76A transistor b1100 B-2000 RIT-135 B-240 B-350 B-600 B4100

74191, 74192, 74193 circuit diagram

Abstract: IC 7402, 7404, 7408, 7432, 7400 Function 74LS190 74LS191 74LS192 74LS193 74LS194A 74LS195A 74LS196 74LS197 74LS240 74LS241 74LS244 74LS251 , ., latches, flip-flops, and pins) w ithin Altera EPLD s. Together, these features make it easy to im plem ent , specific chip assignments for flip-flops and pins in the source design files. After partitioning, the
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74191, 74192, 74193 circuit diagram IC 7402, 7404, 7408, 7432, 7400 Truth Table 74161 counter schematic diagram 74161 7408, 7404, 7486, 7432 74244 uses and functions HP400 IC-24 QIC-24

pin diagram of counter ic 74193

Abstract: ic 74192 Product Specification 65mA 32MHz 74193 74192 32MHz 74LS192 '193 74LS193 32MHz 19mA DESCRIPTION The , LOADING AND FAN-OUT TABLE PINS D E S C R IP TIO N 74 74LS All All NOTE: Inputs Outputs 1 ul
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LM 74192 of IC 74193 74ls193 pin diagram 74193 counter pin diagram of ic 74192 pin diagram of 74192

sn 74373

Abstract: SN 74114 74LS175 74LS181 74LS183 74LS190 74LS191 74LS192 74LS193 74LS194A 74LS195A 74LS196A 74LS197 74LS240 74LS241 , (e.g., latches, flip-flops, and pins) within Altera EPLDs. Together, these features make it easy to , control the d esig n 's partitioning b y entering specific chip a ssig nm ents for flip-flops and pins in
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sn 74373 SN 74114 logic diagram of ic 74112 IC 7486 xor 7486 xor IC sn 74377

C350AVB

Abstract: full adder using Multiplexer IC 74150 Cell2 Propagation Delay 4 4 4 4 4 4 ns ns ns ns ns ns Max. Number o f Signal Pins 54 74 80 68 68 52 72 , ns 1.4 ns 1.4 ns 1.4 ns 1.4 ns 1.4 ns 1.4 ns 1.4 ns 1.4 ns 1.4 ns 1.4 ns Max.3 Number o f Signal Pins , = 2, 2-input NAND gate. The values in parenthesis show the maximum number o f signal pins when no , Com plexity1 Cell2 Propagation Delay Max3 Number.of Signal Pins I/O Options Supply4 Voltage Operating5 , Fujitsu. 3: Including 7 RAM Test Pins or 5 ROM Test Pins. PACKAGE OPTIONS Tech nology Dual In-line
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C350AVB full adder using Multiplexer IC 74150 74ls69 MB652xxx T2D 7N IC 74ls147 pin details 37MT7 54L98 54L99 74H101 74H102 74H103

74LS382

Abstract: C1602A Complexly1 Cell2 Propagation Delay Max. Number off Signal Pins I/O Opt Iona Supply3 Voltage Operating4 Temp , Technology Dirrice Name Part Number Complexity1 Cell2 Propagation Delay Max.3 Number of Signal Pins I/O , values In parenthosis show the maximum number of signal pins when no high driving capabfllty (Iql " ss , Signal Pins I/O Optlont Supply3 Voltalo Operating Temp. Ranga C-20000UH MB 600xxx 20160 gates 1.0 ns , F190 74LS190 106 F191H 74LS191 73 F192 74LS192 92 F193 74LS193 82 F194 74LS194A 78 F195 74LS195A
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74LS381 C1602A 74LS08 fan-in 74ls517 74LS556 74LS86 full adder C-15006UM 74LS107 74H108 74LS109A 74LS112A 74LS113

74LS115

Abstract: 74LS273 Diagram. Pin numbers in Logic Diagram are correct, except that legends beside Pins 2, 3, and 4 are , Symbol should have inversion bubbles on complement outputs, pins 2, 6, 10 and 14. Logic Diagram, delete
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74LS115 74LS273 74LS00 QUAD 2-INPUT NAND GATE 74LS189 equivalent 74LS265 74LS93A
Abstract: . 5 1.5 Non-connected pins . . 6 1.6 , pins . 15 1.15 Test circuit 1.16 Drivability of pre-buffers , â  NON-CQNNECTED PINS T -42-11-09 The input pins of unconnected macrocells are automatically , > â'" @ â'" # â'" # FDPC3 CK -KÌ All unconnected pins will be modified as , (3503 0013430 3 â  T E S T PINS T - 42 - l l - o d In the event that Insufficient pins are -
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G01341Q 4TLS03 0G13411 HD14508B HD14510B HD14512B

74LS08 fan-in

Abstract: 74LS398 Common Parallel I/O Pins . . . . . . . . . . . . . . . . . 8-Input Shift/Storage Register with Synchronous Reset and Common I/O Pins . . . . . . . . . 4-Bit Shifter/3-State . . . . . . . . . . . . . . . . , /74LS181 SN54/74LS190 SN54/74LS191 SN54/74LS192 SN54/74LS193 SN54/74LS194A SN54/74LS195A SN54/74LS196 SN54
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74LS398 MC74F579 74LS14 Hex Inverter definition 74LS08 TTL 74ls795 Decade Up/Down counter 3 State 74LS797 SN54/74LS798 SN54/74LS848 81LS95 81LS96 81LS97

billion transformer e 3103 308 30631

Abstract: 74ls219 and number of pins are listed along with the manufacturer's part number and name. The engineer's next
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billion transformer e 3103 308 30631 74ls219 HD46505 motorola mda 962-2 SAA6000 billion transformer e 3140 118 32432 S2000 J24616 J26487 K25582 CH-5404 54070Z
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