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SN74LS138N-10 Texas Instruments LS SERIES, OTHER DECODER/DRIVER, INVERTED OUTPUT, PDIP16 visit Texas Instruments
SN74LS138N-00 Texas Instruments LS SERIES, OTHER DECODER/DRIVER, INVERTED OUTPUT, PDIP16 visit Texas Instruments
SN74LS138J Texas Instruments LS SERIES, OTHER DECODER/DRIVER, INVERTED OUTPUT, CDIP16 visit Texas Instruments
SN74LS138FN Texas Instruments LS SERIES, OTHER DECODER/DRIVER, INVERTED OUTPUT, PQCC20 visit Texas Instruments
SN74LS138FNR Texas Instruments LS SERIES, OTHER DECODER/DRIVER, INVERTED OUTPUT, PQCC20 visit Texas Instruments
SN74LS138J-00 Texas Instruments LS SERIES, OTHER DECODER/DRIVER, INVERTED OUTPUT, CDIP16 visit Texas Instruments

74LS138 decoder

Catalog Datasheet MFG & Type PDF Document Tags

intel 8085 microprocessor

Abstract: 8085 memory organization a 74LS138 decoder and a 74LS373 transparent latch. The 74LS138 is used to generate individual Chip , from the 74LS138 decoder. The display system can be shortened by removing HDSP-211X displays from the , Character Interface to 6808 Microprocessor 2 74LS04 74LS138 DECODER G-1 G-2A G-2B Y4 C Y5 B Y6 A Y7 11 10 9 , the addition of a 74LS138 decoder. The 74LS138 is used to generate individual Chip Enables for each of , 6 11 10 9 7 74LS138 DECODER A B C Y4 G-2B Y5 G-2A Y6 G-1 Y7 74LS273 LATCH 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 2
Hewlett-Packard
Original
intel 8085 microprocessor 8085 memory organization 8085 microprocessor 74LS373 Decoder latch used for 8085 ic 74ls138

8085 microprocessor

Abstract: intel 8085 microprocessor addition of a 74LS138 decoder and a 74LS373 transparent latch. The 74LS138 is used to generate individual , be connected to an unused output from the 74LS138 decoder. The display system can be shortened by , addition of a 74LS138 decoder. Figure 2 shows how the six lower order microprocessor address lines are , 16 19 Y4 Y5 Y6 Y7 74LS138 DECODER 74LS273 LATCH Q0 D0 Q1 D1 D2 Q2 D3 Q3 D4 , CMOS IC consists of an eight byte Character RAM, an 8 bit Flash RAM, a 128 character ASCII decoder, a
Avago Technologies
Original
8085 microprocessor Datasheet 8085 microprocesor ic 74ls138 information intel 8085 interfacing of ram with 8085 8085 clock circuit HDSP-211 5988-5632EN

8085 microprocessor hex code

Abstract: code lock using 8085 microprocessor ddition of a 74LS138 decoder and a 74LS373 transparent latch. The 74LS138 is used to generate individual C , connected to an unused o u tp u t from the 74LS138 decoder. The display system can be shortened by removing , ith the addition of a 74LS138 decoder. The 74LS138 is used to generate individual C hip Enables fo r , consists of an eight byte C haracter RAM, an 8 bit Flash RAM, a 128 character ASCII decoder, a 16 sym bol U , 1 18 13 RST R/W VMA E 74LS00 7 4LS 138 DECODER 4 G -1 G -2 A G -2 B C B A Y
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8085 microprocessor hex code code lock using 8085 microprocessor 8085 hex code 40 pin 8085 8085 hardware reset 74LS007 HDSP211X

block diagram of 74LS138 3 to 8 decoder

Abstract: 74LS138 decoder be updated simultaneously. The interface shown in Figure 12 uses a 74LS138 decoder to decode a set , , simultaneously updating all analog outputs. All the interface schemes shown below use a base address decoder. If blocks of memory are used, the base address decoder can be simplified or eliminated altogether , 74LS139 provides the two-to-four decoder and selects it with the base address. Memory Write (WR) of the microcomputer is connected directly to the WR pin of the DAC811. An 8205 decoder is an alternative to the
Burr-Brown
Original
block diagram of 74LS138 3 to 8 decoder 74LS138 decoder 74LS138 pins DAC811A DAC811AH DAC811BH 12-BIT

74LS138 decoder

Abstract: 8205 decoder converters be updated simultaneously. The interface shown in Figure 12 uses a 74LS138 decoder to decode a set , strobed by WR. WR A15 A4 Base Address Decoder CS WR LDAC NC NB NA A3 0 WR 74LS138 0 DAC811 (2) 0 0 0 , base address decoder. If blocks of memory are used, the base address decoder can be simplified or , decoder and selects it with the base address. Memory Write (WR) of the microcomputer is connected directly to the WR pin of the DAC811. An 8205 decoder is an alternative to the 74LS139. 1M 100k 100k
Burr-Brown
Original
8205 decoder DAC811J 16-BIT

pin for 74LS138

Abstract: 74LS138 decoder converters be updated simultaneously. The interface shown in Figure 12 uses a 74LS138 decoder to decode a set , strobed by WR. WR A15 A4 Base Address Decoder CS WR LDAC NC NB NA A3 0 WR 74LS138 0 DAC811 (2) 0 0 0 , base address decoder. If blocks of memory are used, the base address decoder can be simplified or , decoder and selects it with the base address. Memory Write (WR) of the microcomputer is connected directly to the WR pin of the DAC811. An 8205 decoder is an alternative to the 74LS139. 1M 100k 100k
Burr-Brown
Original
pin for 74LS138 10MSPS DAC811JP DAC811JU DAC811JU/1K DAC811KP DAC811KU

74LS138 3 to 8 decoder notes

Abstract: 74LS138 be updated simultaneously. The interface shown in Figure 12 uses a 74LS138 decoder to decode a set , , simultaneously updating all analog outputs. All the interface schemes shown below use a base address decoder. If blocks of memory are used, the base address decoder can be simplified or eliminated altogether , 74LS139 provides the two-to-four decoder and selects it with the base address. Memory Write (WR) of the microcomputer is connected directly to the WR pin of the DAC811. An 8205 decoder is an alternative to the
Burr-Brown
Original
74LS138 3 to 8 decoder notes DAC811RH pin diagram of ic 74ls139 DAC811SH X0116

74LS138 decoder

Abstract: DAC811AN simultaneously. The interface shown in Figure 12 uses a 74LS138 decoder to decode a set of eight adjacent , , simultaneously updating all analog outputs. All the interface schemes shown below use a base address decoder. If blocks of memory are used, the base address decoder can be simplified or eliminated altogether , provides the two-to-four decoder and selects it with the base address. Memory Write (WR) of the microcomputer is connected directly to the WR pin of the DAC811. An 8205 decoder is an alternative to the
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DAC811AN
Abstract: , simultaneously updating all analog outputs. All the interface schemes shown below use a base address decoder. If blocks of memory are used, the base address decoder can be simplified or eliminated altogether , four address locations. A 74LS139 provides the two-to-four decoder and selects it with the base , 8205 decoder is an alternative to the 74LS139. â BRQWN 8 * ^ 1 Burr-Brown IC Data Bookâ'"Data , several D/A converters be updated simul­ taneously. The interface shown in Figure 12 uses a 74LS138 -
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DAC813 74LS136 DACS13 DAC81

74LS138 decoder

Abstract: 74ls139 decoder pin configuration simultaneously. The interface shown in Figure 12 uses a 74LS138 decoder to decode a set of eight adjacent , interface schemes shown below use a base address decoder. If blocks of memory are used, the base address decoder can be simplified or eliminated altogether. For instance, if half the memory space is unused , 74LS139 provides the two-to-four decoder and selects it with the base address. Memory Write (WR) of the microcomputer is connected directly to the WR pin of the DAC811. An 8205 decoder is an alternative to the
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74ls139 decoder pin configuration 8205 microprocessor ic 74 LS 138 DECODER data sheet

DAC81

Abstract: . The interface shown in Figure 12 uses a 74LS138 decoder to decode a set o f eight adjacent addresses , analog outputs. All the interface schemes shown below use a base address decoder. If blocks of m emory are used, the base address decoder can be simplified or eliminated altogether. For instance, if half , two-to-four decoder and selects it with the base address. M emory W rite (WR) of the microcomputer is connected directly to the W R pin o f the DAC811. An 8205 decoder is an alternative to the 74LS139. B U
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DAC811

Abstract: DAC811A interface shown in Figure 12 uses a 74LS138 decoder to decode a set of eight adjacent addresses, to load , shown below use a base address decoder. If blocks of memory are used, the base address decoder can be , four address locations. A 74LS139 provides the two-to-four decoder and selects it with the base , 8205 decoder is an alternative to the 74LS139. FIGURE 6. Equivalent Resistances. OUTPUT RANGE , Decoder 14 D5 12 D6 D7 10 D8 16 D0 9 D9 DB0 DB1 CS (Chip Select
Burr-Brown
Original

74LSI38

Abstract: 8205 decoder 74LS138 decoder to decode a set of eight adjacent addresses to load the input latches of four DAC811's , below use a base address decoder. If blocks of memory are unused, the base address decoder can be , decoder and selects these with the base address. Memory Write (WR) of the 1/2 74LSI39 microcomputer is connected directly to the WR pin of the DAC8I1. A 8205 decoder is an alternative device to use instead of , needed, thus saving 8 address spaces for other uses. Incorporate Ai into the Base Address Decoder, remove
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74LSI38 MTA 240 DAC811R 0AC811
Abstract: ­ taneously. The interface shown in Figure 12 uses a 74LS138 decoder to decode a set of eight adjacent , , simultaneously updating all analog outputs. All the interface schemes shown below use a base address decoder. If blocks of memory are used, the base address decoder can be simplified or eliminated altogether , two-to-four decoder and selects it with the base address. Memory Write (WR) of the microcomputer is connected directly to the WR pin of the DAC811. An 8205 decoder is an alternative to the 74LS139 -
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002T253

5611B

Abstract: 561-1B such as automatic test systems. The interface shown in Figure 12 uses a 74LS138 decoder to decode a set , below use a base address decoder. If blocks of memory are unused, the base address decoder can be , decoder and selects these with the base address. Memory Write (WR) of the microcomputer is connected directly to the WR pin of the HI-5811. A 8205 decoder is an alternative device to use instead of the , into the Base Address Decoder, remove the inverter, con- nect the common LDAC line to Nc of D/A #4
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HI-5Q11 5611B 561-1B 74LS13S transistor 5B11 HI-5611B h1158 HI-5B11 620C/W

74LS138 decoder

Abstract: converters be updated simultaneously. The interface shown in Figure 12 uses a 74LS138 decoder to decode a set , strobed by WR. WR A15 A4 Base Address Decoder CS WR LDAC NC NB NA A3 0 WR 74LS138 0 DAC811 (2) 0 0 0 , base address decoder. If blocks of memory are used, the base address decoder can be simplified or , decoder and selects it with the base address. Memory Write (WR) of the microcomputer is connected directly to the WR pin of the DAC811. An 8205 decoder is an alternative to the 74LS139. 1M 100k 100k
Burr-Brown
Original

74LS138 decoder

Abstract: 8205 decoder be updated simultaneously. The interface shown in Figure 12 uses a 74LS138 decoder to decode a set , , simultaneously updating all analog outputs. All the interface schemes shown below use a base address decoder. If blocks of memory are used, the base address decoder can be simplified or eliminated altogether , 74LS139 provides the two-to-four decoder and selects it with the base address. Memory Write (WR) of the microcomputer is connected directly to the WR pin of the DAC811. An 8205 decoder is an alternative to the
Burr-Brown
Original
block diagram of 74LS138 1 line to 16 line 74LS138 3 to 8 decoder Pin 74LS138 1 to 8 decoder notes
Abstract: converters be updated simultaneously. The interface shown in Figure 12 uses a 74LS138 decoder to decode a set , strobed by WR. WR A15 A4 Base Address Decoder CS WR LDAC NC NB NA A3 0 WR 74LS138 0 DAC811 (2) 0 0 0 , base address decoder. If blocks of memory are used, the base address decoder can be simplified or , decoder and selects it with the base address. Memory Write (WR) of the microcomputer is connected directly to the WR pin of the DAC811. An 8205 decoder is an alternative to the 74LS139. 1M 100k 100k Burr-Brown
Original

ic marking ACOM

Abstract: dac811ah converters be updated simultaneously. The interface shown in Figure 12 uses a 74LS138 decoder to decode a set , strobed by WR. WR A15 A4 Base Address Decoder CS WR LDAC NC NB NA A3 0 WR 74LS138 0 DAC811 (2) 0 0 0 , base address decoder. If blocks of memory are used, the base address decoder can be simplified or , decoder and selects it with the base address. Memory Write (WR) of the microcomputer is connected directly to the WR pin of the DAC811. An 8205 decoder is an alternative to the 74LS139. 1M 100k 100k
Burr-Brown
Original
ic marking ACOM
Abstract: converters be updated simultaneously. The interface shown in Figure 12 uses a 74LS138 decoder to decode a set , strobed by WR. WR A15 A4 Base Address Decoder CS WR LDAC NC NB NA A3 0 WR 74LS138 0 DAC811 (2) 0 0 0 , base address decoder. If blocks of memory are used, the base address decoder can be simplified or , decoder and selects it with the base address. Memory Write (WR) of the microcomputer is connected directly to the WR pin of the DAC811. An 8205 decoder is an alternative to the 74LS139. 1M 100k 100k Burr-Brown
Original
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