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LTC2756ACG#TRPBF Linear Technology LTC2756 - Serial 18-Bit SoftSpan IOUT DAC; Package: SSOP; Pins: 28; Temperature Range: 0°C to 70°C visit Linear Technology - Now Part of Analog Devices Buy
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74LS138 3 to 8 decoder notes

Catalog Datasheet MFG & Type PDF Document Tags

pin diagram of ic 74ls138

Abstract: 74LS138 pin configuration Signetics 74LS138, S138 Decoders/Demultiplexers 1-Of-8 Decoder/Demultiplexer Product , de vice to a 1-of-32 (5 lines to 32 lines) decoder with just four '1 38 s and one inverter. The , state Operating free-air temperature range 74LS 7.0 -0.5 to +7.0 -3 0 to +1 " 0.5 to +V cc 0 to 70 74S 7.0 -0.5 to +5.5 - 3 0 to +5 -0.5 to + V cc UNIT V V mA V "C RECOMM ENDED OPERATING CONDITIONS , expansion · Ideal for memory chip select decoding · Direct replacement for Intel 3205 TYPE 74LS138 74S138
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pin diagram of ic 74ls138 74LS138 pin configuration ic 74ls138 74LS138 pin diagram 74ls138 function LOGIC OF 74LS138 N74S13BN N74LS138N N74LS138D N74S138D 1N916 1N3064

74ls138 truth table

Abstract: 74LS138 (g) MOTOROLA 1-0F-8 DECODER/ DEMULTIPLEXER The LSTTL/MSI SN54/74LS138 is a high speed 1-of-8 , AND LS TTL DATA SN54/74LS138 FUNCTIONAL DESCRIPTION The LS138 is a high speed 1-of-8 Decoder , decoding. The multiple input enables allow parallel ex pansion to a 1-of-24 decoder using just three LS138 devices or to a 1-of-32 decoder using four LS138s and one inverter. The LS138 is fabricated with the , Effects SN54/74LS138 1-0F-8 DECODER/ DEMULTIPLEXER LOW POWER SCHOTTKY ranimniinfmninm VCC Oo
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74ls138 truth table connection for 74LS138 74 LS 138 DECODER demultiplexer 3 to 8 truth table 74LS138 3 to 8 decoder Pin 74ls138 demultiplexer SN54/74LS138 751B-03 SN54LSXXXJ SN74LSXXXN SN74LSXXXD

74LS138

Abstract: 74LS138 3 to 8 decoder Pin SN54/74LS138 1-OF-8 DECODER/ DEMULTIPLEXER The LSTTL / MSI SN54 / 74LS138 is a high speed 1-of-8 , decoding. The multiple input enables allow parallel expansion to a 1-of-24 decoder using just three LS138 devices or to a 1-of-32 decoder using four LS138s and one inverter. The LS138 is fabricated with the , . · · · · · 1-OF-8 DECODER / DEMULTIPLEXER LOW POWER SCHOTTKY Demultiplexing Capability , = PIN 8 = PIN NUMBERS 6 1 2 3 456 12 3 A0 A1 A2 E O0 O1 O2 O3 O4 O5 O6 O7 15
Motorola
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74LS138 3 to 8 decoder notes pin for 74LS138 Truth table of 1 to 16 demultiplexer TTL 74ls138 of 74LS138 3 to 8 decoder motorola 74ls138

LOGIC OF 74LS138

Abstract: pin for 74LS138 Signetics 74LS138, S138 Decoders/Demultiplexers 1-Of-8 Decoder/Demultiplexer Product , 27 12 ns tPHL Address to output 3 logic levels 39 12 tpLH Propagation delay Waveform 2 18 8 , 16 GND = Pin 8 FUNCTION TABLE inputs outputs e, e2 e3 a0 ai a2 0 1 2 3 4 5 6 7 H X X , Enable to output 3 logic levels 38 11 TEST CIRCUITS AND WAVEFORMS Test Circuit For 74 Totem-Pole , '138 decoder accepts three binary weighted inputs (A0, A), A2) and when enabled, provides eight
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N74S138N 74LS138 pins 74l5138 74l513 74LS LD01

LOGIC OF 74LS138

Abstract: 74LS138 pin configuration Signetics 74LS138, S138 Decoders/Demultiplexers 1-Of-8 Decoder/Demultiplexer Product , -of-32 (5 lines to 32 lines) decoder with just four '138s and one inverter. The device can be used as an , , Hl °2 33 °3 HIÖ 4 70)05 I]0 8 C D 0 4 6 1 0 S *2 OE È, [T È2 U E stl Ö 7Ü S N D []r December , .) 74LS 7.0 -0 .5 to +7.0 - 3 0 to +1 -0 .5 to + V (X 0 to 70 74S 7.0 -0 .5 to +5 .5 - 3 0 to + 5 - 0 .5 , expansion · Ideal for memory chip select decoding · Direct replacement for Intel 3205 TYPE 74LS138 74S138
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74LS138 3 to pin configuration

74LS138 3 to 8 decoder notes

Abstract: 74LS138 DATASHEET SN54/74LS138 1-OF-8 DECODER/ DEMULTIPLEXER The LSTTL / MSI SN54 / 74LS138 is a high speed 1-of-8 , /74LS138 FUNCTIONAL DESCRIPTION The LS138 is a high speed 1-of-8 Decoder/Demultiplexer fabricated with , decoding. The multiple input enables allow parallel expansion to a 1-of-24 decoder using just three LS138 devices or to a 1-of-32 decoder using four LS138s and one inverter. The LS138 is fabricated with the , . · · · · · 1-OF-8 DECODER/ DEMULTIPLEXER LOW POWER SCHOTTKY Demultiplexing Capability
Motorola
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74LS138 DATASHEET FUNCTIONAL APPLICATION OF 74LS138 74LS138 data sheet 74LS138 1 to 8 decoder notes 74LS138 application note LS138 Motorola

block diagram of 74LS138 3 to 8 decoder

Abstract: 74LS138 3 to 8 decoder notes TSL230 and a 74LS138 3 line to 8 line decoder tied to some LED's, we can construct a UV monitor. This , pins to a 74LS138 to display the suggesed SPF on the 8 LED's. Block Diagram: Display TSL230 , battery 16 6 7 9 10 11 12 13 14 15 74LS138 3 +5 1 7 +5 2 6 5 1 1 5 4 MHz 8 33 pF 2 0.1 pF 8 2 4 7 3 TSL230 4 GP3 input 8 freq. out 3 6 4 5 33 pF +5 PIC12C508 0.1 pF © 1998 Microchip
Microchip Technology
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NJM78L05A block diagram of 74LS138 3 to 8 decoder 12C508 block diagram of 74LS138 1 line to 16 line application note PIC12C508 12C508 APPLICATION DS40160A/5

connection diagram of ic 74ls138

Abstract: ic 74ls138 allow parallel expansion to a 1 -of-2 4 decoder u sing just three L S 1 3 8 devices or to a 1-of-32 decoder u sin g four L S 1 3 8 s and one inverter. The L S 1 3 8 is fabricated with the Schottky barrier , MOTOROLA S N S N 5 4 L S 1 3 8 7 4 L S 1 3 8 D E S C R I P T I O N - The L S T T L / M S IS N 5 4 L S / 7 4 L S 1 3 8 is a high speed 1-of-8 Decoder/Demultiplexer. This device is , DEVICES SN54LS/74LS138 F U N C T IO N A L D E S C R I P T I O N - T he L S 1 3 8 is a high speed l
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connection diagram of ic 74ls138

ic 74 LS 138 DECODER

Abstract: IC 74ls138 expansion to a 1-o f-2 4 decoder using ju st three LS 138 devices or to a l-o f- 3 2 decoder using fo u r , th e device to a 1-of-32 , (g) M OTOROLA SN 5 4 /7 4 L S 1 3 8 D E S C R IP T IO N - The L S T T L /M S IS N 5 4 L S , /74LS138 F U N C T IO N A L D E S C R IP T IO N - The LS138 is a high speed 1-of-8 D eco d e r/D em u , AND LS TTL DATA 5 -9 8 SN54/74LS138 GUARANTEED OPERATING RANGES SYMBOL PARAMETER Supply
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ic 74 LS 138 DECODER ic 74 138 DECODER

pin for 74LS138

Abstract: 74LS138 decoder converters be updated simultaneously. The interface shown in Figure 12 uses a 74LS138 decoder to decode a set , 6 Y3 11 Y4 10 A2 A1 A0 3 2 1 Y5 C B A Y6 Y7 FIGURE 12. Interfacing Multiple DAC811s to an 8 , permit interfacing to 4-, 8-, 12-, or 16-bit buses and to handle right-or left-justified data. The 12 , SETTLING TIME(6) (to within ±0.01% of FSR of Final Value; 2k load) For Full Scale Range Change, 20V Range 3 10V Range 3 For 1LSB Change at Major Carry(7) 1 Slew Rate(6) 8 12 ANALOG OUTPUT Voltage Range (±VCC =
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74LS138 decoder DAC811 12-BIT DAC811J DAC811A 10MSPS DAC811AH

block diagram of 74LS138 3 to 8 decoder

Abstract: block diagram of 74LS138 1 line to 16 line E3 R/W E2 DB0 to DB7 74LS138 ADDRESS DECODER 8 4 8 DATA BUS LD DB7 , E1 E3 E2 WR A0 to A2 74LS138 ADDRESS DECODER DATA BUS 8 SOD LD CLK CS0P to , Rev. 2.00 7 MP7651 8 ENABLE DAC NOT USED LD 8 8 4 To 16 Decoder CS3P CS2P , . Internal Chip Address Decoder Plus Logic Interface Rev. 2.00 8 MP7651 ADDRESS BUS A0 to A23 AS , Digital Data Port and Chip Select Decoder FEATURES · 8 Independent 2-Quadrant Multiplying 8-Bit DACs ·
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hp5082 7651 MP7651AS HP5082-2835 MC6800 MC68000 MP7651AN

block diagram of 74LS138 3 to 8 decoder

Abstract: 74LS138 decoder be updated simultaneously. The interface shown in Figure 12 uses a 74LS138 decoder to decode a set , input latch is divided into three 4-bit nibbles to permit interfacing to 4-, 8-, 12-, or 16-bit buses , ) (to within ±0.01% of FSR of Final Value; 2k load) For Full Scale Range Change, 20V Range 3 10V Range 3 For 1LSB Change at Major Carry(7) 1 Slew Rate(6) 8 12 +6.2 +2 UNITS T T T T , . (2) TTL, LSTTL and 54/74 HC compatible. (3) Adjustable to zero with external trim potentiometer. (4
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DAC811BH DAC811JP DAC811KU-1 ic 74ls138 pdf datasheet

74LS138 decoder

Abstract: 8205 decoder converters be updated simultaneously. The interface shown in Figure 12 uses a 74LS138 decoder to decode a set , 6 Y3 11 Y4 10 A2 A1 A0 3 2 1 Y5 C B A Y6 Y7 FIGURE 12. Interfacing Multiple DAC811s to an 8 , permit interfacing to 4-, 8-, 12-, or 16-bit buses and to handle right-or left-justified data. The 12 , SETTLING TIME(6) (to within ±0.01% of FSR of Final Value; 2k load) For Full Scale Range Change, 20V Range 3 10V Range 3 For 1LSB Change at Major Carry(7) 1 Slew Rate(6) 8 12 ANALOG OUTPUT Voltage Range (±VCC =
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8205 decoder 16-BIT
Abstract: Data Sheet PT74HC138 3-to-8 Line Decoder , . PT0127(10/05) Ver:0 1 Data Sheet PT74HC138 3-to-8 Line Decoder , Logic Diagram PT0127(10/05) Ver:0 2 Data Sheet PT74HC138 3-to-8 Line Decoder , PT74HC138 3-to-8 Line Decoder , (10/05) Ver:0 4 Data Sheet PT74HC138 3-to-8 Line Decoder Pericom Technology
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PT74HC138W PT74HC138WE SOIC-16 PT74HC138P PDIP-16 PT74HC138PE
Abstract: LS TTL DN74LS Series DN74LS138 DN74LS138 M 741^)3^ 3 -lin e to 8 -lin e Decoders / Demultiplexers â  Description P-2 D N 74LS138 is a 3-bit decimal to octal decoder/dem ulti­ plexer w ith enable inputs. â  Features â'¢ â'¢ Three types o f enable inputs Q uaternary to , ns 25 38 ns 3 .4 VCC= 4 .7 5 V I ,= - 1 8 m A Icc = 5 . 25 V V 20 Vcc = 5 . , ts/o u tp u ts to delay level O utput Input Delay level (2-stages) Delay level (3-stages) A -
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74LS138 3 to 8 decoder notes

Abstract: 74LS138 be updated simultaneously. The interface shown in Figure 12 uses a 74LS138 decoder to decode a set , divided into three 4-bit nibbles to permit interfacing to 4-, 8-, 12-, or 16-bit buses and to handle , ±1/2 Guaranteed ±10 ±5 ±5 ±1/4 T T T T T ±30 ±10 ±10 ±3/4 SETTLING TIME(6) (to , bipolar offset binary. (2) TTL, LSTTL and 54/74 HC compatible. (3) Adjustable to zero with external trim , parameter. (7) At the major carry, 7FF16 to 80016 and 80016 to 7FF16. (8) Minimum supply voltage required
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DAC811RH pin diagram of ic 74ls139 DAC811SH X0116

pin diagram of ic 74ls138

Abstract: FUNCTIONAL APPLICATION OF 74LS138 Address Bus 8 8 8085 3 8212 E1 +5 A0 to A2 E3 ALE 74LS138 Address Decoder , MP7612 16 16 Address Bus A0 to A15 3 E1 A0 to A2 02 E3 R/W E2 74LS138 Address Decoder MC6800 8 Data Bus 8 DBO to DB7 LD DB7 CLK SDI RST From SYSTEM , VRP VRP ­ + D VRN Q 12 LAT0 XR XE RST + ­ VO7 VRP 8 8 4 to , +85°C MP7612BP 12 ­40 to +85°C 1 0.75 6 PLCC MP7612AP 12 1 8 SOIC
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MP7613 MP7612AS MP7612BS

a1275

Abstract: E2 74LS138 Address Decoder MC6800 8 Data Bus 8 DBO to DB7 LD DB7 CLK SDI , 14 #6;3 #6;24 SOIC â'"40 to +85°C #6;4 MP7610AS 14 #6;8 #6;4 #6;32 PIN , less than 100mA for less than 100µs. APPLICATION NOTES Refer to Section 8 in the 1995 Data , . MC6800 Interface Address Bus 8 8 8085 3 8212 E1 +5 A0 to A2 E3 ALE 74LS138 Address Decoder E2 WR 8 Data Bus SOD LD CLK SDI RST From SYSTEM RESET
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a1275 MP7610 MP7611 P7610

7HC125

Abstract: ic 74ls138 8 8085 8212 ALE 3 A0 to A2 E1 +5 74LS138 E3 ADDRESS DECODER E2 WR , E1 MC6800 02 R/W 74LS138 ADDRESS DECODER E3 E2 DB0 to DB7 8 8 DATA BUS LD , MP7652 4-Channel Voltage Output 15 MHz, Input Bandwidth, 8-Bit Multiplying DACs with 3 , ­ VREF to VOUT Settling Time: 150ns to 8­bit (typ) ­ Voltage Reference Input Bandwidth: 15 MHz · , VREFN3 VREFP4 DAC1 LATCH4 VOUT4 VREFN4 LD 2 to 4 Decoder SDO SDI CLK EN D Q D
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7HC125 MP7652AN MP7652AS ic 74ls138 details

ic marking ACOM

Abstract: dac811ah converters be updated simultaneously. The interface shown in Figure 12 uses a 74LS138 decoder to decode a set , 6 Y3 11 Y4 10 A2 A1 A0 3 2 1 Y5 C B A Y6 Y7 FIGURE 12. Interfacing Multiple DAC811s to an 8 , permit interfacing to 4-, 8-, 12-, or 16-bit buses and to handle right-or left-justified data. The 12 , SETTLING TIME(6) (to within ±0.01% of FSR of Final Value; 2k load) For Full Scale Range Change, 20V Range 3 10V Range 3 For 1LSB Change at Major Carry(7) 1 Slew Rate(6) 8 12 ANALOG OUTPUT Voltage Range (±VCC =
Burr-Brown
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ic marking ACOM
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