74HCT10 |
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Philips Semiconductors
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Triple 3-Input NAND Gate |
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74HCT107 |
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Philips Semiconductors
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Dual JK flip-flop with reset negative-edge trigger |
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74HCT107D |
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Philips Semiconductors
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Dual JK flip-flop with reset negative-edge trigger |
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74HCT107D |
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Unknown
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Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. |
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PDF
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74HCT107D,652 |
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NXP Semiconductors
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Dual JK flip-flop with reset; negative-edge trigger - Description: Dual J-K Flip-Flop with Reset; Negative-Edge Trigger; TTL Enabled ; Fmax: 73 MHz; Logic switching levels: TTL ; Number of pins: 14 ; Output drive capability: +/- 4 mA ; Power dissipation considerations: Low Power ; Propagation delay: 16 ns; Voltage: 4.5-5.5V; Package: SOT108-1 (SO14); Container: Bulk Pack, CECC |
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Original |
PDF
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74HCT107D,653 |
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NXP Semiconductors
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Dual JK flip-flop with reset; negative-edge trigger - Description: Dual J-K Flip-Flop with Reset; Negative-Edge Trigger; TTL Enabled ; Fmax: 73 MHz; Logic switching levels: TTL ; Number of pins: 14 ; Output drive capability: +/- 4 mA ; Power dissipation considerations: Low Power ; Propagation delay: 16 ns; Voltage: 4.5-5.5V; Package: SOT108-1 (SO14); Container: Reel Pack, SMD, 13", CECC |
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PDF
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74HCT107DB |
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Philips Semiconductors
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Dual JK Flip-Flop with Reset, Negative-Edge Trigger |
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Original |
PDF
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74HCT107D-Q100 |
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NXP Semiconductors
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Dual JK flip-flop with reset; negative-edge trigger |
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Original |
PDF
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74HCT107D-Q100J |
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NXP Semiconductors
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74HCT107D-Q100 - 74HCT107D-Q100 - Dual JK flip-flop with reset; negative-edge trigger |
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PDF
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74HCT107D-T |
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Philips Semiconductors
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Dual JK flip-flop with reset negative-edge trigger |
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Original |
PDF
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74HCT107D-T |
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Unknown
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Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. |
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Scan |
PDF
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74HCT107DW |
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Philips Semiconductors
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Dual JK flip-flop with reset, negative-edge trigger |
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Original |
PDF
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74HCT107N |
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Philips Semiconductors
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Dual JK flip-flop with reset negative-edge trigger |
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Original |
PDF
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74HCT107N |
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Unknown
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Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. |
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Scan |
PDF
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74HCT107N,652 |
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NXP Semiconductors
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Dual JK flip-flop with reset; negative-edge trigger - Description: Dual J-K Flip-Flop with Reset; Negative-Edge Trigger; TTL Enabled ; Fmax: 73 MHz; Logic switching levels: TTL ; Number of pins: 14 ; Output drive capability: +/- 4 mA ; Power dissipation considerations: Low Power ; Propagation delay: 16 ns; Voltage: 4.5-5.5V; Package: SOT27-1 (DIP14); Container: Bulk Pack, CECC |
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74HCT107PW |
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Philips Semiconductors
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Dual JK Flip-Flop with Reset, Negative-Edge Trigger |
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Original |
PDF
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74HCT107U |
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Philips Semiconductors
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Dual JK flip-flop with reset negative-edge trigger |
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Original |
PDF
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74HCT109 |
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Philips Semiconductors
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Dual J invertedK flip-flop with set and reset positive-edge trigger |
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Original |
PDF
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74HCT109D |
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Philips Semiconductors
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Dual J Inverted(K)Flip-flop with Set and Reset, Positive-Edge Trigger |
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Original |
PDF
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74HCT109D |
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Unknown
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Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. |
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Scan |
PDF
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