74HC30 74HCT30 JESD22-A114F JESD22-A115-A 74HC30N DIP14 SSOP14 TSSOP14 74HCT30N - Datasheet Archive

 

8-input NAND gate Rev. 04 - 4 May 2010 Product data sheet 1. General description The 74HC30; 74HCT30 are high-speed Si-gate CMOS

 

74HC30 74HC30; 74HCT30 74HCT30 8-input NAND gate Rev. 04 - 4 May 2010 Product data sheet 1. General description The 74HC30 74HC30; 74HCT30 74HCT30 are high-speed Si-gate CMOS devices that comply with JEDEC standard no. 7A. They are pin compatible with Low-power Schottky TTL (LSTTL). The 74HC30 74HC30; 74HCT30 74HCT30 provides a quad 8-input NAND function. 2. Features and benefits Input levels: For 74HC30 74HC30: CMOS level For 74HCT30 74HCT30: TTL level ESD protection: HBM JESD22-A114F JESD22-A114F exceeds 2000 V MM JESD22-A115-A JESD22-A115-A exceeds 200 V Multiple package options Specified from -40 °C to +85 °C and from -40 °C to +125 °C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name 74HC30N 74HC30N Description Version -40 °C to +125 °C DIP14 DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1 -40 °C to +125 °C SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 -40 °C to +125 °C SSOP14 SSOP14 plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1 -40 °C to +125 °C TSSOP14 TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 74HCT30N 74HCT30N 74HC30D 74HC30D 74HCT30D 74HCT30D 74HC30DB 74HC30DB 74HCT30DB 74HCT30DB 74HC30PW 74HC30PW 74HCT30PW 74HCT30PW 74HC30 74HC30; 74HCT30 74HCT30 NXP Semiconductors 8-input NAND gate 4. Functional diagram 1 A 1 2 B 2 3 C 4 D 5 E 6 F 6 11 G 11 12 H 12 3 4 8 Y 8 5 mna489 mna488 Fig 1. & Logic symbol Fig 2. IEC logic symbol A B C D Y E mna490 F G H Fig 3. Logic diagram 74HC_HCT30 HCT30_4 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 04 - 4 May 2010 © NXP B.V. 2010. All rights reserved. 2 of 16 74HC30 74HC30; 74HCT30 74HCT30 NXP Semiconductors 8-input NAND gate 5. Pinning information 5.1 Pinning 74HC30 74HC30 74HCT30 74HCT30 A 1 14 VCC B 2 13 n.c. C 3 12 H D 4 11 G E 5 10 n.c. F 6 9 n.c. GND 7 8 Y 001aal790 Fig 4. Pin configuration DIP14 DIP14, SO14 and (T)SSOP14 SSOP14 5.2 Pin description Table 2. Pin description Symbol Pin Description A 1 data input B 2 data input C 3 data input D 4 data input E 5 data input F 6 data input GND 7 ground (0 V) Y 8 data output n.c. 9 not connected n.c. 10 not connected G 11 data input H 12 data input n.c. 13 not connected VCC 14 supply voltage 74HC_HCT30 HCT30_4 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 04 - 4 May 2010 © NXP B.V. 2010. All rights reserved. 3 of 16 74HC30 74HC30; 74HCT30 74HCT30 NXP Semiconductors 8-input NAND gate 6. Functional description Table 3. Function table[1] Input Output A B C D E F G H Y L X X X X X X X H X L X X X X X X H X X L X X X X X H X X X L X X X X H X X X X L X X X H X X X X X L X X H X X X X X X L X H X X X X X X X L H H H H H H H H H L [1] H = HIGH voltage level; L = LOW voltage level; X = don't care. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage Conditions Min Max Unit -0.5 +7 V IIK input clamping current VI < -0.5 V or VI > VCC + 0.5 V [1] - ±20 mA [1] IOK output clamping current VO < -0.5 V or VO > VCC + 0.5 V - ±20 mA IO output current -0.5 V < VO < VCC + 0.5 V - ±25 mA ICC supply current - 50 mA IGND ground current -50 - mA Tstg storage temperature -65 +150 °C Ptot total power dissipation DIP14 DIP14 package [2] - 750 mW SO14, (T)SSOP14 SSOP14 packages [2] - 500 mW [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For DIP14 DIP14 package: Ptot derates linearly with 12 mW/K above 70 °C. For SO14 package: Ptot derates linearly with 8 mW/K above 70 °C. For (T)SSOP14 SSOP14 packages: Ptot derates linearly with 5.5 mW/K above 60 °C. 74HC_HCT30 HCT30_4 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 04 - 4 May 2010 © NXP B.V. 2010. All rights reserved. 4 of 16 74HC30 74HC30; 74HCT30 74HCT30 NXP Semiconductors 8-input NAND gate 8. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V) Symbol Parameter Conditions 74HC30 74HC30 Min 74HCT30 74HCT30 Typ Max Min Typ Unit Max VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V VI input voltage 0 - VCC 0 - VCC V VO output voltage 0 - VCC 0 - VCC V Tamb ambient temperature -40 - +125 -40 - +125 °C t/V input transition rise and fall rate VCC = 2.0 V - - 625 - - - ns/V VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V VCC = 6.0 V - - 83 - - - ns/V 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter 25 °C Conditions -40 °C to +85 °C -40 °C to +125 °C Unit Min Typ Max Min Max Min Max 74HC30 74HC30 1.2 - 1.5 - 1.5 - V VCC = 4.5 V 3.15 2.4 - 3.15 - 3.15 - V 4.2 3.2 - 4.2 - 4.2 - V LOW-level input voltage VCC = 2.0 V - 0.8 0.5 - 0.5 - 0.5 V VCC = 4.5 V - 2.1 1.35 - 1.35 - 1.35 V - 2.8 1.8 - 1.8 - 1.8 V IO = -20 A; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V 4.4 4.5 - 4.4 - 4.4 - V IO = -20 A; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V IO = -4.0 mA; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V IO = -5.2 mA; VCC = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V IO = 20 A; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V IO = 20 A; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V IO = 20 A; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V IO = 4.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V IO = 5.2 mA; VCC = 6.0 V VOL 1.5 IO = -20 A; VCC = 4.5 V VOH VCC = 2.0 V VCC = 6.0 V VIL HIGH-level input voltage VCC = 6.0 V VIH - 0.16 0.26 - 0.33 - 0.4 V HIGH-level output voltage LOW-level output voltage VI = VIH or VIL VI = VIH or VIL II input leakage current VI = VCC or GND; VCC = 6.0 V - - ±0.1 - ±1 - ±1 A ICC supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V - - 2.0 - 20 - 40 A 74HC_HCT30 HCT30_4 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 04 - 4 May 2010 © NXP B.V. 2010. All rights reserved. 5 of 16 74HC30 74HC30; 74HCT30 74HCT30 NXP Semiconductors 8-input NAND gate Table 6. Static characteristics .continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter 25 °C Conditions -40 °C to +85 °C -40 °C to +125 °C Unit Min CI Max Min Max Min Max - input capacitance Typ 3.5 - - - - - pF 74HCT30 74HCT30 VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - 2.0 - V VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 - 0.8 V VOH HIGH-level output voltage VI = VIH or VIL; VCC = 4.5 V IO = -20 A 4.4 4.5 - 4.4 - 4.4 - V IO = -4.0 mA 3.98 4.32 - 3.84 - 3.7 - V LOW-level output voltage VI = VIH or VIL; VCC = 4.5 V IO = 20 A - 0 0.1 - 0.1 - 0.1 V IO = 4.0 mA - 0.15 0.26 - 0.33 - 0.4 V VOL II input leakage current VI = VCC or GND; VCC = 5.5 V - - ±0.1 - ±1 - ±1 A ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 2.0 - 20 - 40 A ICC additional supply current per input pin; VI = VCC - 2.4 V; IO = 0 A; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V - 60 216 - 275 - 294 A CI input capacitance - 3.5 - - - - - pF 10. Dynamic characteristics Table 7. Dynamic characteristics GND = 0 V; CL = 50 pF; for load circuit see Figure 6. Symbol Parameter 25 °C Conditions -40 °C to +125 °C Unit Min Typ Max Max (85 °C) Max (125 °C) 74HC30 74HC30 tpd propagation delay A, B, C, D, E, F, G, H to Y; see Figure 5 [1] VCC = 2.0 V - 41 130 165 195 ns VCC = 4.5 V - 15 26 33 39 ns VCC = 5.0 V; CL = 15 pF - 12 - - - ns - 12 22 28 33 ns VCC = 2.0 V - 19 75 95 110 ns VCC = 4.5 V - 7 15 19 22 ns VCC = 6.0 V - 6 13 16 19 ns VCC = 6.0 V tt transition time 74HC_HCT30 HCT30_4 Product data sheet see Figure 5 [2] All information provided in this document is subject to legal disclaimers. Rev. 04 - 4 May 2010 © NXP B.V. 2010. All rights reserved. 6 of 16 74HC30 74HC30; 74HCT30 74HCT30 NXP Semiconductors 8-input NAND gate Table 7. Dynamic characteristics .continued GND = 0 V; CL = 50 pF; for load circuit see Figure 6. Symbol Parameter 25 °C Conditions -40 °C to +125 °C Unit Min CPD power dissipation capacitance Typ Max Max (85 °C) Max (125 °C) - 15 - - - pF - 16 28 35 42 ns [3] per package; VI = GND to VCC 74HCT30 74HCT30 [1] propagation delay A, B, C, D, E, F, G, H to Y; see Figure 5 tpd VCC = 4.5 V VCC = 5.0 V; CL = 15 pF power dissipation capacitance CPD [1] 12 - - - ns VCC = 4.5 V; see Figure 5 transition time tt [2] - 7 15 19 22 ns per package; VI = GND to VCC - 1.5 V [3] - 15 - - - pF tpd is the same as tPHL and tPLH. [2] tt is the same as tTHL and tTLH. [3] CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD × VCC2 × fi × N + (CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (CL × VCC2 × fo) = sum of outputs. 11. Waveforms VI A, B, C, D, E, F, G, H input GND VM tPHL VOH tPLH VY VM nY output VOL VX tTHL tTLH 001aal792 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 5. Table 8. Input to output propagation delays Measurement points Type Input Output VM VM VX VY 74HC30 74HC30 0.5VCC 0.5VCC 0.1VCC 0.9VCC 74HCT30 74HCT30 1.3 V 1.3 V 0.1VCC 0.9VCC 74HC_HCT30 HCT30_4 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 04 - 4 May 2010 © NXP B.V. 2010. All rights reserved. 7 of 16 74HC30 74HC30; 74HCT30 74HCT30 NXP Semiconductors 8-input NAND gate VI negative pulse tW 90 % VM VM 10 % GND tr tf tr tf VI 90 % positive pulse GND VM VM 10 % tW VCC G VI VO DUT RT CL 001aah768 Test data is given in Table 9. Definitions for test circuit: RT = termination resistance should be equal to the output impedance Zo of the pulse generator. CL = load capacitance including jig and probe capacitance. Fig 6. Table 9. Test circuit for measuring switching times Test data Type Input Load Test VI tr, tf CL 74HC30 74HC30 VCC 6.0 ns 15 pF, 50 pF tPLH, tPHL 74HCT30 74HCT30 3.0 V 6.0 ns 15 pF, 50 pF tPLH, tPHL 74HC_HCT30 HCT30_4 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 04 - 4 May 2010 © NXP B.V. 2010. All rights reserved. 8 of 16 74HC30 74HC30; 74HCT30 74HCT30 NXP Semiconductors 8-input NAND gate 12. Package outline DIP14 DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1 ME seating plane D A2 A A1 L c e Z w M b1 (e 1) b MH 8 14 pin 1 index E 1 7 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.2 0.51 3.2 1.73 1.13 0.53 0.38 0.36 0.23 19.50 18.55 6.48 6.20 2.54 7.62 3.60 3.05 8.25 7.80 10.0 8.3 0.254 2.2 inches 0.17 0.02 0.13 0.068 0.044 0.021 0.015 0.014 0.009 0.77 0.73 0.26 0.24 0.1 0.3 0.14 0.12 0.32 0.31 0.39 0.33 0.01 0.087 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. REFERENCES OUTLINE VERSION JEDEC JEITA SOT27-1 Fig 7. IEC 050G04 050G04 MO-001 MO-001 SC-501-14 SC-501-14 EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-13 Package outline SOT27-1 (DIP14 DIP14) 74HC_HCT30 HCT30_4 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 04 - 4 May 2010 © NXP B.V. 2010. All rights reserved. 9 of 16 74HC30 74HC30; 74HCT30 74HCT30 NXP Semiconductors 8-input NAND gate SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index Lp 1 L 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.35 0.014 0.0075 0.34 0.16 0.15 0.010 0.057 inches 0.069 0.004 0.049 0.05 0.244 0.039 0.041 0.228 0.016 0.028 0.024 0.01 0.01 0.028 0.004 0.012 o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION JEDEC SOT108-1 Fig 8. IEC 076E06 076E06 MS-012 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Package outline SOT108-1 (SO14) 74HC_HCT30 HCT30_4 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 04 - 4 May 2010 © NXP B.V. 2010. All rights reserved. 10 of 16 74HC30 74HC30; 74HCT30 74HCT30 NXP Semiconductors 8-input NAND gate SSOP14 SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm D SOT337-1 E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index Lp L 7 1 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 6.4 6.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 1.4 0.9 8 o 0 o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT337-1 Fig 9. REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-150 MO-150 Package outline SOT337-1 (SSOP14 SSOP14) 74HC_HCT30 HCT30_4 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 04 - 4 May 2010 © NXP B.V. 2010. All rights reserved. 11 of 16 74HC30 74HC30; 74HCT30 74HCT30 NXP Semiconductors 8-input NAND gate TSSOP14 TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 E D A X c y HE v M A Z 8 14 Q (A 3) A2 A A1 pin 1 index Lp L 1 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.72 0.38 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT402-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-153 MO-153 Fig 10. Package outline SOT402-1 (TSSOP14 TSSOP14) 74HC_HCT30 HCT30_4 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 04 - 4 May 2010 © NXP B.V. 2010. All rights reserved. 12 of 16 74HC30 74HC30; 74HCT30 74HCT30 NXP Semiconductors 8-input NAND gate 13. Abbreviations Table 10. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model LSTTL Low-power Schottky Transistor-Transistor Logic MM Machine Model TTL Transistor-Transistor Logic 14. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74HC_HCT30 HCT30_4 20100504 Product data sheet - 74HC_HCT30 HCT30_3 · The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. · Modifications: Legal texts have been adapted to the new company name where appropriate. 74HC_HCT30 HCT30_3 20100420 Product data sheet - 74HC_HCT30 HCT30_2 74HC_HCT30 HCT30_2 19970829 Product specification - - 74HC_HCT30 HCT30_4 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 04 - 4 May 2010 © NXP B.V. 2010. All rights reserved. 13 of 16 74HC30 74HC30; 74HCT30 74HCT30 NXP Semiconductors 8-input NAND gate 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term `short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft - The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet - A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification - The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 15.3 Disclaimers Limited warranty and liability - Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors' aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes - NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use in automotive applications - This NXP Semiconductors product has been qualified for use in automotive applications. The product is not designed, authorized or warranted to be 74HC_HCT30 HCT30_4 Product data sheet suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications - Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer's sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer's applications and products planned, as well as for the planned application and use of customer's third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer's applications or products, or the application or use by customer's third party customer(s). Customer is responsible for doing all necessary testing for the customer's applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer's third party customer(s). NXP does not accept any liability in this respect. Limiting values - Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale - NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer's general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license - Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. All information provided in this document is subject to legal disclaimers. Rev. 04 - 4 May 2010 © NXP B.V. 2010. All rights reserved. 14 of 16 74HC30 74HC30; 74HCT30 74HCT30 NXP Semiconductors 8-input NAND gate Export control - This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74HC_HCT30 HCT30_4 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 04 - 4 May 2010 © NXP B.V. 2010. All rights reserved. 15 of 16 74HC30 74HC30; 74HCT30 74HCT30 NXP Semiconductors 8-input NAND gate 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 5 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 13 Legal information. . . . . . . . . . . . . . . . . . . . . . . 14 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 14 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Contact information. . . . . . . . . . . . . . . . . . . . . 15 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'. © NXP B.V. 2010. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 4 May 2010 Document identifier: 74HC_HCT30 HCT30_4