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74H 14D

Catalog Datasheet MFG & Type PDF Document Tags

74H 14D

Abstract: PACKAGE INFORMATION # P a c k a g e code of H S - C M O S Logic In the H D 7 4 H C series of H S -C M O S logic, either of plastic D IP and small outline packages can be selected. Fo r y o u r ordering, please refer to the following package code. H D 74H C XXXXP T L P a ck a ge , type O U T L IN E P A C K A G E [Unit: m m(inch), scale: 1) 4 ] FD -14D A (E IA J) 10.06(0.396) 10.5max (0.4l3max) F P -14D N (JED EC) 8.7,5 max (0.344 max) nnnnnnn 8 o * S # 1 6 -
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OCR Scan
Abstract: 1 1 1 1 1 1 1 1 # 1 7#16;4H& #27;6#25;*! A ) 8 . C I G 9 A , )99 ,&-89 ,&-9) ,&8-) ,&8CI 1.30 1 7#16;4H& #27;6#25;*! ) 8 C G A, A) A8 AC AG , #24;(#16;#19;#19;%1#30;4%F4#16;#24;#30;E#16;4!1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 7#16;4H& #27;6#25;*! A , &G 9)&C GA&I,&I C,&G .A&C 8)&G -8&I )C&9 A9&) AA&C .&) ,&A #17;-&I #17;G&8 #17;A-&A #17;AG&) 7#16;4H , #30;#19;1D#24;#4#30; 1#20;34#21;1%#24;9#22;#21;#28;1 #19;E#16;1#29;#22;#16;#29;E#22;#30; Mitsubishi
Original
Abstract: L S / 7 4 L S logic fam ily. â  Logic diagram (1 gate) 14-pin Panaflat package (S0-14D , cu rre n t Ii ±20 mA O u tp u t cu rren t Io ±25 mA M N 74H C 10 Ta = â'" 4 0 ~ + 6 0 t : dissipation M N 74H C 10S S to rag e tem p eratu re range mW Decrease to -
OCR Scan

74HC125M

Abstract: rro w B o d y M 14D 1 4 -L e a d S m a ll O u tlin e P a c k a g e (S O P ), E IA J T Y P E II, 5 .3 m m W id e M M 74HC125M M M 74H C 125SJ M M 74H C 125M TC M TC14 M M 74H C 125N 1 , te g ra te d C irc u it (S O IC ), J E D E C M S -1 2 0 , 0 .1 5 0 â' N a rro w B o d y M M 74H C 126SJ M 14D 1 4 -L e a d S m a ll O u tlin e P a c k a g e (S O P ), E IA J T Y P E II, 5 .3 m m W id e M M 74H C 126M TC M TC14 M M 74H C 126N 1 4 -L e a d T h in S h rin k S m a ll O u
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OCR Scan
MM74HC125/MM74HC126
Abstract: -pin Panaflat package (SO-14D) I] â  Absolute maximum ratings Sym . Ite m U n it R a tin g V , n t Ii ±20 mA I¿ ± 2 5 mA O u tp u t c u rre n t - 0 . 5 - 7 . M N 74H , â'"4 0 â'" + 60"C 275 M N 74H C 4075S mW Pd Decrease to 200mW at the rate o f 3.8mW -
OCR Scan
MN74HC 74HC4075/ 74HC4075S MN74HC4075/MN74HC4075S SO-14D
Abstract: C + D E + FG + HIJ. G NDC 7 14D V c c 13 ⡠J 2D | n D H oD G 9JF 8UX SN 5 4 H 6 2 , conditions SN 54H 62 SN 74H 62 U N IT M IN S u p p l y vo lta g e V|H M IN NOM M AX 5 , (off) U N IT M IN V X = 1 V, V CC = M AX, 'X l o n l SN 74H 62 M AX T a = 0°C v -
OCR Scan
SN54H62 SN74H62 SN54H50/SN74H50 SN54H53/ SN74H53 SN54H55/SN74H55
Abstract: High-Speed CMOS Logic MN74HC Series MN74HC107/MN74HC107S M N 74H C107 MN74HC107S Dual J - K F l i p - F l o p s with Clear B Description P-1 M N 7 4 H C 1 0 7 /M N 7 4 H C 1 0 7 S c , t 14-pin Panaflat package (S0-14D) CLR CLK J K L X X X L H L , 4 0 ~ + 6 0 â'˜C 400 mVV M N 74H C 107 P o w er d issip a tio n D ecrease to 200m W a t , M N 74H C 107S mW Pi, D ecrease to 200m W a t th e rate o f 3 .8 m W /°C Ta = + 6 0 ~ + 8 -
OCR Scan
S0-14D
Abstract: NAND Gate General Description The M M 74H C T00 is a NAND gates fabricated using advanced , to V qq and ground. M M 74H C T devices are intended to interface between TT L and N M OS com , â  High fan out, 10 LS -TTL loads Ordering Code: O rder N um ber Package N um ber M M 74H C T00M M14A M M 74H C T00SJ M14D M M 74H C T00M TC MTC14 M M 74H C T00N N14A , ), EIAJ TYP E II, 5.3m m W ide Package N um ber M 14D 4 * t 0 014 ¡0 ^ 5 6 ) ' -
OCR Scan
MM74HCT00 S-120 S-001

393S

Abstract: M74HC393N The M M 74H C 393 counter circuits contain independent rip ple carry counters and utilize advanced silicon-gate CM OS technology. The M M 74H C 393 contains tw o 4-bit ripple carry binary counters, w hich can , quiescent supply current: 80 j^A m axim um (74H C S eries) Fanout of 10 LS-TTL loads Ordering Code: O rder N um ber MM 74HC393M MM 74H C 393SJ M M 74H C 393M TC M M 74HC393N Package Num ber M14A M14D M , 14A 14-Lead Sm all O utline Package (SO P), EIAJ T Y P E II, 5.3m m W ide Package N um ber M 14D
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OCR Scan
393S M74HC393N 74H 14D MM74HC393

C194

Abstract: SN74HC194 1 / M 3 >C4 > 1 4 /2 4 - SR SER (2) J2)_ 1.4D 3,4D 3,4D 3,4D 3,4D 2,4D (15) (14) (13 , temperature V c c = 4 -5 V Vcc = 6 V Vcc = v Vcc = 6 V 2 1.5 NOM 5 M AX 6 SN 74H C194 MIN 2 1.5 3.1 5 4 .2 0.3 , ±100 8 10 M AX SN 54H C194 MIN 1.9 4 .4 5.9 3.7 5.2 0.1 0.1 0.1 0 .4 0.4 ±1000 160 10 M AX SN 74H C194 , V 6 V 2 V th Hold time, data after CLKÎ 4 .5 V 6 V 80 16 14 80 16 14 100 20 17 SN 54H C194 SN 74H , 13 - 2 5 °C TYP M AX S N 54H C194 MIN 4.2 21 25 225 45 37 220 44 37 110 22 19 | M AX SN 74H C194 MIN
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OCR Scan
SN74HC194 C194 SN54HC194 SN4HC194

hcm 582

Abstract: = tf = 6 ns Notes G E N E R A L D E S C R IP T IO N The 74H C/H CT299 are high-speed Si-gate CMOS , compliance with J E D E C standard no. 7A. The 74H C/H CT299 contain eight edgetriggered D-type flip-flops , H I 0? Te] i/o7 So S1 d sr i/o 0 - I/O , 7 - 13 1.4D 3,40 V < 6 .5 3.4D V < 5 l , MSI -March 1988 579 74HC/HCT299 MSI DC C H A R A C T E R IS T IC S F O R 74H C Fo r , = tf = 6 ns; C L = 50 pF Tam b ( C) 74H C T O > > SYM BO L PA RA M ETER +25 min. 1p h l / T E S
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OCR Scan
hcm 582
Abstract: -pin P anaflat package {SO -14D ) Inpu ts Data P o r t Status GAB GBA A B H H , + 6 0 Ï ; : mW M N 74H C 243 P o w er Decrease to 200mW at the rate o f 8mW/°C Ta = + 6 0 ~ + 8 5 t ' d issip a tio n Ta = - 4 0 ~ ± 6 0 t : 275 M N 74H C 243S mW Pd -
OCR Scan
74HC243/ 74HC243S MN74HC243 MN74HC243S MN74HC243/MN74HC243S

74HC14D

Abstract: 74H 14D dissipation Storage tem pe ra ture range M 74H C 14FP , T a = - 4 0 - M 74H C 14D P , T a = - 4 0 - V cc , M IT S U B IS H I HIGH SPEED CMOS M 74H C 14P /FP /D P HEX S C H M IT T -T R IG G E R IN V E R TE R DESCRIPTION The M74HC14 is a semiconductor integrated circuit con sisting of six Schmitt-trigger inverters. PIN CONFIGURATION (TOP VIEW) HI 75] - INPUT A1 - n ~ Y1 - [~2~ A 2 -[~3~ Y 2 - 1~4~ A3 - r i Y 3 - 1~6~ FEATURES · · · · · · High-speed: 12ns typ. (C L=15pF, V cc
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OCR Scan
74HC14D 74LSTTL 14P2N 14P2P 4000B 74LS14 16PIN
Abstract: Description The M M 74H C 393 counter circuits contain independent rip­ ple carry counters and utilize advanced silicon-gate C M OS technology. The M M 74H C 393 contains tw o 4-bit ripple carry binary , voltage range: 2 - 6 V â  Low input current: -
OCR Scan
Abstract: -pin Panaflat package (SO -14D ) y â'" 1> â'" Pin configuration (top view) "v â  Absolute , atio n mW 275 Ta = - 4 0 ~ + 6 0 t ; M N 74H C 32S V mW D ecrease to 200m W a t th e -
OCR Scan
MN74HC32/MN74HC32S MN74HC32 MN74HC32S
Abstract: diagram (1 gate) 14-pin Panaflat package (SO-14D) Pin configuration (top view) â  Absolute , 74H C 00S mW Decrease to 200mW at the rate of 8mW/° C Ta = + 6 0 ~ + 8 5 â'˜C Decrease to -
OCR Scan
MN74HC00/MN74HC00S MN74HCOO MN74HCOOS
Abstract: -pin Partaflat package (S0-14D) 5 5 = 0 -1 c r^ -> Pin configuration (top view) â'" ~h | V i ,h , 5 t; M N 74H C 21S V Iss â'" â'" 6 5 â'" I-150 £ ±50 mA MN74HC21 -
OCR Scan
MN74HC21S

54HC299

Abstract: texas instruments UFN 450 ) 111) R & 3EN13 O '! 0 - ?M 1 / 3 > C 4 /1 -* /2 4 - n 1.4D 3,4D 0 25 * - -1 , s POST OFFICE BOX 6 5 5 0 1 2 · DALLAS. TEXAS 75 26 5 SN54H C299, SN 74H C299 8-BIT UNIVERSAL , le ct o r data 4 .5 V 6 V 2 5 °C S N 54H C 299 M IN MAX SN 74H C 299 M IN Q ~ im "ö o o 80 16 14 , * SN54H C299, SN 74H C299 8 BIT UNIVERSAL SHIFT/STORAGE REGISTERS WITH DIRECT CLEAR AND 3-STATE OUTPUTS , , SN 74H C299 8 BIT UNIVERSAL SHIFT/STORAGE REGISTERS WITH DIRECT CLEAR AND 3 STATE OUTPUTS sw itching
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OCR Scan
54HC299 texas instruments UFN 450 SN74H 1982-REVISED
Abstract: M M 74H C 08M M M 74H C 08SJ M M 74H C 08M TC M M 74HC08N Package Number Package , -1 2 0 , 0 .1 5 0 â' W id e M 14D 1 4 -L e a d S m a ll O u tlin e P a c k a g e (S O P ), E -
OCR Scan
MM74HC08
Abstract: , 0 .1 5 0 â' N a rro w B o d y M 14D 1 4 -L e a d S m a ll O u tlin e P a c k a g e (S O P ), E IA J T Y P E II, 5 .3 m m W id e M M 74HC132M M M 74H C 132SJ M M 74H C 132M TC M TC14 M M 74H C 132N 1 4 -L e a d T h in S h rin k S m a ll O u tlin e P a c k a g e (T S S O P ), J E -
OCR Scan
MM74HC132
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