74AHC257 74AHCT257 EIA/JESD22-A114-A EIA/JESD22-A115-A EIA/JESD22-C101 - Datasheet Archive

 

DATA SHEET 74AHC257; 74AHCT257 Quad 2-input multiplexer; 3-state Product specification File under Integrated Circuits, IC06 2000

 

INTEGRATED CIRCUITS DATA SHEET 74AHC257 74AHC257; 74AHCT257 74AHCT257 Quad 2-input multiplexer; 3-state Product specification File under Integrated Circuits, IC06 2000 mar 21 Philips Semiconductors Product specification 74AHC257 74AHC257; 74AHCT257 74AHCT257 Quad 2-input multiplexer; 3-state FEATURES DESCRIPTION · ESD protection: HBM EIA/JESD22-A114-A EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A EIA/JESD22-A115-A exceeds 200 V CDM EIA/JESD22-C101 EIA/JESD22-C101 exceeds 1000 V The 74AHC/AHCT257 74AHC/AHCT257 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. · Balanced propagation delays The 74AHC/AHCT257 74AHC/AHCT257 have four identical 2-input multiplexers with 3-state outputs, which select 4 bits of data from two sources and are controlled by a common data select input (S). · All inputs have Schmitt-trigger actions · Non-inverting data path · Inputs accept voltages higher than VCC The data inputs from source 0 (1I0 to 4I0) are selected when input S is LOW and the data inputs from source 1 (1Y1 to 4I1) are selected when S is HIGH. Data appears at the outputs (1Y to 4Y) in true (non-inverting) form from the selected inputs. · For AHC only: operates with CMOS input levels · For AHCT only: operates with TTL input levels · Specified from -40 to +85 and +125 °C. The `257' is the logic implementation of a 4-pole, 2-position switch, where the position of the switch is determined by the logic levels applied to S. The outputs are forced to a high impedance OFF-state when OE is HIGH. FUNCTION TABLE See note 1. INPUT OUTPUT OE S nI0 nI1 nY H X X X Z L H X L L L H X H H L L L X L L L H X H When OE is LOW then the logic equations for the outputs are: 1Y = 1I1 × S + 1I0 × S; 2Y = 2I1 × S + 2I0 × S; 3Y = 3I1 × S + 3I0 × S; 4Y = 4I1 × S + 4I0 × S. The `257' is identical to the `258' but has non-inverting (true) outputs. Note 1. H = HIGH voltage level; L = LOW voltage level; X = don't care. Z = high impedance OFF-state ORDERING INFORMATION PACKAGES TYPE NUMBER 74AHC257D 74AHC257D TEMPERATURE RANGE PINS -40 to +125 °C PACKAGE MATERIAL CODE 16 SO plastic SOT109-1 74AHC257PW 74AHC257PW 16 TSSOP plastic SOT403-1 74AHCT257D 74AHCT257D 16 SO plastic SOT109-1 74AHCT257PW 74AHCT257PW 16 TSSOP plastic SOT403-1 2000 mar 21 2 Philips Semiconductors Product specification 74AHC257 74AHC257; 74AHCT257 74AHCT257 Quad 2-input multiplexer; 3-state QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf 3.0 ns. TYPICAL SYMBOL PARAMETER CONDITIONS UNIT AHC tPHL/tPLH AHCT propagation delay nl0, nI1 to nY CL = 15 pF; VCC = 5 V 2.9 3.7 ns S to nY CL = 15 pF; VCC = 5 V 3.5 5.1 ns VI = VCC or GND 3.0 3.0 pF 4.0 4.0 pF 4 outputs switching via S 45 51 pF 1 output switching via I 15 15 pF CI input capacitance CO output capacitance CPD power dissipation capacitance CL = 50 pF; f = 1 MHz; notes 1 and 2 Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi + (CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; (CL × VCC2 × fo) = sum of outputs; CL = output load capacitance in pF; VCC = supply voltage in Volts. 2. The condition is VI = GND to VCC. PINNING PIN 1 SYMBOL DESCRIPTION S common data select input 2, 5, 11 and 14 1I0 to 4I0 data inputs from source 0 3, 6, 10 and 13 1I1 to 4I1 data inputs from source 1 4, 7, 9 and 12 1Y to 4Y multiplexer outputs 8 GND ground (0 V) 15 OE output enable input (active LOW) 16 VCC DC supply voltage 2000 mar 21 3 Philips Semiconductors Product specification 74AHC257 74AHC257; 74AHCT257 74AHCT257 Quad 2-input multiplexer; 3-state handbook, halfpage 16 VCC S 1 2 1I0 2 15 OE 1I1 3 14 4I0 1Y 4 13 4I1 1 2I0 5 12 4Y 15 11 3I0 2Y 7 5 10 3I1 6 11 10 14 13 OE 2I1 6 3 S 257 handbook, halfpage 1I0 1I1 2I0 2I1 3I0 3I1 4I0 4I1 1Y 2Y 3Y 4Y 4 7 9 12 MNA537 MNA537 GND 8 9 3Y MNA536 MNA536 Fig.1 Pin configuration. Fig.2 Logic symbol. handbook, halfpage handbook, halfpage 1 15 2 3 G1 2 1I0 EN 3 1I1 5 2I0 6 2I1 11 3I0 10 3I1 14 4I0 13 4I1 1 MUX 4 1 5 7 6 11 9 10 14 1Y 2Y SELECTOR 3-STATE MULTIPLEXER OUTPUTS 7 3Y 9 4Y 12 12 13 S Fig.3 IEC logic symbol. OE 1 MNA538 MNA538 2000 mar 21 4 15 Fig.4 Functional diagram. 4 MNA540 MNA540 Philips Semiconductors Product specification 74AHC257 74AHC257; 74AHCT257 74AHCT257 Quad 2-input multiplexer; 3-state handbook, full pagewidth 1I0 1Y 1I1 2I0 2Y 2I1 3I0 3Y 3I1 4I0 4Y 4I1 OE MNA539 MNA539 S Fig.5 Logic diagram. 2000 mar 21 5 Philips Semiconductors Product specification 74AHC257 74AHC257; 74AHCT257 74AHCT257 Quad 2-input multiplexer; 3-state RECOMMENDED OPERATING CONDITIONS 74AHC 74AHC SYMBOL PARAMETER 74AHCT 74AHCT CONDITIONS UNIT MIN. TYP. MAX. MIN. TYP. MAX. 4.5 5.0 5.5 V VCC DC supply voltage 2.0 5.0 5.5 VI input voltage 0 - 5.5 0 - 5.5 V VO output voltage 0 - VCC 0 - VCC V Tamb operating ambient temperature range -40 +25 +85 -40 +25 +85 °C -40 +25 +125 -40 +25 +125 °C VCC = 3.3 V ±0.3 V - - 100 - - - VCC = 5 V ±0.5 V - 20 - - 20 tr,tf (t/V) input rise and fall rates see DC and AC characteristics per device - ns/V LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134); voltages are referenced to GND (ground = 0 V). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VCC DC supply voltage -0.5 +7.0 V VI input voltage range -0.5 +7.0 V IIK DC input diode current VI < -0.5 V; note 1 - -20 mA VO < -0.5 V or VO > VCC + 0.5 V; note 1 IOK DC output diode current - ±20 mA IO DC output source or sink current -0.5 V < VO < VCC + 0.5 V - ±25 mA ICC DC VCC or GND current - ±75 mA Tstg storage temperature range -65 +150 °C PD power dissipation per package - 500 for temperature range: -40 to +125 °C; note 2 Notes 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. For SO packages: above 70 °C the value of PD derates linearly with 8 mW/K. For TSSOP packages: above 60 °C the value of PD derates linearly with 5.5 mW/K. 2000 mar 21 6 mW Philips Semiconductors Product specification 74AHC257 74AHC257; 74AHCT257 74AHCT257 Quad 2-input multiplexer; 3-state DC CHARACTERISTICS 74AHC 74AHC family Over recommended operating conditions; voltage are referenced to GND (ground = 0 V). Tamb (°C) TEST CONDITIONS SYMBOL -40 to +85 25 PARAMETER OTHER VCC (V) MIN. TYP. -40 to +125 UNIT MAX. MIN. MAX. MIN. MAX. VOH HIGH-level output voltage; all outputs VI = VIH or VIL; IO = -50 µA HIGH-level output voltage - - 1.5 - 1.5 - - - 2.1 - 2.1 - 3.85 - - 3.85 - 3.85 - - - 0.5 - 0.5 - 0.5 3.0 LOW-level input voltage 1.5 2.0 HIGH-level input voltage 2.1 - - 0.9 - 0.9 - 0.9 5.5 VIL 2.0 3.0 5.5 VIH - - 1.65 - 1.65 - 1.65 2.0 1.9 2.0 - 1.9 - 1.9 - V V V 2.9 3.0 - 2.9 - 2.9 - 4.4 4.5 - 4.4 - 4.4 - VI = VIH or VIL; IO = -4.0 mA 3.0 2.58 - - 2.48 - 2.40 - VI = VIH or VIL; IO = -8.0 mA 4.5 3.94 - - 3.8 - 3.70 - LOW-level output voltage; all outputs VI = VIH or VIL; IO = 50 µA 2.0 - 0 0.1 - 0.1 - 0.1 3.0 - 0 0.1 - 0.1 - 0.1 4.5 - 0 0.1 - 0.1 - 0.1 LOW-level output voltage VI = VIH or VIL; IO = 4 mA 3.0 - - 0.36 - 0.44 - 0.55 VI = VIH or VIL; IO = 8 mA VOL 3.0 4.5 4.5 - - 0.36 - 0.44 - 0.55 - 1.0 - 2.0 ±2.5 - ±10.0 µA V V V II input leakage current VI = VCC or GND 5.5 - - 0.1 IOZ 3-state output OFF current VI = VIH or VIL; 5.5 VO = VCC or GND - - ±0.25 - ICC quiescent supply current VI = VCC or GND; IO = 0 5.5 - - 4.0 - 40 - 80 µA CI input capacitance - - 3 10 - 10 - 10 pF 2000 mar 21 7 µA Philips Semiconductors Product specification 74AHC257 74AHC257; 74AHCT257 74AHCT257 Quad 2-input multiplexer; 3-state 74AHCT 74AHCT family Over recommended operating conditions; voltage are referenced to GND (ground = 0 V). Tamb (°C) TEST CONDITIONS SYMBOL -40 to +85 25 PARAMETER OTHER VCC (V) -40 to +125 UNIT MIN. TYP. MAX. MIN. MAX. MIN. MAX. VIH HIGH-level input voltage 4.5 to 5.5 2.0 - - 2.0 - 2.0 - V VIL LOW-level input voltage 4.5 to 5.5 - - 0.8 - 0.8 - 0.8 V VOH HIGH-level output voltage; all outputs VI = VIH or VIL; IO = -50 µA 4.5 4.4 4.5 - 4.4 - 4.4 - V HIGH-level output voltage VI = VIH or VIL; IO = -8.0 mA 4.5 3.94 - - 3.8 - 3.70 - V LOW-level output voltage; all outputs VI = VIH or VIL; IO = 50 µA 4.5 - 0 0.1 - 0.1 - 0.1 V LOW-level output voltage VI = VIH or VIL; IO = 8 mA 4.5 - - 0.36 - 0.44 - 0.55 V II input leakage current VI = VIH or VIL 5.5 - - 0.1 - 1.0 - 2.0 µA IOZ 3-state output OFF current VI = VIH or VIL; 5.5 VO = VCC or GND per input pin; other inputs at VCC or GND; IO = 0 - - ±0.25 - ±2.5 - ±10.0 µA ICC quiescent supply current VI = VCC or GND; 5.5 IO = 0 - - 4.0 - 40 - 80 µA ICC additional quiescent supply current per input pin VI = VCC - 2.1 V other inputs at VCC or GND; IO = 0 4.5 to 5.5 - - 1.35 - 1.5 - 1.5 mA CI input capacitance - 3 10 - 10 - 10 pF VOL 2000 mar 21 - 8 Philips Semiconductors Product specification 74AHC257 74AHC257; 74AHCT257 74AHCT257 Quad 2-input multiplexer; 3-state AC CHARACTERISTICS Type 74AHC257 74AHC257 GND = 0 V; tr = tf 3.0 ns. Tamb (°C) TEST CONDITIONS SYMBOL -40 to +85 25 PARAMETER WAVEFORMS CL MIN. -40 to +125 UNIT TYP. MAX. MIN. MAX. MIN. MAX. 15 pF - 4.2 9.3 1.0 11.0 1.0 12.0 ns - 5.2 11.0 1.0 13.0 1.0 14.0 ns - 4.5 10.5 1.0 12.5 1.0 13.5 ns - 5.1 9.5 1.0 11.0 1.0 11.5 ns 50 pF - 6.0 12.8 1.0 14.5 1.0 16.0 ns - 7.4 14.5 1.0 16.5 1.0 18.5 ns - 6.4 14.0 1.0 16.0 1.0 17.5 ns - 7.2 12.0 1.0 13.5 1.0 14.5 ns 15 pF - 2.9 5.9 1.0 7.0 1.0 7.5 ns - 3.5 6.8 1.0 8.0 1.0 8.5 ns - 3.2 6.8 1.0 8.0 1.0 8.5 ns - 3.4 6.5 1.0 7.0 1.0 8.5 ns 50 pF - 4.2 7.9 1.0 9.0 1.0 11.5 ns - 5.0 8.8 1.0 10.0 1.0 12.5 ns - 4.5 8.8 1.0 10.0 1.0 12.5 ns - 4.9 7.9 1.0 9.0 1.0 9.5 ns VCC = 3.0 to 3.6 V; note 1 tPHL/tPLH propagation delay nI0 to nY; nI1 to nY see Figs 6 and 8 propagation delay S to nY tPZH/tPZL 3-state output enable time OE to nY tPHZ/tPLZ 3-state output disable time OE to nY tPHL/tPLH propagation delay nI0 to nY; nI1 to nY see Figs 7 and 8 see Figs 6 and 8 propagation delay S to nY tPZH/tPZL 3-state output enable time OE to nY tPHZ/tPLZ see Figs 7 and 8 3-state output disable time OE to nY VCC = 4.5 to 5.5 V; note 2 tPHL/tPLH propagation delay nI0 to nY; nI1 to nY see Figs 6 and 8 propagation delay S to nY tPZH/tPZL 3-state output enable time OE to nY tPHZ/tPLZ 3-state output disable time OE to nY tPHL/tPLH propagation delay nI0 to nY; nI1 to nY see Figs 7 and 8 see Figs 6 and 8 propagation delay S to nY tPZH/tPZL 3-state output enable time OE to nY tPHZ/tPLZ 3-state output disable time OE to nY see Figs 7 and 8 Notes 1. Typical values at VCC = 3.3 V. 2. Typical values at VCC = 5.0 V. 2000 mar 21 9 Philips Semiconductors Product specification Quad 2-input multiplexer; 3-state 74AHC257 74AHC257; 74AHCT257 74AHCT257 Type 74AHCT257 74AHCT257 GND = 0 V; tr = tf 3.0 ns. TEST CONDITIONS SYMBOL PARAMETER WAVEFORM S Tamb (°C) -40 to +85 25 CL MIN. -40 to +125 UNIT TYP. MAX. MIN. MAX. MIN. MAX. 15 pF - 3.7 6.5 1.0 8.0 1.0 9.0 ns - 5.1 9.0 1.0 10.5 1.0 11.5 ns - 3.9 8.0 1.0 9.0 1.0 10.0 ns - 4.5 7.5 1.0 8.0 1.0 8.5 ns 50 pF - 4.9 8.5 1.0 10.0 1.0 11.0 ns - 6.4 10.5 1.0 12.5 1.0 13.5 ns - 5.1 10.0 1.0 11.0 1.0 12.0 ns - 6.5 9.5 1.0 10.5 1.0 11.5 ns VCC = 4.5 to 5.5 V; note 1 tPHL/tPLH propagation delay nI0 to nY; nI1 to nY see Figs 6 and 8 propagation delay S to nY tPZH/tPZL 3-state output enable time OE to nY tPHZ/tPLZ 3-state output disable time OE to nY tPHL/tPLH propagation delay nI0 to nY; nI1 to nY see Figs 7 and 8 see Figs 6 and 8 propagation delay S to nY see Figs 7 and 8 tPZH/tPZL 3-state output enable time OE to nY tPHZ/tPLZ 3-state output disable time OE to nY Note 1. Typical values at VCC = 5.0 V. AC WAVEFORMS VI handbook, halfpage nI0, nI1, S VM(1) INPUT GND t PHL t PLH VOH VM(1) nY OUTPUT VOL VM(1) INPUT MNA486 MNA486 VM(1) OUTPUT FAMILY VI INPUT REQUIREMENTS AHC GND to VCC 50% VCC 50% VCC AHCT GND to 3.0 V 1.5 V 50% VCC Fig.6 The data inputs (1I0, 1I1) and common data select input (S) to output (nY) propagation delays. 2000 mar 21 10 Philips Semiconductors Product specification Quad 2-input multiplexer; 3-state 74AHC257 74AHC257; 74AHCT257 74AHCT257 VI handbook, full pagewidth VM(1) OE input GND tPLZ output LOW-to-OFF OFF-to-LOW tPZL VCC VM(2) VOL + 0.3 V VOL tPHZ tPZH VOH VOH - 0.3 V output HIGH-to-OFF OFF-to-HIGH VM(2) GND outputs enabled outputs enabled outputs disabled MNA450 MNA450 VM(1) INPUT VM(1) OUTPUT FAMILY VI INPUT REQUIREMENTS AHC GND to VCC 50% VCC 50% VCC AHCT GND to 3.0 V 1.5 V 50% VCC Fig.7 3-state enable and disable times. S1 handbook, full pagewidth VCC PULSE GENERATOR VI 1000 VO D.U.T. CL RT MNA219 MNA219 TEST S1 tPLH/tPHL open tPLZ/tPZL VCC tPHZ/tPZH GND Fig.8 Load circuitry for switching times. 2000 mar 21 11 VCC open GND Philips Semiconductors Product specification 74AHC257 74AHC257; 74AHCT257 74AHCT257 Quad 2-input multiplexer; 3-state PACKAGE OUTLINES SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index Lp 1 L 8 e 0 detail X w M bp 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.069 0.010 0.057 0.004 0.049 0.01 0.019 0.0100 0.39 0.014 0.0075 0.38 0.16 0.15 0.050 0.039 0.016 0.028 0.020 0.01 0.01 0.004 0.028 0.012 inches 0.244 0.041 0.228 Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT109-1 076E07 076E07 MS-012 MS-012 2000 mar 21 EIAJ EUROPEAN PROJECTION ISSUE DATE 97-05-22 99-12-27 12 o 8 0o Philips Semiconductors Product specification 74AHC257 74AHC257; 74AHCT257 74AHCT257 Quad 2-input multiplexer; 3-state TSSOP16 TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 E D A X c y HE v M A Z 9 16 Q (A 3) A2 A A1 pin 1 index Lp L 1 8 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) mm 1.10 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1.0 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.40 0.06 8 0o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 2000 mar 21 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 95-04-04 99-12-27 MO-153 MO-153 13 o Philips Semiconductors Product specification 74AHC257 74AHC257; 74AHCT257 74AHCT257 Quad 2-input multiplexer; 3-state · Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. SOLDERING Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). · For packages with leads on two sides and a pitch (e): ­ larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. ­ smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. · For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should preferable be kept below 230 °C. Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results: 2000 mar 21 14 Philips Semiconductors Product specification 74AHC257 74AHC257; 74AHCT257 74AHCT257 Quad 2-input multiplexer; 3-state Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE REFLOW(1) WAVE BGA, LFBGA, SQFP, TFBGA not suitable suitable(2) HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS not PLCC(3), SO, SOJ suitable suitable suitable suitable not SSOP, TSSOP, VSO suitable not LQFP, QFP, TQFP recommended(3)(4) recommended(5) suitable Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 2000 mar 21 15