74ABT16373 ABT16373 ABT373 74ABT16373CSSC MS48A MO-118 74ABT16373CMTD MTD48 - Datasheet Archive
74ABT16373 16-Bit Transparent D-Type Latch with 3-STATE Outputs General Description Features The ABT16373 contains sixteen
Revised January 1999 74ABT16373 74ABT16373 16-Bit Transparent D-Type Latch with 3-STATE Outputs General Description Features The ABT16373 ABT16373 contains sixteen non-inverting latches with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. The flip-flops appear transparent to the data when the Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup time is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the outputs are in high Z state. s Separate control logic for each byte s 16-bit version of the ABT373 ABT373 s High impedance glitch free bus loading during entire power up and power down cycle s Non-destructive hot insertion capability s Guaranteed latch-up protection Ordering Code: Order Number Package Number 74ABT16373CSSC 74ABT16373CSSC MS48A MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118 MO-118, 0.300" Wide Package Description 74ABT16373CMTD 74ABT16373CMTD MTD48 MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153 MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code. Logic Symbol Connection Diagram Pin Assignment for SSOP and TSSOP Pin Descriptions Pin Names Description OEn Output Enable Input (Active Low) LEn Latch Enable Input D0D15 Data Inputs O0O15 Outputs © 1999 Fairchild Semiconductor Corporation DS011666 DS011666.prf www.fairchildsemi.com 74ABT16373 74ABT16373 16-Bit Transparent D-Type Latch with 3-STATE Outputs March 1994 74ABT16373 74ABT16373 Functional Description Truth Tables The ABT16373 ABT16373 contains sixteen D-type latches with 3STATE standard outputs. The device is byte controlled with each byte functioning identically, but independent of the other. Control pins can be shorted together to obtain full 16-bit operation. The following description applies to each byte. When the Latch Enable (LEn) input is HIGH, data on the Dn enters the latches. In this condition the latches are transparent, i.e., a latch output will change states each time its D input changes. When LEn is LOW, the latches store information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LEn. The 3STATE standard outputs are controlled by the Output Enable (OEn) input. When OEn is LOW, the standard outputs are in the 2-state mode. When OEn is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches. Inputs Outputs LE1 OE1 D0D7 O0O7 Z X H X H L L L H L H H L L X (Previous) LE2 OE2 D8D15 O8O15 X H X Z H L L L H L H H L L X (Previous) Inputs Outputs H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance Previous = previous output prior to HIGH to LOW transition of LE Logic Diagrams www.fairchildsemi.com 2 Storage Temperature (Across Comm Operating Range) -65°C to +150°C Ambient Temperature under Bias -55°C to +125°C -500 mA Other Pins Over Voltage Latchup (I/O) -55°C to +150°C Junction Temperature under Bias -350 mA DC Latchup Source Current: OE Pin 10V -0.5V to +7.0V VCC Pin Potential to Ground Pin Input Voltage (Note 2) -0.5V to +7.0V Input Current (Note 2) -30 mA to +5.0 mA Recommended Operating Conditions Voltage Applied to Any Output -40°C to +85°C Free Air Ambient Temperature in the Disabled or -0.5V to +5.5V Power-Off State -0.5V to VCC in the HIGH State +4.5V to +5.5V Supply Voltage Minimum Input Edge Rate (V/t) Data Input twice the rated IOL (mA) in LOW State (Max) 50 mV/ns Enable Input Current Applied to Output 20 mV/ns Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. DC Electrical Characteristics Symbol Parameter Input HIGH Voltage VIL VCC VCD Output HIGH Voltage Recognized HIGH Signal V Recognized LOW Signal -1.2 Input Clamp Diode Voltage Units V Input LOW Voltage VOH Typ Max 0.8 VIH Min V 2.0 Min Conditions IIN = -18 mA 2.5 IOH = -3 mA 2.0 IOH = -32 mA VOL Output LOW Voltage 0.55 V Min IOL = 64 mA IIH Input HIGH Current 1 µA Max VIN = 2.7V (Note 3) IBVI Input HIGH Current Breakdown Test 7 µA Max VIN = 7.0V IIL Input LOW Current -1 µA Max VIN = 0.5V (Note 3) V 0.0 VIN = VCC 1 -1 VID Input Leakage Test 4.75 VIN = 0.0V IID = 1.9 µA All Other Pins Grounded IOZH Output Leakage Current 10 µA 0 - 5.5V VOUT = 2.7V; OE = 2.0V IOZL Output Leakage Current -10 µA 0 - 5.5V VOUT = 0.5V; OE = 2.0V IOS Output Short-Circuit Current -275 mA Max VOUT = 0.0V ICEX Output High Leakage Current 50 µA Max VOUT = VCC IZZ Bus Drainage Test 100 µA 0.0 VOUT = 5.5V; All Others GND ICCH Power Supply Current 2.0 mA Max All Outputs HIGH ICCL Power Supply Current 62 mA Max All Outputs LOW ICCZ Power Supply Current 2.0 mA Max OE = V CC ICCT Additional ICC/Input Outputs Enabled 2.5 mA Outputs 3-STATE 2.5 mA Outputs 3-STATE 2.5 mA -100 All Others at VCC or GND VI = VCC - 2.1V Max Enable Input VI = VCC - 2.1V Data Input VI = VCC - 2.1V All Others at VCC or GND ICCD Dynamic ICC No Load mA/ (Note 3) 0.15 MHz Max Outputs Open, LE = VCC OE = GND, (Note 4) One Bit Toggling, 50% Duty Cycle Note 3: Guaranteed, but not tested. Note 4: For 8 bits toggling, ICCD < 0.8 mA/MHz. 3 www.fairchildsemi.com 74ABT16373 74ABT16373 Absolute Maximum Ratings(Note 1) 74ABT16373 74ABT16373 AC Electrical Characteristics (SOIC and SSOP Packages) TA = +25°C Symbol VCC = 4.5V to 5.5V CL = 50 pF Parameter TA = -40°C to +85°C VCC = +5.0V CL = 50 pF Max Min tPLH Propagation Delay Min 1.4 Typ 5.6 1.4 5.6 tPHL Dn to On 1.4 5.6 1.4 5.6 tPLH Propagation Delay 1.7 6.0 1.7 6.0 tPHL LE to On 1.7 5.5 1.7 5.5 tPZH Output Enable Time Units Max 1.1 tPHZ Output Disable Time 6.1 1.1 6.1 1.5 tPZL 5.6 1.5 ns 5.6 2.4 7.1 2.4 7.1 1.6 tPLZ ns 6.5 1.6 ns 6.5 ns AC Operating Requirements (SOIC and SSOP Packages) TA = +25°C Symbol VCC = 4.5V to 5.5V CL = 50 pF Parameter TA = -40°C to +85°C VCC = +5.0V CL = 50 pF Min fTOGGLE Typ Max Toggle Max Min Units Max 100 MHz Frequency tS(H) Setup Time, HIGH 1.5 1.5 tS(L) or LOW Dn to LE 1.5 1.5 tH(H) Hold Time, HIGH 1.0 1.0 tH(L) or LOW Dn to LE 1.0 1.0 tW(H) Pulse Width, 3.0 ns 3.0 ns ns LE HIGH Capacitance Symbol Parameter Typ Conditions Units (TA = 25°C) CIN Input Capacitance 5 pF VCC = 0V COUT (Note 5) Output Capacitance 11 pF VCC = 5.0V Note 5: COUT is measured at frequency f = 1 MHz, per MIL-STD-883 MIL-STD-883, Method 3012. www.fairchildsemi.com 4 74ABT16373 74ABT16373 Physical Dimensions inches (millimeters) unless otherwise noted 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118 MO-118, 0.300" Wide Package Number MS48A MS48A 5 www.fairchildsemi.com 74ABT16373 74ABT16373 16-Bit Transparent D-Type Latch with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153 MO-153, 6.1mm Wide Package Number MTD48 MTD48 LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.