NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Part | Manufacturer | Description | Samples | Ordering |
| 748333-9 | TE Connectivity / AMP | Standard Cable Connectors; CONT. HD22 PIN ( AMP ) | 
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| 748333-2 | TE Connectivity / AMP | Standard Cable Connectors; CONTACT, HD22 PIN, 30AU ( AMP ) |
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| 748333-5 | TE Connectivity / AMP | Standard Cable Connectors; CONTACT, HD22 PIN, FLAU ( AMP ) |
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| 748333-4 | TE Connectivity / AMP | Standard Cable Connectors; CONTACT, HD22 PIN, 30AU, CCLP ( AMP ) |
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| 748333-7 | TE Connectivity / AMP | Standard Cable Connectors; CONTACT, HD22 PIN, FLAU, CCLP ( AMP ) |
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| Catalog Datasheet Results | Type | Document Tags |
| Abstract: Signelics Logic Products 7483, LS83A LS83A Adders 4-Bit Full Adder Product Specification FEATURES • , lookahead • See '283 for corner power pin version DESCRIPTION The '83 adds two 4-bit binary words (An , - BIT WORDS) TYPICAL SUPPLY CURRENT (TOTAL) 7483 23ns 66mA 74LS83A 74LS83A 25ns 19mA ORDERING CODE , lIH and -1,6mA l,Ll and a 74LS unit load (LSul) is 20(iA l,H and -0.4mA l|L. PIN CONFIGURATION *4 DI , LOGIC SYMBOL LOGIC SYMBOL (IEEE/IEC) 10 11 • 7 3 4 1 it I I I I I I Vcc - Pin 5 G NO - Pin 12 ... | OCR Scan |
5 pages, |
N74LS83AN pin diagram 7483 ls83a 7483 32 bit full adder 7483 pin diagram binary adder 7483 7483 pin configuration 7483 4 bit binary adder full adder 7483 7483 PIN 7483 adder 7483 7483 TTL adder LS83A LS83A LS83A abstract |
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| Abstract: Signetics 7483, LS83A LS83A Adders 4-Bit Full Adder Product Specification Logic Products FEATURES • , lookahead • See '283 for corner power pin version DESCRIPTION The '83 adds two 4-bit binary words (An , (TWO 8 - BIT WORDS) TYPICAL SUPPLY CURRENT (TOTAL) 7483 23ns 66mA 74LS83A 74LS83A 25ns 19mA ORDERING CODE , |H and -1,6mA l|L, and a 74LS unit load (LSul) is 20(iA l!H and -0.4mA In. PIN CONFIGURATION a4[T , TIe, December 4. 1985 LOGIC SYMBOL LOGIC SYMBOL (IEEE/IEC) 10 11 • 7 3 4 1 1« Vcc - Pin 5 ... | OCR Scan |
5 pages, |
manual do 7483 N7483N N74LS83AD N74LS83AN pin diagram 7483 full adder 7483 7483 4 bit binary full adder Signetics 7483 4-bit adder 7483 adder 7483 input output pins 7483 7483 full adder 7483 Signetics 4-Bit Full Adder LS83A LS83A LS83A abstract |
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| Abstract: TT L/MS I 9383/5483, 7483 4-BIT BINARY FULL ADDER DESCRIPTION - The TTL/MSI 9383/5483,7483 is a , (Ambient) Under Bias Vcc P'n Potential to Ground Pin * Input Voltage (dc) *lnput Current (dc) Voltage , limit or Input Current limit is sufficient to protect the inputs. PIN NAMES A-i^^Bs A2,B2,A4,B4 CIN £2 , B4 Y Y LOGIC SYMBOL 10 11 8 7 3 4 1 16 a, b, a2 b2 a3 b3 a4 b4 c|n 9383/5483,7483 -3 "4 c4 9 6 2 15 14 VCC = Pin 5 GND = Pin 12 CONNECTION DIAGRAM DIP (TOP VIEW) d Ü16 C L c4 L B3 cin L vcc gnd ... | OCR Scan |
5 pages, |
SJ 8227 adder 7483 7483 BINARY ADDER PIN OUT diagram binary adder 7483 4 bit 7483 binary adder Truth Table 7483 7483 truth table 7483 16 bit full adder 7483 32 bit full adder 7483 4 bit binary full adder full adder 7483 7483 4 bit binary adder datasheet abstract |
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| Abstract: -.001 -A- 5.08r.2QQ' TYPICAL 24 3.1 8[0.1 25] 74.83[2.946] 83.31 [3.280] 50 553444-8 31 4-40 UNC-2B 89.97[3.542] 98.43[3.875] 64 553444-5 24 74.83[2.946] 83.31 [3.280] 50 553444-4 17 59.74[2.352 , PIN AREA OVER 1.27//m[.000050] MINIMUM THICK NICKEL UNDERPLATE OVER ENTIRE TERMINAL. RETAINER - , AMP Incorporated Harrisburg, PA 17105-3608 NAME PLUG ASSEMBLY, ACTION PIN, CHAMP-LOK SIZE A2 CAGE ... | OCR Scan |
1 pages, |
datasheet abstract |
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| Abstract: delay from the I/O pin to the PIA. t PIA Altera Corporation Dedicated input pad and buffer delay. t IN represents the time required for a dedicated input pin to drive the input signal into the , Global control delay. The delay from a dedicated input pin to any global control function in a macrocell , tFIN Fast input delay. The delay from the I/O pin to the macrocell register when fast input , output pin after the output buffer's enable control is disabled. tZX1 Output buffer enable delay ... | Original |
12 pages, |
7483 4-bits parallel adder ic 7483 block diagram pin diagram of 7483 7483 parallel adder pin diagram pin diagram for IC 7483 xor ttl 7483 data sheet ic 7483 full adder 7483 TTL 7483 parallel adder 7483 full adder ic 7483 full adder 7483 full adder application notes datasheet abstract |
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| Abstract: from the I/O pin to the PIA. t PIA Altera Corporation Dedicated input pad and buffer delay. t IN represents the time required for a dedicated input pin to drive the input signal into the , Global control delay. The delay from a dedicated input pin to any global control function in a macrocell , Fast input delay. The delay from the I/O pin to the macrocell register when fast input registers are , buffer disable delay. The delay required for high impedance to appear at the output pin after the output ... | Original |
12 pages, |
X030 ttl 7483 FULL ADDER of IC 7483 7483 IC APPLICATIONS 7483 full adder application notes ttl 7483 7483 IC ic 7483 full adder 7483 parallel adder datasheet abstract |
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| Abstract: from the I/O pin to the PIA. In MAX 5000 devices with a single logic array block (LAB), t IO is the delay from the I/O pin to the logic arrays. In Classic devices, t IO is the delay added to t IN. t PIA Altera Corporation The time required for a dedicated input pin to drive the true and , dedicated clock pin to a register's clock input. t LAC Logic array control delay. The AND array delay , disable delay. The delay required for high impedance to appear at the output pin after the output ... | Original |
15 pages, |
for ic 7483 ic 7483 pin diagram pin diagram for IC 7483 7483 full adder epm5130 7483 TTL data sheet ic 7483 ic 7483 adder Datasheet of IC 7483 full adder 7483 datasheet 7483 IC 4 bit full adder of IC 7483 data sheet ic 7483 full adder datasheet abstract |
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| Abstract: Sine Wave Generation Techniques Sine Wave Generation Techniques TL H 7483 Â 1 FIGURE 1 , 7483 RRD-B30M115 RRD-B30M115 Printed in U S A Sine-Wave-Generation Techniques Typical Amplitude Stability , transformer is used to provide voltage gain within a tightly controlled servo TL H 7483 Â 2 TL H 7483 Â , DIV Middle 1V DIV 500 ns DIV Bottom 0 5V DIV 500 ns DIV TL H 7483 Â 4 FIGURE 3 Low-distortion , LS-52 LS-52 All diodes e 1N914 1N914 e low-TC metal-film types TL H 7483 Â 5 FIGURE 4 Generate high-voltage ... | Original |
12 pages, |
FET CONTROLLED WEIN BRIDGE OSCILLATOR Sine Wave Generation Techniques pin configuration of ic 7483 7483 application of ic 7483 ic 7483 specifications 7483 ic pin diagram alternative of LM386 ic 7483 block diagram ic 7483 pin diagram applications of IC 7483 datasheet abstract |
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| Abstract: 1654741 CHAMP Ribbon Style Connectors Revised 1-04 ACTION PIN (Compliant Pin) PCB Connectors ACTION PIN connectors for printed circuit board applications combine the high reliability of the , PIN terminals. They are available in both plug and receptacles in 14, 24, 36, 50 and 64 position , hardware. The design of the ACTION PIN terminal permits insertion into printed circuit boards having , Revised 1-04 ACTION PIN (Compliant Pin) PCB Connectors 1 Input/Output Connectors 1 Position 1 ... | Original |
2 pages, |
champ idc 50 pin data ribbon connector idc 14 pin data ribbon connector 14 pin data ribbon connector datasheet abstract |
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| Abstract: 330 74-83 REC3-xx12SRW/H1 4.5 - 9, 9 - 18, 18 - 36, 36 - 72 12 220 250 75-85 , , 9 - 18, 18 - 36, 36 - 72 � �0 �0 74-83 REC3-xx12DRW/H1 4.5 - 9, 9 - 18, 18 - 36, 36 , 4:1 Package A 3rd angle projection 20.30 32.00 10.20 Pin Connections 3.81 Pin # , , Wide Input 2:1 & 4:1 3rd angle projection Package B 32.00 20.30 Pin Connections 10.20 Pin # Single 1 +Vin +Vin 3.81 2 No Pin ç'™out Com 15.24 0.51 2.06 ... | Original |
3 pages, |
EN-60950-1 217F UL94V-0 UL94V-0 abstract |
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| Abstract | Saved from | Date Saved | File Size | Type | Download |
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| PINLIST,2 (DRAWING,ORCAD.PIN,1-1 (SYM,1 DATA,2,U2 DATA,3,AND2 PIN,NZ1,1-1,5,21,O PIN,C0,1-1,5,23,1 PIN,A1,1-1,5,23,2 ) (SYM,2 DATA,2,U3 DATA,3,AND2 PIN,NZ2,1-1,5,21,O PIN,C0,1-1,5,23,1 PIN,B1,1-1,5,23,2 ) (SYM,3 DATA,2,U4 DATA,3,AND2 PIN,NZ4,1-1,5,21,O PIN,A1,1-1,5,23,1 PIN,B1,1-1,5,23,2 ) (SYM,4 DATA,2,U5 DATA,3,AND2 PIN,NZ5,1-1,5,21,O PIN,C0,1-1,5,23,1 PIN,A1,1-1,5,23,2 ) (SYM,5 DATA,2,U6 DATA,3,AND2 PIN,NZ6,1-1,5,21,O PIN,C0,1-1,5,23,1 PIN,B1,1-1,5,23,2 ) (SYM,6 DATA,2 www.datasheetarchive.com/download/16751784-958120ZC/or4sdt4.zip (X74-83.PIN) |
Xilinx | 05/09/1996 | 611.19 Kb | ZIP | or4sdt4.zip |
| PINLIST,2 (DRAWING,ORCAD.PIN,1-1 (SYM,1 DATA,2,U2 DATA,3,AND2 PIN,NZ1,1-1,5,21,O PIN,C0,1-1,5,23,1 PIN,A1,1-1,5,23,2 ) (SYM,2 DATA,2,U3 DATA,3,AND2 PIN,NZ2,1-1,5,21,O PIN,C0,1-1,5,23,1 PIN,B1,1-1,5,23,2 ) (SYM,3 DATA,2,U4 DATA,3,AND2 PIN,NZ4,1-1,5,21,O PIN,A1,1-1,5,23,1 PIN,B1,1-1,5,23,2 ) (SYM,4 DATA,2,U5 DATA,3,AND2 PIN,NZ5,1-1,5,21,O PIN,C0,1-1,5,23,1 PIN,A1,1-1,5,23,2 ) (SYM,5 DATA,2,U6 DATA,3,AND2 PIN,NZ6,1-1,5,21,O PIN,C0,1-1,5,23,1 PIN,B1,1-1,5,23,2 ) (SYM,6 DATA,2 www.datasheetarchive.com/download/99180585-996482ZC/or4sdt4.zip (X74-83.PIN) |
Xilinx | 09/04/1997 | 611.19 Kb | ZIP | or4sdt4.zip |
| Xilinx Answer #7483 : 2.1i TRCE Spartan\XL: Input hold time using Primary Clock and IFF is non-zero even with delay Primary Clock and IFF is non-zero even with delay Record #7483 ( input Flip-Flop or Latch) even with delay contrary to Spartan Pin-to-Pin Input Parameter Guidelines . End of Record #7483 - Last Modified: 01/04/00 10:05 For the www.datasheetarchive.com/files/xilinx/docs/rp0001c/rp01c90.htm |
Xilinx | 29/02/2000 | 4.48 Kb | HTM | rp01c90.htm |
| * * * *BAS101 BAS101 BAS101 BAS101 * *NXP Semiconductors * *High-voltage switching diodes * * * * * * * * * * * *VRRM = 300V *IFRM = 1A @ tp = 1ms *trr = 50ns * *Package: SOT23 * *Package Pin 1: Anode *Package Pin 2: not connected *Package Pin 3: Cathode * * * *Simulator: SPICE2 * * *# .SUBCKT BAS101 BAS101 BAS101 BAS101 1 2 * * The = 330 + IBV = 0.0001 + RS = 0.63 + CJO = 4.584E-13 584E-13 584E-13 584E-13 + VJ = 0.7483 + M = 0.06257 + FC = 0.5 + TT www.datasheetarchive.com/download/52977079-596978ZC/71536.zip (BAS101.prm) |
NXP | 23/10/2012 | 463.29 Kb | ZIP | 71536.zip |
| * * * *BAS101 BAS101 BAS101 BAS101 * *NXP Semiconductors * *High-voltage switching diodes * * * * * * * * * * * *VRRM = 300V *IFRM = 1A @ tp = 1ms *trr = 50ns * *Package: SOT23 * *Package Pin 1: Anode *Package Pin 2: not connected *Package Pin 3: Cathode * * * *Simulator: SPICE2 * * *# .SUBCKT BAS101 BAS101 BAS101 BAS101 1 2 * * The = 330 + IBV = 0.0001 + RS = 0.63 + CJO = 4.584E-13 584E-13 584E-13 584E-13 + VJ = 0.7483 + M = 0.06257 + FC = 0.5 + TT www.datasheetarchive.com/download/83020311-596964ZC/41738.zip (BAS101.prm) |
NXP | 23/10/2012 | 56.27 Kb | ZIP | 41738.zip |
| 83C748 83C748 83C748 83C748_87C748_3 83C748 83C748 83C748 83C748; 87C748 87C748 87C748 87C748 80C51 80C51 80C51 80C51 8-bit microcontroller family 2K/64 2K/64 2K/64 2K/64 OTP/ROM, low pin count . 80C51 80C51 80C51 80C51 based architecture Small package sizes - 24-pin DIP (300 mil Â"skinny DIPÂ") - 24-pin Shrink Small Outline Package (SSOP) - 28-pin PLCC 87C748 87C748 87C748 87C748 available in erasable quartz lid or one Type Clock Frequency (MHz) I/O pins Category Clock Frequency (MHz) I/O pins www.datasheetarchive.com/files/philips/pip/83c748_87c748_3.html |
Philips | 14/02/2002 | 11.09 Kb | HTML | 83c748_87c748_3.html |
| * * * *BAS21J BAS21J BAS21J BAS21J * *NXP Semiconductors * *Single high-speed switching diode * * * * * * * * * * * *VRRM = 300V *IFRM = 1A @ tp = 0,5ms *trr = 50ns * *Package: SOD323F * *Package Pin 1: Cathode *Package Pin 2: Anode * * * * *Simulator: SPICE2 * * *# .SUBCKT BAS21J BAS21J BAS21J BAS21J 1 2 * * The resistor R1 does not reflect * a physical device. Instead it * improves = 7.219E-9 219E-9 219E-9 219E-9 + N = 2 + BV = 330 + IBV = 0.0001 + RS = 0.63 + CJO = 4.584E-13 584E-13 584E-13 584E-13 + VJ = 0.7483 + M www.datasheetarchive.com/download/52977079-596978ZC/71536.zip (BAS21J.prm) |
NXP | 23/10/2012 | 463.29 Kb | ZIP | 71536.zip |
| * * * *BAS21J BAS21J BAS21J BAS21J * *NXP Semiconductors * *Single high-speed switching diode * * * * * * * * * * * *VRRM = 300V *IFRM = 1A @ tp = 0,5ms *trr = 50ns * *Package: SOD323F * *Package Pin 1: Cathode *Package Pin 2: Anode * * * * *Simulator: SPICE2 * * *# .SUBCKT BAS21J BAS21J BAS21J BAS21J 1 2 * * The resistor R1 does not reflect * a physical device. Instead it * improves = 7.219E-9 219E-9 219E-9 219E-9 + N = 2 + BV = 330 + IBV = 0.0001 + RS = 0.63 + CJO = 4.584E-13 584E-13 584E-13 584E-13 + VJ = 0.7483 + M www.datasheetarchive.com/download/83020311-596964ZC/41738.zip (BAS21J.prm) |
NXP | 23/10/2012 | 56.27 Kb | ZIP | 41738.zip |
| * * * *BAW101 BAW101 BAW101 BAW101 * *NXP Semiconductors * *High voltage double diode * * * * * * * * * * * *VRRM = 300V *IFRM = 625mA @ tp = *trr = 50ns * *Package: SOT143B * *Package Pin 1: Cathode D1 *Package Pin 2: Cathode D2 *Package Pin 3: Anode D2 *Package Pin 4: Anode D1 * * *Simulator: SPICE2 + IS = 7.219E-9 219E-9 219E-9 219E-9 + N = 2 + BV = 310 + IBV = 0.0001 + RS = 0.63 + CJO = 4.584E-13 584E-13 584E-13 584E-13 + VJ = 0.7483 www.datasheetarchive.com/download/52977079-596978ZC/71536.zip (BAW101.prm) |
NXP | 23/10/2012 | 463.29 Kb | ZIP | 71536.zip |
| * * * *BAW101 BAW101 BAW101 BAW101 * *NXP Semiconductors * *High voltage double diode * * * * * * * * * * * *VRRM = 300V *IFRM = 625mA @ tp = *trr = 50ns * *Package: SOT143B * *Package Pin 1: Cathode D1 *Package Pin 2: Cathode D2 *Package Pin 3: Anode D2 *Package Pin 4: Anode D1 * * *Simulator: SPICE2 + IS = 7.219E-9 219E-9 219E-9 219E-9 + N = 2 + BV = 310 + IBV = 0.0001 + RS = 0.63 + CJO = 4.584E-13 584E-13 584E-13 584E-13 + VJ = 0.7483 www.datasheetarchive.com/download/83020311-596964ZC/41738.zip (BAW101.prm) |
NXP | 23/10/2012 | 56.27 Kb | ZIP | 41738.zip |