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CSD17483F4T Texas Instruments 30V, N-Channel FemtoFET™MOSFET 3-PICOSTAR -55 to 150
CSD17483F4R Texas Instruments 30-V, N-Channel NexFET? Power MOSFET 3-PICOSTAR -55 to 150
CSD17483F4 Texas Instruments 30V, N-Channel FemtoFET™MOSFET 3-PICOSTAR -55 to 150
TPS3702CX18DDCR Texas Instruments High-Accuracy, Fixed-Threshold OV/UV Monitor 6-SOT-23-THIN -40 to 125
TMX320LF2407APGE Texas Instruments 16-bit fixed point DSP with Flash 144-LQFP
SN74S157N3 Texas Instruments Quadruple 2-Line To 1-Line Data Selectors/Multiplexers 16-PDIP 0 to 70

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Part : HBL57483IVA Supplier : Hubbell Manufacturer : Newark element14 Stock : - Best Price : $39.68 Price Each : $49.88
Part : HBL57483IV Supplier : Hubbell Manufacturer : Sager Stock : - Best Price : $36.46 Price Each : $41.16
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7483 IC

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: 68.60 Panel Mount B C 46.79 3.2 59.74 3.2 74.83 3.2 Rear A 40.01 52.96 68.58 Panel Mount B C 46.79 3.78 59.74 3.78 74.83 3.78 Front Panel M o u n t - Panel T h ic k n e s s R ange : 1 .0 - 2 .0 m m R ear Panel M o u n t - Panel T h ic k n e s s R ange : 1 .6 m m (1 . 6 - 2 . 4 , Lock No. of Pos. 24 36 50 B 46.79 59.74 74.83 A 55,2 68.2 83.3 Panel Cutout C -
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application of ic 7483 7483 IC APPLICATIONS
Abstract: Timing 3/3 t ASU = ( t IN + t PIA + t LAD ) ­ ( t IN + t PIA + t IC ) + t SU t AH = ( t IN + t PIA + t IC ) ­ ( t IN + t PIA + t LAD ) + t H Clock-to-Output t CO1 , t IN + t PIA + t IC + t RD + ( t OD1 or t OD2 or t OD3 ) Altera Corporation AN94: Understanding MAX 7000 Timing 7483 TTL MAX+PLUS II .rpt 7483 TTL s1 s1 = OUTPUT , : Understanding MAX 7000 Timing 7483 TTL _X tSEXP 7483 s2 s2 _LC019 _EQ023 _X029 _X030 Altera
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ic 7483 7483 ttl data sheet ic 7483 ttl 7483 Datasheet of IC 7483 data sheet 7483 7000EMAX 7000S 7000E LC021 EQ026 EQ024
Abstract: carry lookahead · See '283 for corner power pin version TYPE 7483 7 4LS 83A T Y P IC A L A D D T IM E S (T W O 8 - B IT WORDS) 23ns 25ns T Y P IC A L SU PP LY C U R R E N T (T O T A L ) 66 , Signelics Logic Products Adders 7483, LS83A 4-Bit Full Adder Product Specification , Products P roduct S p ecification Adders LOGIC DIAGRAM 7483 7483, LS83A = ) D - x' i) D - , 0 1 7483, LS83A a 2 a 3 a 4 H b 2 B3 L 0 B4 H 1 2 i H 1 £ -
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7483N ic 7483 pin configuration diagram 74LS83AN circuit diagram for IC 7483 full adder INTERNAL DIAGRAM OF IC 7483 ic 7483 full adder
Abstract: amplitude stabilized phase shift sine wave oscillator which requires one IC package three transistors and , Sine Wave Generation Techniques Sine Wave Generation Techniques TL H 7483 ­ 1 FIGURE 1 , 7483 RRD-B30M115 Printed in U S A Sine-Wave-Generation Techniques Typical Amplitude Stability , circuit of Figure 4 Although complex in appearance this circuit requires just 3 IC packages Here a transformer is used to provide voltage gain within a tightly controlled servo TL H 7483 ­ 2 TL H 7483 ­ National Semiconductor
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ic 7483 pin configuration of IC 7483 pin diagram for IC 7483 applications of IC 7483 7483 comparator ic 7483 pin diagram LM386 AN-263
Abstract: S ignelics 7483, LS83A Adders 4-Bit Full Adder Product Specification Logic Products , carry lookahead · See '283 for comer power pin version TYPE 7483 74LS83A TYPICAL ADD TIMES (TWO 8 - , Signetics Logic Products P roduct S p ecification Adders 7483, LS83A LOGIC DIAGRAM 7483 (13 , Signetics Logic Products P roduct S pecification Adders 7483, LS83A FUNCTION TABLE PINS Logic , 7483, LS83A DC ELECTRICAL CHARACTERISTICS PARAMETER (Over recommended operating free-air -
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pin configuration of ic 7483 for ic 7483 internal circuit full adder 7483 7483 logic diagram 7483 ic pin diagram pin diagram of ic 7483 N7483N N74LS83AN N74LS83AD 1N916 1N3064
Abstract: as preset, clear, and output enable. MAX 7000 devices only. t IC Array clock delay. The delay , , t LPA must be added to the logic array delay (t LAD), the register control delay (t LAC, t IC, t , Combinatorial Logic Combinatorial Logic t ASU = ( t IN + t PIA + t LAD ) ­ ( t IN + t PIA + t IC ) + , t PIA + t IC ) ­ ( t IN + t PIA + t LAD ) + t H Clock-to-Output Delay t CO1 = t IN + t , ACO1 = 630 t IN + t PIA + t IC + t RD + ( t OD1 or t OD2 or t OD3 ) Altera Corporation AN Altera
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7483 parallel adder 7483 4-bits parallel adder ttl 7483 FULL ADDER ic 7483 adder 7483 full adder application notes X030
Abstract: - ~ Housing and Strain Relief Clipâ'" t h e r m o p la s t ic (b la c k ) Terminalsâ'" g o ld o v e r n ic k , v e r n ic k e l p la te o n t e r m in a t in g s id e 1 ,_ c .830 [21 0 8 ] I EMI Shieldâ'" n ic k e l p la te d d ie c a s tin g Loose Piece Preassembled Preassembled , 2.352 59.74 554350-1 2.946 74.83 B 2.205 56.01 554348-1 2.352 59.74 6-32 Hole , 3.20 52.96 2.700 2.946 .149 2.946 .126 74.83 3.78 74.83 3.20 68.58 R et : .014 [ar0 -
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IEEE-488
Abstract: IC Array clock delay. The delay through a macrocell's clock product term to the register's clock , ASU = ( t IN + t LAD ) ­ ( t IN + t IC ) + t SU Classic t ASU = ( t IN + t LAD ) ­ ( t IN + t IC ) + t SU 976 Altera Corporation AN 78: Understanding MAX 5000 & Classic Timing , Combinatorial Logic MAX 5000 t AH = ( t IN + t IC ) ­ ( t IN + t LAD ) + t H Classic t AH = ( t IN + t IC ) ­ ( t IN + t LAD ) + t H Clock-to-Output Delay MAX 5000 t CO1 = Altera
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7483 adder data sheet ic 7483 full adder 7483 IC 4 bit full adder full adder 7483 datasheet 7483 full adder epm5130 EP610 EP610I EP910 EP910I EP1810 LC017
Abstract: enable. t IC Array clock delay. The delay through a macrocell's clock product term to the register , added to the logic array delay (t LAD), the register control delay (t LAC, t IC, t ACL, or t EN), and , ( t IN + t PIA + t IC ) + t SU Asynchronous Hold Time Combinatorial Logic Combinatorial Logic t AH = ( t IN + t PIA + t IC ) ­ ( t IN + t PIA + t LAD ) + t H Clock-to-Output Delay t , Combinatorial Logic t ACO1 = 964 t IN + t PIA + t IC + t RD + ( t OD1 or t OD2 or t OD3 ) Altera Altera
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pin diagram for IC 7483 xor 7483 parallel adder pin diagram pin diagram of 7483 ic 7483 block diagram 7000AE 7000B
Abstract: at the macrocell output. MAX 5000 devices only. t ICS t LAC t IC t CLR t PRE t LAD t RD , Logic Combinatorial Logic MAX 5000 Classic t ASU t ASU = = ( t IN + t LAD ) ­ ( t IN + t IC ) + t SU ( t IN + t LAD ) ­ ( t IN + t IC ) + t SU 642 Altera Corporation AN 78 , Time Combinatorial Logic Combinatorial Logic MAX 5000 Classic t AH t AH = = ( t IN + t IC ) ­ ( t IN + t LAD ) + t H ( t IN + t IC ) ­ ( t IN + t LAD ) + t H Clock-to-Output Delay MAX Altera
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IC 7483 functions classic clock IC 7483 4bit adder LC018
Abstract: devices only. t IC Array clock delay. The delay through a macrocell's clock product term to the , (t LAC, t IC, t ACL, or t EN), and the shared expander delay (t SEXP) paths. MAX 7000 devices only , IN + t PIA + t IC ) + t SU MAX 5000 t ASU = ( t IN + t LAD ) ­ ( t IN + t IC ) + t SU EP610, EP610I, EP910, EP910I, EP1810 t ASU = ( t IN + t LAD ) ­ ( t IN + t IC ) + t SU MAX 7000 t AH = ( t IN + t PIA + t IC ) ­ ( t IN + t PIA + t LAD ) + t H MAX 5000 t AH = Altera
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EPM5192 EPM5128 EPM5064 EPM5032
Abstract: GLOB t IOE t LAC t IC t EN t CLR t PRE t LAD 496 Altera Corporation AN 78 , be added to the logic array delay (t LAD), the register control delay (t LAC, t IC, t ACL, or t EN , Logic t ASU t ASU t ASU = = = ( t IN + t PIA + t LAD ) ­ ( t IN + t PIA + t IC ) + t SU ( t IN + t LAD ) ­ ( t IN + t IC ) + t SU ( t IN + t LAD ) ­ ( t IN + t IC ) + t SU MAX 7000 MAX 5000 EP610, EP610I, EP910, EP910I, EP1810 t AH t AH t AH = = = ( t IN + t PIA + t IC ) ­ ( t IN + t Altera
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Abstract: MODEL SERIES 7 4 8 0 7/8" Diameter 5-Turn W i rewound Precision Potentiometer D i s t r i b u t o r He MODEL 1 /8 " Shaft, 1 /4 " Bushing 7483 7486 1/8" Shaft, Servo 1/4" Shaft, 3/8 " Bushing , . 1800° + 1 5 ° - 0° 2 0.75 oz. 1° 7483 36 oz.-in. N/A .005" .002" .002" .004" .002" 0.9 oz.-in. 0 0 , technologies CORPORATION 133bbl0 0QQ33^S 4Sb 2-107 Model Series 7480 MODEL 7483 (S E R V O M , N 105° M AX U se S p e c ia l Feature Code " F T " to order. M ETR IC C O N V E R S IO N S -
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IC 7486 7486 ic ic 7480 specifications of IC 7486 2606S 2607S 2646S 2647S
Abstract: a ra m e te r is o n ly a v a ila b le in M A X 7 0 0 0 E an d M A X 7 0 0 0 S d e v ic e s. T h is p a ra m e te r is n ot a v a ila b le in 4 4 -p in d e v ic es. 500 Altera Corporation AN , 5000 EP610, EP610I, EP910, EP910I, EP1810 *AC01 *AC01 *AC01 = = t IN+ t PIA + t IC+ t m + t , timing param eters to calculate the delays for real applications. Exam ple 1 : First Bit of 7483 T T L , determ ine the logic implementation of any signal. For example, Figure 6 shows part of a 7483 TTL m -
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Abstract: / / v+ tu o ) - (f//v+ hcs ) + fsu U lN + t L A o ) - ( t / N + t IC s ) + t SU Hold Time , real applications. Example 1: First Bit of 7483 TTL Macrofunction You can analyze the timing delays , signal. For MAX 5000 devices, Figure 5 shows part of a 7483 TTL macrofunction (a 4-bit full adder). The , , Figure 6 shows part of a 7483 TTL macrofunction (a 4-bit full adder). The Report File gives the following , Example 2: Second Bit of 7483 TTL Macrofunction For complex logic that requires expanders (represented as -
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EQ011 EQ010
Abstract: lock-to -O u tp u t D e la y L T MAX 5000 Classic *C 0 1 - l IN + ( IC S + t R D + f OD t , delays for real applications. Example 1: First Bit of 7483 TTL Macrofunction You can analyze the , any signal. For MAX 5000 devices, Figure 5 shows part of a 7483 TTL macrofunction (a 4-bit full adder , For Classic devices, Figure 6 shows part of a 7483 TTL macrofunction (a 4-bit full adder). The Report , LAD + t OD Example 2: Second Bit of 7483 TTL Macrofunction For complex logic that requires -
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Abstract: Counter Frequency tcNT = (R D + {PIA + ^l a d + rS U D e v ic e O p e r a t io n 629 , internal timing parameters to calculate the delays for real applications. Example 1: First Bit of 7483 , determine the logic implementation of any signal. For example, Figure 3 shows part of a 7483 TTL , AN 94: Understanding MAX 7000 Timing Example 2: Second Bit of 7483 TTL Macrofunction For complex , $exp> added to the delay element. The second bit of the 7483 adder macrofunction, s2, requires shared -
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Abstract: fOD7 O p e r a tio n D e v ic e Example 3: Second Bit of 7483 TTL Macrofunction with Parallel , tio n D e v ic e Introduction A ltera d evices p ro v id e p red ictab le device perform an ce , . The A N D array d e la y for the m acrocell register enable. O p e r a tio n D e v ic e ^SEXP , Delay from a Global Clock & Row Output O p e r a tio n Dedicated Input J-. Row I/O D e v ic e CZ , INCOMB + + tnnw ` ROW + LOCAL IC + + inn ` RD + FTD + + ` RO W + + ` IODR + ` IOCOMB + fOD1 Counter -
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7483 a DIN 748-3 EQ003
Abstract: 59.74 1.952 49.58 553444-3 553443-3 50 3.280 83.31 2.946 74.83 2.546 64.67 , 2.085 52.96 2.352 59.74 50 2.700 68.58 2.946 74.83 3.275 83.19 P an el Cutout for , M in im u m o f ,2 7 5 [ 6 . 9 9 ] s lo t d e p th m in u s c u s to m e r b o a r d t h ic k n e s -
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3510-X
Abstract: N IC K E L U N D E R P L A T E OVER ENTIRE TERMINAL. RETAINER - P O LYETHYLEN E, NATURAL , 553443-8 74.83[2.946 8 3 .3 1 [3 .2 8 0] 50 553443-6 31 A 3 4- 40 UNC-2B 74.83 -
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31MAR2000
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