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Part Manufacturer Description Datasheet BUY
SNJ54191W Texas Instruments Synchronous Up/Down Counters With Down/Up Mode Control 16-CFP -55 to 125 visit Texas Instruments
M38510/31509BFA Texas Instruments Synchronous Up/Down Counters With Down/Up Mode Control 16-CFP -55 to 125 visit Texas Instruments
SNJ54LS191W Texas Instruments Synchronous Up/Down Counters With Down/Up Mode Control 16-CFP -55 to 125 visit Texas Instruments
7600901FA Texas Instruments Synchronous Up/Down Counters With Down/Up Mode Control 16-CFP -55 to 125 visit Texas Instruments
JM38510/31509BFA Texas Instruments Synchronous Up/Down Counters With Down/Up Mode Control 16-CFP -55 to 125 visit Texas Instruments
M38510/31508BFA Texas Instruments Synchronous 4-Bit Up/Down Counters (Dual Clock With Clear) 16-CFP -55 to 125 visit Texas Instruments

7476 up down counter

Catalog Datasheet MFG & Type PDF Document Tags

74573

Abstract: 74574 trigger ) Dual 2-Input NAND Gate Up/Down Decade Counter Hex D-Type Flip-Flop 4520 4018 4516 74121 , ( Presetable ) Dual BCD Counter Dual Binary Counter 8-Stage Counter Up/Down Decade Counter 74390 / 4017 , CMOS chips that are readily available over the counter ( from such places as Maplin Electronics in the , 7476 7483 7485 7486 7490 7493 74121 2 of 12 Function Quad 2-Input NAND Gate Quad 2 , -Bit Magnitude Comparator Quad 2-Input XOR Gate Decade Counter 4-Bit Binary Counter Monostable Multivibrator
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CI 7473

Abstract: counter with 7473 7490/5490 Decade counter - 130 18 10 DIP H,P T 7492/5492 Divide-by-12 counter 60 155 18 10 DIP H,P T 7493/5493 Binary counter - 130 18 10 DIP H ,P T 74157/54157 Quad 2-input data selector 9 250 - 10 DIP K,Q T 74180/54180 8-bit odd/even parity generator/checker - 150 - 10 DIP H,P T 74192/54192 Up/down decade counter - 325 32 10 DIP K,Q T 74193/54193 Up/down binary counter 325 32 10 DIP K,Q , ,P T 7476/5476 Dual J-K master-slave with preset and clear - 100 20 10 DIP K,Q T 74107/54107 Dual
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7404 dip

Abstract: 7493 4 bit binary counter H,P T 74192/54192 Up/down decade counter - 325 32 10 DIP K,Q T 74193/54193 Up/down binary counter , D - 85 25 10 DIP H ,P T 7476/5476 Dual J-K master-slave with preset and clear - 100 20 10 DIP K,Q , write inputs 60 275 - - DIP K,Q T 7490/5490 Decade counter - 130 18 10 DIP H,P T 7492/5492 Divide-by-12 counter 60 155 18 10 DIP H,P T 7493/5493 Binary counter - 130 18 10 DIP H ,P T 74157/54157 Quad 2
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FZH115B

Abstract: fzh261 Quad D-type flip flops Synchronous up/down counter binary 74191 Synchronous up/down counter BCD with clear Syn. up/down dual clock counter bin. with clear 74193 4-bit redirectional universal , register 8-bit synchronous binary down counter Hex Schmitt trigger Strobed hex inverter/buffer BCD up/down counter BCD to 7-segment latch/decoder/driver 1 of 16 decod/demult. with input latches Binary up/down counter Dual BCD counter Dual binary counter Programmable 4-bit BCD down counter
Electro Value
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74LS80

Abstract: 74LS198 , Individual Reset B & S et B MODULO UP/DOWN COUNTER CUD41 CUD42 Modulo 16, Up/Down Counter, Expandable Enable G e a r Direct Modulo 16, Up/Down Counter, Expandable w ith Asynchronous Load and G ear , M odulo 16, Binary Up Counter, Expandable Enable Sync G ear M odulo 16, Binary Up C ounter Fast , 4 Bit Bed C ounter (74 L S I6 2 ) Synchronous 4 Bit Bed Counter (74LS162) Synchronous 4 Bit Up/Dow n , Bit Binary Couner Decade Counter/D river (4017) Dual Binary Up C ounter ROgiCO 4-77 4AE » ' 1
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RSC-15 M4017C M4028C 74LS179 74LS198 74LS80 74LS150 74LS94 OAI32 0001L3M TEK-044-9004 NOR03 NAND08 D410L

7476 up down counter

Abstract: 7476 counter /Decade Up/Down Counter General Description The CD4029BC is a presettable up/down counter which counts , binary/ decade is at logical "1", the counter counts in binary, otherwise it counts in decade. Similarly, the counter counts up when the up/down input is at logical "1" and vice versa. A logical "1" preset , logical "0" state when the counter reaches its maximum count in the "up" mode or the minimum count in the , 74LS â  Parallel jam inputs â  Binary or BCD decade up/down counting o o -fi o IO CO 00 O CD CO
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MS-001 7476 up down counter 7476 counter 74LS CD4029BCN CD4029BCSJ CD4029BCWM

7476 counter

Abstract: 7476 counter down /Decade Up/Down Counter General Description The CD4029BC is a presettable up/down counter which counts , binary/ decade is at logical "1", the counter counts in binary, otherwise it counts in decade. Similarly, the counter counts up when the up/down input is at logical "1" and vice versa. A logical "1" preset , logical "0" state when the counter reaches its maximum count in the "up" mode or the minimum count in the , 74LS â  Parallel jam inputs â  Binary or BCD decade up/down counting Ordering Code: Order Number
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7476 counter down ci 7476 M16B M16D MS-013 N16E

INTERNAL DIAGRAM OF IC 7476

Abstract: D4029BC Presettable Binary/Decade Up/Down Counter General Description The C D 4029BC is a presettable up/down , both V qq and Vgs- Presettable Binary/Decade Up/Down Counter Features W ide supply voltage , Presettable Binary/Decade Up/Down Counter Physical Dimensions in c h e s (m illim e te rs ) u n le s s o , counts in decade. Sim ilarly, th e coun ter counts up w hen the up/down input is at logical " 1 " and , L com patibility: o r 1 driving 74LS Parallel jam inputs Binary or BCD decade up/down counting
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INTERNAL DIAGRAM OF IC 7476 D4029BC LD 7476 PS CD4029BC UP DOWN COUNTER

74LS324

Abstract: 7400 TTL 256-Bit PROM, Open Collector Output 64-Bit RAM, 3-State Outputs Synchronous Up/Down BCD Counter Synchronous Up/Down BCD Counter Synchronous Up/Down Binary Counter Synchronous Up/Down Binary Counter Synchronous Up/Down BCD Counter (Dual Clock with Gear) / Synchronous Up/Down BCD Counter (Dual Clock with Clear) Synchronous Up/Down BCD Counter (Dual Clock with Clear) Synchronous Up/Down Binary Counter (Dual Clock with Clear) Synchronous Up/Down Binary Counter , (Dual Clock with Clear) Synchronous Up/Down
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74LS324 7400 TTL 74LS327 7402, 7404, 7408, 7432, 7400 80C96 74251 multiplexer G0G513S 74C00 74H00 74LS00 74S00 74H01
Abstract: fully synchronous 8-stage up/down counter with m ultiplexed 3-STATE I/O ports for bus-oriented a pplica­ tions. All control functions (hold, count up, count dow n, syn­ chronous load) are controlled , R C H II_ D E M IC O N D U C T O R t 74F779 8-Bit Bidirectional Binary Counter with , e m i.c o m 74F779 8-Bit Bidirectional Binary Counter with 3-STATE Outputs February 1998 F /M , utputs A ppear on I/O Lines Parallel Load All Flip-Flops H L L X C ount Up L H L -
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74F779PC 74F779SC DS009593

LM 4017 decade counter driver

Abstract: 74HC7244A WITH ASYNC. CLEAR SYNC. BINARY COUNTER WITH SYNC. CLEAR 4-BIT BINARY UP/DOWN COUNTER SYNC. UP/DOWN , -BIT BINARY COUNTER SYNC. DECADE COUNTER WITH ASYNC. CLEAR SYNC. DECADE COUNTER WITH SYNC. CLEAR BCD UP/DOWN COUNTER SYNC. UP/DOWN DECADE COUNTER DUAL DECADE COUNTER DECADE COUNTER REGISTER (3-STATE) DECADE COUNTER , /_ VCC A O D ® / / LOAD C D SYN. 4-BIT UP/DOWN COUNTER 190 191 BCD BINARY V cc \ CA CB , -STAGE BINARY COUNTER 14-STAGE BINARY COUNTER/OSCILLATOR DUAL BCD PROGRAMMABLE DOWN COUNTER 8-BIT BINARY
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74HC27A 74HC11A 74HC21A 74HC4072 74HC07A 74HC368A LM 4017 decade counter driver 74HC7244A 74HCT7007A 74HC147 decimal to binary encoder 74HC85A 74HC00A 74HCT00A 74HC03A 74HC10A 74HC20A 74HC30

FZK101

Abstract: FZK105 7 0 3 O P /A 7 2 3 O P /A 7 4 1 F a irc h ild 914 IC 555 LM 565 7490 7420 7402 7440 7476' 74121 709C , 7453 7454 7460 7470 7472 7473 7474 7475 7476 7480 7481 7482 7483 7484 7485 7486 7489 7490 7491 7492
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FZK101 FZK105 upd101 SNF10 SN76131 TAA700 CN50-51 ZSS58-86-116 CN52-53 ZSS57-87-117-137 CN54-55 ZST51-81-11-131

intel 7882

Abstract: 31 anl amplifier output. The DC bias point can be steered up or down by an external potentiometer. By this means , 2.488 Gbit/s, 1.244 Gbit/s, 622.08 Mbit/s, and 155.52 Mbit/s. GD16524 also supports up to 7% overhead , acquisition mode. The PFD is used to ensure predictable lock up conditions for the GD16524 by locking the , above a predefined level. This has been realised with a counter counting the false bit transitions. If this counter runs out within a time period the BEF flag is set. The length of the counter may
GIGA
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STM-16 intel 7882 31 anl DO15 STM16 OC-48 STM-16/OC-48 GD16524-100BA FAGD16524100BA DK-2740

lm294oct

Abstract: d71054c -bit up/down synch bin counter 4 x 4 register file Quad D flip-flop with 3-state out Hex D flip-flop Quad D flip-flop 4-bit arithmetic logic unit Up/down decode counter 4-bit binary up/down counter 4-bit binary up/down counter 4-bit bi-direct universal shift reg 4-bit par-access shift register 4 , -bit binary counter 8-bit ser-in, par-out shift reg 4-bit up/down synch bin counter Hex D flip-flop Quad D flip-flop 4-bit binary up/down counter 4-bit bi-direct universal shift reg 4-bit parallel-access shift
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lm294oct d71054c D71055C lm294oct-12 7486 XOR GATE 74c928 74LS01 74LS02 74LS03 74LS04 74LS05 74LS06

intel 7882

Abstract: GD16524-100BA DC bias level of the limiting amplifier output. The DC bias point can be steered up or down by an , up to 7% overhead, allowing for 2.66 Gbit/s data transfer. l Digital LOS monitor and alarm , range. This mode is called the acquisition mode. The PFD is used to ensure predictable lock up , with a counter counting the false bit transitions. If this counter runs out within a time period the BEF flag is set. The length of the counter may be set by external select signals (SBER0 and SBER1).
GIGA
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FAGD16524100BA

Abstract: DO15 output. The DC bias point can be steered up or down by an external potentiometer. By this means the , up to 7% overhead, allowing for 2.66 Gbit/s data transfer. l Digital LOS monitor and alarm , range. This mode is called the acquisition mode. The PFD is used to ensure predictable lock up , predefined level. This has been realised with a counter counting the false bit transitions. If this counter runs out within a time period the BEF flag is set. The length of the counter may be set by
GIGA
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DO15

Abstract: GD16524 DC bias level of the limiting amplifier output. The DC bias point can be steered up or down by an , range. This mode is called the acquisition mode. The PFD is used to ensure predictable lock up , with a counter counting the false bit transitions. If this counter runs out within a time period the BEF flag is set. The length of the counter may be set by external select signals (SBER0 and SBER1). , 16 / OC-48 data rate. The length of the counter may be set to detect approximate bit error rates of
GIGA
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DO13 package DO14

74HC4096

Abstract: EQUIVALENT TIMER IC WITH CD 4060 Selection Guide C2M0S Logic TC74HC/HCT Series Counter (Continued) SYNC. 4-BIT UP/DOWN COUNTER 192 , . CLEAR 4 -B IT BINARY UP/DO W N COUNTER SYNC. UP/DO W N BINARY COUNTER DUAL BINARY COUNTER 8-B IT BINARY , . CLEAR SYNC. DECADE COUNTER W ITH SYNC. CLEAR BCD UP/DOW N COUNTER SYNC. UP/DO W N DECADE COUNTER DUAL , , SYNCHRONOUS 163 BINARY, SYNCHRONOUS CLEAR VCC GAAKY .OUTPUT 1 QA QB OC QD » " SYNCHRONOUS 4-BIT UP/DOWN , VCC \ 203 ^ 800 2CLOCR INABLE / 2CL0CK PROGRAMMABLE DOWN COUNTER 40102 DUAL BCD 40103 8-BIT BINARY
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C4049A C4050A HC155A C148A HC191A 74HC4096 EQUIVALENT TIMER IC WITH CD 4060 rs flip-flop IC 7400 shiftregister PIPO L1AA HC02A HC08A HC125A HCT244A HC541A

up down counter using IC 7476

Abstract: pin diagram for IC 7476 COUNTER PIN ASSIGNMENT (Top View) 160-Lead, Dual Read-out DIMM (SF-1) 32K x 72 (SF-2) 64K x 72 , which is useful for b attery back up m od e of op era tion. A lth o u g h th e p a rt is n o t gu aran , counter, controlling burst access after the external address is loaded. A HIGH on this pin effectively , registered. A READ or WRITE is performed using the new address if all chip enables are active. Power down , , 63, 65-67, 71-72, 74-76, 82, 84-87, 89-91,95-98,102, 104-106, 129, 132-134, 139-141, 143-147, 152
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up down counter using IC 7476 pin diagram for IC 7476 and pin diagram of IC 7476 MT2LSYT3272C4 MT4LSYT6472C4 160-L DQO-63 256KB 512KB

7476 3 bit ripple counter

Abstract: COP820CJ . The counter counts down upon an edge on the TIO pin. Control bits in the register CNTRL program the , timer contains an 8-bit READ/WRITE down counter clocked by an 8-bit prescaler. Under software control , configured as an output. The number of pulses is determined by the 8-bit down counter. Under software control , counter is clocked by tC. In this mode the 16-bit timer T1 along with the 8-bit down counter are used to generate a variable duty cycle PWM signal. The timer T1 underflow sets MC1 which starts the down counter
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COP840CJ COP820CJ COP822CJ COP823CJ COP842CJ COP940CJ 7476 3 bit ripple counter COP820CJ/COP840CJ COP820CJ/840CJ COP87L
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