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SN7476N-00 Texas Instruments TTL/H/L SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP16 visit Texas Instruments
SN7476N-10 Texas Instruments TTL/H/L SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP16 visit Texas Instruments
SN7476J Texas Instruments IC TTL/H/L SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP16, FF/Latch visit Texas Instruments
SN7476J-00 Texas Instruments IC TTL/H/L SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP16, FF/Latch visit Texas Instruments
ADCS7476AISDX Texas Instruments 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, DSO6, LLP-6 visit Texas Instruments
ADCS7476AIMFX/NOPB Texas Instruments 1MSPS, 12-/10-/8-Bit A/D Converters in SOT-23 & LLP 6-SOT-23 -40 to 125 visit Texas Instruments Buy

7476 ttl

Catalog Datasheet MFG & Type PDF Document Tags

ci 7476

Abstract: 7476 PIN DIAGRAM , Clock, Set and Reset inputs. The 7476 is positive pulse-triggered. JK information is loaded into the , Table. 7476, LS76 Flip-Flops Dual J-K Flip-Flop Product Specification TYPE TYPICAL fMAX TYPICAL SUPPLY CURRENT (TOTAL) 7476 20MHz 10mA 74LS76 45MHz 4mA ORDERING CODE PACKAGES COMMERCIAL RANGE VCC = , Manufacturer 853-0568 81501 Signetics Logic Products _Product Specificotion Flip-Flops 7476, LS76 LOGIC , inputs of the 7476 must be stable while the Clock is HIGH for conventional operation. December 4, 1985
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ci 7476 7476 PIN DIAGRAM pin diagram of 7476 jk flip flop 7476 pin diagram of ttl 7476 7476 N7476N N74LS76N 1N916 1N3064

pin diagram of 7476

Abstract: PIN CONFIGURATION 7476 Flip-Flops 7476, LS76 TEST CIRCUITS AND WAVEFORMS VM = 1.3V for 74LS; V m = 1-5V for all other TTL , Signetics 7476, LS76 Flip-Flops Dual J-K Flip-Flop Product Specification Logic Products DESCRIPTION The '76 is a dual J-K flip-flop with individual J, K, Clock, Set and Reset inputs. The 7476 is , the outputs to the steady state levels as shown in the Function Table. TYPE 7476 74LS76 TYPICAL f MAx , 81501 Signetics Logic Products Product Specification Flip-Flops 7476, LS76 LOGIC DIAGRAM
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PIN CONFIGURATION 7476 7476 PIN DIAGRAM input and output Jk 74ls76 pin out 7476 FUNCTION TABLE 7476 J-K Flip-Flop 7476 pin configuration

PIN CONFIGURATION 7476

Abstract: pin diagram of 7476 Sjgnetics 7476, LS76 Flip-Flops Dual J-K Flip-Flop Product Specification Logic Products DESCRIPTION The '76 is a dual J-K flip-flop with individual J, K, Clock, Set and Reset inputs. The 7476 is , , forcing the outputs to the steady state levels as shown in the Function Table. TYPE 7476 74LS76 TYPICAL f , 5-114 853-0566 81501 Signetics Logic Products Product S pecification Flip-Flops 7476 , the Clock for predictable operation. 3. The J and K inputs of the 7476 must be stable while the Clock
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LS 7476 J-K Flip-Flop 7476 TTL 74ls76 74LS76 logic diagram 7476 ttl TTL 7476

jk flip flop 7476

Abstract: 7476 PIN DIAGRAM , Clock, Set and Reset inputs. The 7476 is positive pulse-triggered. JK information is loaded into the , understood to be 40>iA l,H and -1.6mA l,L. and a 74LS unit load (LSul) is 20juA l)H and -0.4mA l|L. 7476 , (TOTAL) 7476 20MHz 10mA 74LS76 45MHz 4mA ORDERING CODE PACKAGES COMMERCIAL RANGE VCC = 5V±5%; TA = , Flip-Flops 7476, LS76 LOGIC DIAGRAM ld02900s FUNCTION TABLE OPERATING MODE INPUTS OUTPUTS SD Rd , predictable operation. 3. The J and K inputs of the 7476 must be stable while the Clock is HIGH for
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74LS76 ttl Jk 7476 LS76 Flip-Flop 7476 flip-flop 74ls76

IC 7476

Abstract: 7476 truth table FAIRCHILD TTL/SSI . 9N76/5476, 7476 DUAL JK MASTER/SLAVE FLIP-FLOP WITH SEPARATE PRESETS, CLEARS AND CLOCKS DESCRIPTION - The TTL/SSI 9N76/5476, 7476 is a Dual JK Master/Slave flip-flop with separate presets, separate clears and separate clocks. Inputs to the master section are controlled by the clock , FAIRCHILD TTL/SSI â'¢ 9N76/5476, 7476 RECOMMENDED OPERATING CONDITIONS PARAMETER 9N76XM/5476XM 9N76XC , MAX- V|N = OV 51 -18 -57 mA 9N76/7476 'CC Supply Current 20 40 mA Vcc = MU- 49 SWITCHING
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IC 7476 7476 truth table circuit diagram with IC 7476 7476 IC 7476 logic diagram 7476 Connection diagram 9N76XC/7476XC 9N76/7476

74573

Abstract: 74574 Semiconductor Logic Device Cross-Reference Here is a comprehensive cross-reference of TTL and , UK ). Tables of both TTL and CMOS devices are provided along with tables grouping chips with the same functionality together. The following tables are available . TTL Device Summary CMOS Device , device is suitable for your purposes. 1 of 12 E&OE. TTL Device Summary Please click on a , 7476 7483 7485 7486 7490 7493 74121 2 of 12 Function Quad 2-Input NAND Gate Quad 2
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74573 74574 7486 XOR GATE 7486 full adder latch 74574 7408, 7404, 7486, 7432

7476 J-K Flip-Flop

Abstract: TTL 7474 Digital Integrateci Circuits TTL Flip-Flops A range of standard '7400 series' TTL flip-flops is available in plastic dual-in-line encapsulation. DIC 7470 D.C.CIocked J-K Flip-Flop DIC 7472 J-K Master-Slave Flip-Flop DIC 7473 DUAL J-K Master-Slave Flip-Flop DIC 7474 DUAL D type Edge-Triggered Flip-Flop DIC 7476 DUAL Jâ'"K Master-Slave Flip-Flop with Preset and Clear DIC 7470 DIC 7472 DIC7473 DIC 7474 PRESET 2 [j CLEAR 7 1 8 DIC 7476 TO 116 14 LEAD MAX 5 08 HH -pi |4â'"8-9â'" â'¢1C UH c Â
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TTL 7474 Flip-Flop 7470 7472 Flip-Flop 7474 D flip-flop 7473 dual JK 7470 TTL

7476 ic specifications

Abstract: ic 7476 TEXAS 75 26 5 TTL SN 5476, SN 7476 DUAL J-K FLIP FLOPS WITH PRESET AND CLEAR logic diagrams (positive logic) TTL D e v ic e s 2 248 INSTTOJMENTS POST OFPICE BOX 6 5 5 0 1 2 · D ALLAS. TEXAS 75 26 5 SN 5476, SN 54LS 76A , SN 7476, S N 74 LS7 6A DUAL J K FLIP FLOPS WITH PRESET AND CLEAR , Te x a s ^ In s t r u m e n t s POST OFFICE BOX 6 5 5 0 1 2 · D ALLAS . TEXAS 75 26 5 249 TTL D e v ic e s logic sym bols* SN 5476, SN 54LS76A , SN 7476, SN 74 LS 7 6A DUAL J-K FLIP-FLOPS
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7476 ic specifications IC 7476 JK logic diagram of ic 7476 SN547G SN54LS76A SN7476 SN74LS76A

TTL 74ls74

Abstract: 74ls74 FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -TTL MASTER/SLAVE EDGE-TRIGGERED ill (9 D UJ (3 Z o (3 in > O a z o in o z < X o I-3 a. I- O D55 9020 J Q CP K â'ž 0 , /7476, 54H/74H76, 54LS/74LS76 2 7 14 â'" J 0 "Vcc = Pin 14 1-0 CP GND = Pin 7 3 â'" K Q Pins are , '" KC0 0 oL< 12_ O Vcc = Pin 5 GND = Pin 13 13-49 FAIRCHILD DIGITAL TTL TTL SINGLE AND DUAL , D63 3I, 6A, 9A 21 Dual JK 54/7476 J, K J L X X 20 25 100 D58 4L, 6B, 9B 22 Dual JK 54H/74H76 J, K j
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TTL 74ls74 74ls74 CI 7473 7476 JK ttl 7474 14 PIN 7474 PIN DIAGRAM 54S/74S109 54LS/74LS109 54H/74H74 54S/74S74 54LS/74LS74 54H/74H73
Abstract: quantities on request 1) Werte nach DIN IEC 747-6 (ohne vorausgehende Kommutierung)/Values to DIN IEC 747-6 , ^ 7 F l7 t Bild/Fig. 17 Transienter innerer Wärmewiderstand Z(ttl)jc = f(t). DC Transient thermal impedance Z(ttl)jc = f (l), DC Bild/Fig. 18 Zündverzug/Gate controlled delay time tgd = f(iG -
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7476 truth table

Abstract: purpose use. This device has TTL compatible inputs and outputs and requires+5V and -12 V power supplies , next column to right. 2. Underlined addresses result In all outputs going low (TTL "0"). 3. Black , ASCII in next column to right. 2. Undefined addresses result in all outputs going low (TTL â'0"). 3. Black squares in character font are high {TTL â'V ). 130 CUSTOM CODING INFORMATION 2526 , ' Blank Name 2 Data Cards Card No. 1 Column 1-9 10 11-19 20 21-29 73 74-76 77
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2526-N 0I0I00I0I 0I00I0T0T NQISM3AN03 N-92S

2526N

Abstract: signetics 2526 , or as a 512x9 ROM for general purpose use. This device has TTL compatible inputs and outputs and , ORGANIZATION > 625m TYPICAL ACCESS TIME â'¢ STATIC OPERATION â'¢ OUTPUT LATCHES â'¢ TTL/DTL COMPATIBLE INPUTS â'¢ TTL/DTL COMPATIBLE TRI-STATE OUTPUTS â'¢ Vcc"+5V,Vgq = -12V â'¢ 24-PIN SILICONE DIP â , integrated circuits (TTL, DTL, etc.). The data output buffers are capable of sinking a minimum of 1.6mA to drive one standard TTL load. STANDARD CODES The 2526 is available with ASCII-addressed characters
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2526N signetics 2526 7x9 decoder pin diagram decoder 7476 CM3940 CM3400

7476 truth table

Abstract: 7474 truth table s A X 25 10 15 50 TTL/MSI 93178/54178, 74178 93179/54179, 74179 4-BIT SHIFT , 9N25, 7425 9N20, 7420 9N76, 7476 9N73, 7473 9N76, 7476 9N70, 7470 9N73, 7473 9N74, 7474 9N72, 7472 9N50
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82S62 7474 truth table se 9315-1 fairchild 9322 signetics 8281 7474 equivalent 93L22 93L09 93L12 93S12 93H00 93S00

TTL 74ls74

Abstract: 7474 14 PIN FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -TTL MASTER/SLAVE EDGE-TRIGGERED ill (9 D UJ (3 Z o (3 in > O a z o in o z < X o I-3 a. I- O D55 9020 J Q CP K â'ž 0 Cd D60 9024, 54/74109, 54S/74S109, 54LS/74LS109 5 11 ~LT 2 â'" J SD 0 _6 14 0 4 â'" CP 12 CP 3-0 K Co Q »1 13 â'"0 K Cd 0 Vcc = Pin 16 GND = Pin 8 D56 9022 SD J Q CP K 0 Cd , /7476, 54H/74H76, 54LS/74LS76 2 7 14 â'" J 0 "Vcc = Pin 14 1-0 CP GND = Pin 7 3 â'" K Q Pins are
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7474 14 PIN ttl 74ls109 74LS107 74LS73 74LS109 7474 16 PIN 54LS/74LS73 54LS/74LS107 54H/74H103

CI 7474

Abstract: CI 7473 FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -TTL MASTER/SLAVE EDGE-TRIGGERED ill (9 D UJ (3 Z o (3 in > O a z o in o z < X o I-3 a. I- O D55 9020 J Q CP K â'ž 0 Cd D60 9024, 54/74109, 54S/74S109, 54LS/74LS109 5 11 ~LT 2 â'" J SD 0 _6 14 0 4 â'" CP 12 , /7476, 54H/74H76, 54LS/74LS76 2 7 14 â'" J 0 "Vcc = Pin 14 1-0 CP GND = Pin 7 3 â'" K Q Pins are , '" KC0 0 oL< 12_ O Vcc = Pin 5 GND = Pin 13 13-49 FAIRCHILD DIGITAL TTL TTL SINGLE AND DUAL
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CI 7474 7474 D latch CI 74LS76 CI 74107 fairchild 9024 ci 74LS74 54S/74S114 54LS/74LS 54LS/74LS78 93L14 54LS/74LS279 54LS/74LS196

pin diagram for jk flip flop 7476

Abstract: jk flip flop 7476 LS TTL DN74LS Series DN74LS76 DN74LS76 £>ivJ 74^76 Dual J-K Flip-Flops (with Set and Reset) I Description DN74LS76 contains two negative-edge triggered J-K flip-flop circuits, each with independent clock-CP, J, K, and direct-coupled set and reset input terminals. â  Features â'¢ Negative-edge , Electronic-Library Service CopyRight 2003 k LS TTL DN74LS Series DN74LS76 DC characteristics (Ta = â'" 20 â , Electronic-Library Service CopyRight 2003 LS TTL DN74LS Series DN74LS76 [2] tphi . tpLH(Reset, Set â'"» Q, Q) 1
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pin diagram for jk flip flop 7476 SO-16D

jk flip flop 7476

Abstract: pin diagram for jk flip flop 7476 LS TTL DN74LS Series DN74LS76 DN74LS76 £>ivJ 74^76 Dual J-K Flip-Flops (with Set and Reset) I Description DN74LS76 contains two negative-edge triggered J-K flip-flop circuits, each with independent clock-CP, J, K, and direct-coupled set and reset input terminals. â  Features â'¢ Negative-edge , Copyrighted By Its Respective Manufacturer ;â'ž:â'¢ k LS TTL DN74LS Series DN74LS76 DC characteristics (Ta , 'ž _ Vâ'žH â'" Vâ'žr -118â'" This Material Copyrighted By Its Respective Manufacturer LS TTL DN74LS
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74LS80

Abstract: 74LS198 (TTL) "L " Input voltage (TTL) " H " Input voltage (CMOS) " L " Input voltage (CMOS) "H " Output , pull-up INT1U1 INT2U1 INTSU1 INC1U1 INC2U1 INCSU1 INTID1 INT2DI INTSD1 INCIDI INC2D1 INCSD1 FUNCTION TTL Compatible TTL TTL CMOS Compatible CMOS CMOS TTL Compatible TTL TTL CMOS Compatible CMOS CMOS TTL Compatible TTL TTL CMOS Compatible CMOS CMOS Inverter Buffer Schmitt Trigger Inverter Buffer Schmitt Trigger , IOCSCH IOCSH IOTI Ul lOTUl 10T2UI I0CIU1 I0CUI I0C2U1 IOTI Dl lOTDl IOC1D1 IOCD1 XIN01 XOUT XIO TTL
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RSC-15 M4017C M4028C 74LS179 74LS198 74LS80 74LS150 74LS94 OAI32 0001L3M TEK-044-9004 NOR03 NAND08 D410L

7472 PIN DIAGRAM

Abstract: 74ls112 pin diagram Pin 7 13-50 FAIRCHILD DIGITAL TTL TTL SINGLE AND DUAL FLIP-FLOPS Item Function DEVICE NO. Inputs , 20 Dual JK 54LS/74LS113 J, K ~L X â'" 60 12 20 D63 3I, 6A, 9A 21 Dual JK 54/7476 J, K J L X X 20 25
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7472 PIN DIAGRAM 74ls112 pin diagram 74LS112 TTL 74107 7473 pin diagram 74h106 54H/74H78 54H/74H106 54S/74S112 54LS/74LS112 54H/74H108 54S/74S113

7472 PIN DIAGRAM

Abstract: 74574 So J Q â'" 8 CP K O 0â'"6 Cd Vcc = Pin 14 GND = Pin 7 13-48 FAIRCHILD DIGITAL TTL TTL , X â'" 60 12 20 D63 3I, 6A, 9A 21 Dual JK 54/7476 J, K J L X X 20 25 100 D58 4L, 6B, 9B 22 Dual JK
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TTL 7472 7472 ttl O9111 7472 ci Fairchild 9020 74LS113 54H/74H71 54H/74H101 54H/74H72 54H/74H102 74H71
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