NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Catalog Datasheet Results | Type | Document Tags |
| Abstract: Signetics Logic Products _Product Specificotion Flip-Flops 7476, LS76 LOGIC DIAGRAM cp ldoz800s , , Set and Reset inputs. The 7476 is positive pulse-triggered. JK information is loaded into the master , and Data inputs, forcing the outputs to the steady state levels as shown in the Function Table. 7476 , (TOTAL) 7476 20MHz 10mA 74LS76 74LS76 45MHz 4mA ORDERING CODE PACKAGES COMMERCIAL RANGE VCC = 5V±5%; TA = , tobe40*iA l,H and-1.6mA l|L, and a74LS unit load (LSul) is20/uA lIH and -0.4mA l(L. PIN CONFIGURATION ... | OCR Scan |
6 pages, |
TTL 7476 7476 logic diagram Flip-Flop 7476 ci 74ls76 74ls76 Jk 7476 PIN CONFIGURATION 7476 i c 74ls76 7476 pin configuration 7476 J-K Flip-Flop 7476 TTL 74ls76 7476 ttl 74LS76 74LS76 abstract |
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| Abstract: Manufacturer Signetics Logic Products _Product Specification Flip-Flops 7476, LS76 LOGIC DIAGRAM ld02900s , , Set and Reset inputs. The 7476 is positive pulse-triggered. JK information is loaded into the master , -1.6mA l,L. and a 74LS unit load (LSul) is 20juA l)H and -0.4mA l|L. 7476, LS76 Flip-Flops Dual J-K Flip-Flop Product Specification TYPE TYPICAL fMAX TYPICAL SUPPLY CURRENT (TOTAL) 7476 20MHz 10mA 74LS76 74LS76 , inputs 2ul 2LSul J, K Data inputs 1ul 1LSul Q, 3 Outputs 10ul 10LSul note: PIN CONFIGURATION cp, [T ... | OCR Scan |
6 pages, |
LS76 N7476N pin diagram for jk flip flop 7476 PIN CONFIGURATION 7476 N74LS76N Jk 7476 TTL 7476 74LS76 ttl 74LS76 7476 pin configuration J-K Flip-Flop 7476 7476 J-K Flip-Flop pin diagram of ttl 7476 74LS76 abstract |
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| Abstract: 0-13 12 KC0 0 Vcc = Pin 4 GND = Pin 11 D57b 54H/74H103 54H/74H103 D58 54/7476, 54H/74H76 54H/74H76, 54LS/74LS76 54LS/74LS76 2 7 , Co Q »1 13 -0 K Cd 0 Vcc = Pin 16 GND = Pin 8 D56 9022 SD J Q CP K 0 Cd "O 11 J_ 15 Vcc = Pin 16 GND = Pin 8 D61 54/7474, 54H/74H74 54H/74H74, 54S/74S74 54S/74S74, 54LS/74LS74 54LS/74LS74 4 10 J SC Q CP KCoQ 7 2 - D SD Q -5 - O 3 - CP 11 - CP Cd 0 0-6 Cd O 15 Vcc = Pin 16 GND = Pin 8 Vcc = Pin 14 GND = Pin 7 111 F < o tu z z o ... | OCR Scan |
2 pages, |
7474 PIN DIAGRAM pin diagram 7474 ttl 74ls109 TTL 74107 flip flop jk pin diagram of 7473 Jk 74ls76 7476 ttl 7473 dual JK TTL 7474 7476 PIN DIAGRAM jk 7474 74LS74 TTL datasheet abstract |
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| Abstract: 54/7476 54H/74H76 54H/74H76 54LS/74LS76 54LS/74LS76 LOGIC SYMBOL DESCRIPTION The "76" is a DualJK Flip-Flop with individual J, K, Clock, Set and Reset inputs. The 7476 and 74H76 74H76 are positive pulse triggered flip-flops. JK , Information) PACKAGES PIN CONF. COMMERCIAL RANGES VCC = 5V ± 5%; TA = 0°C to *70°C MILITARY RANGES VCC = 5V ± , 16- Û -14 12 - K "O 0 -10 Vcc = Pin 5 GND = Pin 13 PIN CONFIGURATION CP, [T 76]K, sdì [X TS , Material Copyrighted By Its Respective Manufacturer LOGIC DIAGRAM MODE SELECT-TRUTH TABLE CP OPERATING ... | OCR Scan |
2 pages, |
74H76 N7476F N7476N N74H76F N74LS76F N74LS76N 74ls76 N74H76N 7476 logic diagram 7476 J-K Flip-Flop 7476 PIN DIAGRAM input and output Jk 7476 Jk 74ls76 pin out S5476F 54H/74H76 54LS/74LS76 54H/74H76 abstract |
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| Abstract: 0-13 12 KC0 0 Vcc = Pin 4 GND = Pin 11 D57b 54H/74H103 54H/74H103 D58 54/7476, 54H/74H76 54H/74H76, 54LS/74LS76 54LS/74LS76 2 7 , Co Q »1 13 -0 K Cd 0 Vcc = Pin 16 GND = Pin 8 D56 9022 SD J Q CP K 0 Cd "O 11 J_ 15 Vcc = Pin 16 GND = Pin 8 D61 54/7474, 54H/74H74 54H/74H74, 54S/74S74 54S/74S74, 54LS/74LS74 54LS/74LS74 4 10 J SC Q CP KCoQ 7 2 - D SD Q -5 - O 3 - CP 11 - CP Cd 0 0-6 Cd O 15 Vcc = Pin 16 GND = Pin 8 Vcc = Pin 14 GND = Pin 7 111 F < o tu z z o ... | OCR Scan |
2 pages, |
74LS73 dual JK 74ls76 74196 74LS76 FAIRCHILD ttl 74ls109 TTL 74109 ttl 74107 pin diagram of 7473 7473 latch 74ls74 74LS109 74ls107 ci 74LS74 fairchild 9024 datasheet abstract |
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| Abstract: D54 54/7470 13 Vcc = Pin 14 GND = Pin 7 T 13 Vcc = Pin 14 GND = Pin 7 19-ol-^ So CP KCo ~~7 Vcc = Pin 14 GND = Pin 7 111 O D 111 O z o (9 111 > H < (9 ui Z o (0 111 u z < z o 3 a. , - 6 CP K O 0-8 Vcc = Pin 14 GND = Pin 7 D53a 54/7472 54H/74H72 54H/74H72 13 Vcc = Pin 14 GND = Pin 7 D53b 54H/74H102 54H/74H102 1ÌE0 J S° o - 8 CP KC0 0 0-6 T 2 Vcc = Pin 14 GND = Pin 7 ÌED So J Q - 8 CP K O 0-6 Cd Vcc = Pin 14 GND = Pin 7 13-48 FAIRCHILD DIGITAL TTL TTL SINGLE AND DUAL ... | OCR Scan |
2 pages, |
TTL 7472 7474 fairchild 7474 PIN DIAGRAM 7476 7476 ttl Fairchild 902 jk 7474 Jk 7476 d52b 7472 ci pin diagram of ttl 7476 Fairchild 9020 CI 7473 7473 dual JK datasheet abstract |
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| Abstract: z o (A Ul (9 z < X o I-3 a H 3 O Vcc = Pin 14 GND = Pin 7 EDGE-TRIGGERED D58 54H/74H106 54H/74H106 4 - , J 0 -5 1-i J S° 0 CP 13-0 CP K _ Co Q o-6 3£ K ^ Cd 0 Vcc = Pin 5 GND = Pin 13 o-10 Vcc = Pin 16 GND = Pin 8 D59b 54H/74H108 54H/74H108 10 0 - 2 11 J So 0 CP CP K Co Q 0-3 8_ K Cd 0 D63 54S/74S113 54S/74S113, 54LS/74LS113 54LS/74LS113 3 - 0 -5 11 a 1-0 CP 13-0 CP 2- K 0 0-6 12- K Q Vcc = Pin 14 GND = Pin 7 Vcc = Pin 14 GND = Pin 7 D64 54S/74S114 54S/74S114, 54LS/74LS114 54LS/74LS114 4 J> 10 i 3 - J sd Q - S 11 Sd J Q ... | OCR Scan |
2 pages, |
74574 7472 ci 7473 dual JK 7474 PIN DIAGRAM 7476 ttl 74H108 74H78 74LS74 D59b Fairchild 902 jk 7474 CI 7473 7476 Jk 7476 54H/74H78 54H/74H78 abstract |
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| Abstract: Table on the HIGH-to-LOW clock transitions. ORDERING CODE: See Section 9 CONNECTION DIAGRAM PIN OUT A PKGS PIN OUT COMMERCIAL GRADE MILITARY GRADE PKG TYPE Vcc = +5.0 V ±5%, Ta = 0°C to +70" C Vcc = , 76 ^54/7476 O/Zô/b, ^54H/74H76 54H/74H76 l/54LS/74LS76 Gf/otù, DUAL JK FLIP-FLOP (With Separate Sets, Clears and Clocks) DESCRIPTION -The '76 and 'H76 are dual JK master/slave flip-flops with separate , o-10 Vcc = Pin 5 GND = Pin 13 4-86 This Material Copyrighted By Its Respective Manufacturer 76 PIN ... | OCR Scan |
3 pages, |
7476 JK 7476 54LS76DM 54H76DM 74ls76 LS76 Jk 74ls76 pin out 74LS76DC Flip-Flop 7476 7476 master slave 74LS76PC J-K Flip-Flop 7476 74LS76P 74LS76 dual flip-flop 54H/74H76 54H/74H76 abstract |
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| Abstract: COMPATIBLE TRI-STATE OUTPUTS • Vcc"+5V,Vgq = -12V • 24-PIN SILICONE DIP • P-MOS SILICON GATE TECHNOLOGY , BILLBOARDS MICRO-PROGRAMMING CODE CONVERSION PROGRAM STORAGE SILICON GATE MOS 2500 SERES PIN , 9 . Address 8 . Address 7 . Address 6 BLOCK DIAGRAM BIPOLAR COMPATIBILITY All inputs of the 2526 , OP. TEMP. RANGE PACKAGE 2526N 2526N 0-70°C 24-Pin Silicone DIP 25261 0-70°C 24-Pin Ceramic DIP 88 , TIMING DIAGRAM NOTE: AM Tim«« Measured from 50% Point«. tr - tf â- 10 it* or let«. APPLICATION ... | OCR Scan |
7 pages, |
CHARACTER table application pin diagram decoder 7476 CM3400 7476 truth table 7x9 decoder 7476 ttl 7476 PIN DIAGRAM 2526N PIN CONFIGURATION 7476 pin diagram of ttl 7476 datasheet abstract |
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| Abstract: (/) 30 (D IQ W (D CO CO m O c T3 C Connection Diagram Dual-ln-Line Package Logic Symbol MR - 1 , Mode Select Table Vqq = Pin 16 GND = Pin 8 Operating Mode Inputs 8 tn Outputs @tn+1 MR CP S Ds , either state, provided that the recommended setup and hold times are observed. Logic Diagram When the S , 0.3977-0.41 33 16 15 14 13 12 11 10 9 nnnnnnnn LEAD NO 1 IDENTIFICATION 0.29 14-0.2992 7.4-7.6 , Molded Package (M) Order Number DM74LS395WM DM74LS395WM Package Number M16B PIN NO. 1_ IDENT 0.130 ±0.005 (3.302 ... | OCR Scan |
5 pages, |
N16E M16B LS395 DM74LS395WM DM74LS395N DM74LS395 762-T 7476 PIN DIAGRAM input and output DM74LS395 abstract |
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| t han 2 sec. (typ), the warning pin is pulled down. The m P can address the TDA7476 to know the byte from TDA7476 Figure 2: Data Validity on the I 2 CBUS Figure 3: Timing Diagram on the I 2 address of TDA7476 is selected using pin ADD (pin 4) . If ADD is connected to ground, then A = 0 and the the TDA7476 connecting STBY pin to ground; 2- to wait T 5V seconds (time necessary for the - to do the repetitive turn-on diagnostic as above described; 5- to turn off the TDA7476. WARNING PIN www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/6328.htm |
STMicroelectronics | 20/10/2000 | 30.71 Kb | HTM | 6328.htm |
| : Timing Diagram on the I 2 CBUS Figure 4: Acknowledge on the I 2 CBUS TDA7476 8/15 SOFTWARE SPECIFICATIONS The TDA7476 is activated by turning-on the ST-BY pin (CMOS compatible). In this pin ADD (pin 4) . If ADD is connected to ground, then A = 0 and the TDA7476 address is 0100010X 0100010X 0100010X 0100010X -on diagnostic are the following: 1- to switch off the TDA7476 connecting STBY pin to ground; 2- to wait T described; 5- to turn off the TDA7476. WARNING PIN This is an open drain output pin that is activated www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/6328-v3.htm |
STMicroelectronics | 25/05/2000 | 29.65 Kb | HTM | 6328-v3.htm |
| Stand-By Voltage Pin = 1.5V 100 m A Iq Total Quiescent Current Total quiescent Current with TDA7476 not warning pin is pulled down. The m P can address the TDA7476 to know the status. The subsonic current ) when it reads a data byte from TDA7476 Figure 2: Data Validity on the I 2 CBUS Figure 3: Timing Diagram 7476 is activated by turning-on the ST-BY pin (CMOS compatible). In this condition it waits for the I . The address of TDA7476 is selected using pin ADD (pin 4) . If ADD is connected to ground, then A = 0 www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/6328-v1.htm |
STMicroelectronics | 02/04/1999 | 27.38 Kb | HTM | 6328-v1.htm |
| Stand-By Voltage Pin = 1.5V 100 m A Iq Total Quiescent Current Total quiescent Current with TDA7476 not warning pin is pulled down. The m P can address the TDA7476 to know the status. The subsonic current ) when it reads a data byte from TDA7476 Figure 2: Data Validity on the I 2 CBUS Figure 3: Timing Diagram 7476 is activated by turning-on the ST-BY pin (CMOS compatible). In this condition it waits for the I . The address of TDA7476 is selected using pin ADD (pin 4) . If ADD is connected to ground, then A = 0 www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/6328-v2.htm |
STMicroelectronics | 14/06/1999 | 27.34 Kb | HTM | 6328-v2.htm |
| . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 4.13 MANAGING TRACE BUFFER RECORDING USING THE LOGIC ANALYSER . . . . . . . . 50 4.14 PIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 4.14.2 How to Setup Pin Input Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 4.14.3 Starting Pin Input Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 4.14.4 Pin Output Signals Generated by your Program . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4.14.5 Viewing Pin Output Generated by your Program www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/6138-v2.htm |
STMicroelectronics | 11/01/2000 | 108.13 Kb | HTM | 6138-v2.htm |
| . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 4.13 MANAGING TRACE BUFFER RECORDING USING THE LOGIC ANALYSER . . . . . . . . 50 4.14 PIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 4.14.2 How to Setup Pin Input Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 4.14.3 Starting Pin Input Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 4.14.4 Pin Output Signals Generated by your Program . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4.14.5 Viewing Pin Output Generated by your Program www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/6138.htm |
STMicroelectronics | 20/10/2000 | 111.51 Kb | HTM | 6138.htm |
| . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 4.13 MANAGING TRACE BUFFER RECORDING USING THE LOGIC ANALYSER . . . . . . . . 50 4.14 PIN INPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 4.14.2 How to Setup Pin Input Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 4.14.3 Starting Pin Input Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 4.14.4 Pin Output Signals Generated by your Program . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4.14.5 Viewing Pin Output Generated by your Program www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/6138-v1.htm |
STMicroelectronics | 02/04/1999 | 106.03 Kb | HTM | 6138-v1.htm |
| /D CONVERTER, 80 PINS Datasheet 8-BIT MICROCONTROLLER (MCU) WITH 8K OTP, ROM, EPROM, WITH LCD DRIVER, EEPROM AND A/D CONVERTER, 80 PINS bytes n Data EEPROM: 128 bytes n User Programmable Options n 12 I/O pins, fully programmable as . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2 PIN DESCRIPTIONS well as the respec- tive ST6285B ST6285B ST6285B ST6285B ROM devices. Figure 1. Block Diagram TEST NMI INTERRUPT www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/5695-v2.htm |
STMicroelectronics | 11/01/2000 | 160.78 Kb | HTM | 5695-v2.htm |
| /D CONVERTER, 80 PINS Datasheet 8-BIT MICROCONTROLLER (MCU) WITH 8K OTP, ROM, EPROM, WITH LCD DRIVER, EEPROM AND A/D CONVERTER, 80 PINS bytes n Data EEPROM: 128 bytes n User Programmable Options n 12 I/O pins, fully programmable as . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2 PIN DESCRIPTIONS well as the respec- tive ST6285B ST6285B ST6285B ST6285B ROM devices. Figure 1. Block Diagram TEST NMI INTERRUPT www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/5695-v3.htm |
STMicroelectronics | 25/05/2000 | 160.74 Kb | HTM | 5695-v3.htm |
| /D CONVERTER, 80 PINS Datasheet 8-BIT MICROCONTROLLER (MCU) WITH 8K OTP, ROM, EPROM, WITH LCD DRIVER, EEPROM AND A/D CONVERTER, 80 PINS ST6285BQ1 ST6285BQ1 ST6285BQ1 ST6285BQ1 ST Options n 12 I/O pins, fully programmable as: - Input with pull-up resistor - Input without pull . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2 PIN DESCRIPTIONS the respec- tive ST6285B ST6285B ST6285B ST6285B ROM devices. Figure 1. Block Diagram TEST NMI INTERRUPT PROGRAM PC www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/5695-v1.htm |
STMicroelectronics | 20/10/2000 | 166.32 Kb | HTM | 5695-v1.htm |