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LTC2938HDE#TRPBF Linear Technology LTC2938 - Configurable 4-Supply Monitors with Watchdog Timer; Package: DFN; Pins: 12; Temperature Range: -40°C to 125°C visit Linear Technology - Now Part of Analog Devices Buy
LTC2939HMS#TRPBF Linear Technology LTC2939 - Configurable 6-Supply Monitors with Watchdog Timer; Package: MSOP; Pins: 16; Temperature Range: -40°C to 125°C visit Linear Technology - Now Part of Analog Devices Buy
LTC2938HMS#TRPBF Linear Technology LTC2938 - Configurable 4-Supply Monitors with Watchdog Timer; Package: MSOP; Pins: 12; Temperature Range: -40°C to 125°C visit Linear Technology - Now Part of Analog Devices Buy
LTC2939IMS#TRPBF Linear Technology LTC2939 - Configurable 6-Supply Monitors with Watchdog Timer; Package: MSOP; Pins: 16; Temperature Range: -40°C to 85°C visit Linear Technology - Now Part of Analog Devices Buy
LTC2938CMS#PBF Linear Technology LTC2938 - Configurable 4-Supply Monitors with Watchdog Timer; Package: MSOP; Pins: 12; Temperature Range: 0°C to 70°C visit Linear Technology - Now Part of Analog Devices Buy
LTC2939CMS#PBF Linear Technology LTC2939 - Configurable 6-Supply Monitors with Watchdog Timer; Package: MSOP; Pins: 16; Temperature Range: 0°C to 70°C visit Linear Technology - Now Part of Analog Devices Buy

7474 ic pin configuration

Catalog Datasheet MFG & Type PDF Document Tags

pin DIAGRAM OF IC 7474

Abstract: ic 7474 pin diagram delay time for reliable operation. T Y PE 7474 74L S 74A 74S 74 NOTE: T Y P IC A L f , AX 25M H z 33M H z 100M H z T Y P IC A L SU PP LY C U R R E N T (T O T A L ) 17m A 4m A 30m A For inform , and -0 .4 m A i|L PIN CONFIGURATION LOGIC SYMBOL LOGIC SYMBOL (IEEE/IEC) 4 10 Roi I X D ,[I C P ,|T Sd Æ ° i E Qi Ï 3 vcc Ü ] *02 HD 02 T T Ic p j 3- >CP, 2- k A Qj - 9 , Signetics 7474, LS74A, S74 Flip-Flops Dual D-Type Flip-Flop Product Specification Logic
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pin DIAGRAM OF IC 7474 ic 7474 pin diagram 7474 ic pin configuration IC 7474 pin configuration pin IC 7474 logic ic 7474 pin diagram 7474N 74S74N N741S 1N916 1N3064

14 pin ic 7404

Abstract: sn 7404 n ic diagram IC l IC 2. 5.6 IC 3 IC4 IC 7. 8.9 SN 74132 SN 74107 SN 7404 SN 7474 SN 74161 OS Vss NC NC Vss , CCD Linear Image Sensor LZ2019 LZ2019 Description 2048-bit CCD Linear Image Sensor Pin , Inspection machines 8. 22 pin dual-in-line package (CERDIP) Block Diagram SHARP 452 CCD Linear Image Sensor LZ2019 1 2 5 Pin Description Symbol OS V ss V ss V ss Pin No. Pin name , Shift reg ister clock ( 1 1 Input source (test) T ransfer gate clock Pin No. 12 13 14 17 20 21
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14 pin ic 7404 sn 7404 n ic diagram pin configuration of ic 7404 7404 ic diagram ic 7474 with timing diagram IC 7404 pin diagram

14 pin ic 7404

Abstract: pin DIAGRAM OF IC 7474 to facsimile machines, optical character readers, and Inspection machines 8. 22 pin dual-in-line package (CERDIP) â  Block Diagram LZ2019 Pin Connections 452 SHARP» SHARP ELEK/ MELEC DIV 1SE 0 I 0100710 000157b Ml CCD Linear Image Sensor 1SE O I 0100710 0001575 ¿J T-41-55 LZ2019 Pin Description Pin No. Symbol Pin name Pin No. Symbol Pin name 1 OS Output transistor source 12 Vss Substrate (Aluminum , Parameter Symbol Rating Unit Pin voltage VT -0.3 to +15 V Operating temperature T Aopr -25 to +60 Storage
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CI 7474 IC 7474 ic 74132 pin DIAGRAM OF IC 7404 CI 74107 pin configuration of 7474 ic L12-1-2

ic 7483 BCD adder

Abstract: 9N01 operation is perform ed on the negative going edge o f the clock pulse. LOG IC SY M B O L 4 10 3 11 LOG IC D IA G R A M 93176/54176, 74176 Pin nu m b ers are show n fo r D IP o n ly . CO , PHILIPS FAIRCHILD PIN FOR PIN REPLACEMENT 9N74, 7474 9390,7490 9391,7491 9375,7475 9N76, 7476 9393,7493 , divide-by-tw o and divide-by-five configuration, or in the bi-quinary mode. The 9 3 1 77/54177, 74177 can be , N T IF IC A T IO N T E M P E R A T U R E ^ D E V ^ E ^ PACKAGE RANGE TYPE TYPE PACKAGE CROSS
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ic 7483 BCD adder 9N01 ic 7483 full adder function of ic 7490 IC 7490 pin configuration 9N03 93H183 93S41 93S42 93L24 93S62 93H87
Abstract: ). 6V Analog Input (Pin 1 0 ) . Vcc Reference Input (Pin 1 1 , 50°C Note 1: All voltages are with respect to ground, Pins 4,5, 12, 13. Pin numbers refer to DIL , vr jo] C urrent l,[7 9] lo P h a s e [8 PACKAGE PIN FUNCTION PIN FUNCTION 1 N/C , U C 1717 -55 125 â'C U C 3717 0 70 °C ELE C TR IC A L C H A R A C TER -
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UC1717 UC3717 UC3717S UC3717N UC1717J UC1717SP

pin diagram of ic 6116

Abstract: pin DIAGRAM OF IC 7474 JEDEC standard pin configuration - 32-pin PDIP package - 32-pin PLCC package The M8720 is a , both DIP and surface mount packages. The DIP package is a 32-pin molded dual-in-line package. The surface mount package is a 32-pin PLCC package. Package & Pin Configurations A17 PGM# 32L PDIP , , Preliminary- Product Brief Package Information 32-pin PDIP Package 32-pin PLCC Package Page 3 , Austin Road, Tsimshatsui, Hong Kong Tel: 852-2735 -1736 Fax: 852-2730 - 5260 I&C Microsystems Co
Acer Laboratories
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pin diagram of ic 6116 ACER LABORATORIES INC flash 32 Pin PLCC 2mbit Acer Laboratories EPROM 27020 features of ic 7474 27C020 M8720BRF02

full adder using ic 74138

Abstract: full adder using Multiplexer IC 74151 Advanced CHMOS circuitry features low power, high performance, and high noise immunity · Includes 68-pin , as special processors, dedicated peripheral controllers and intelligent support chips. IC count can be reduced by an order of magnitude depending on the system configuration. Power requirements can be , contains some 17 logic func tions most of which are MacroFunctions. The overall configuration of the chip , /checker 7483 - 4 bit full adder 74190 - up/down decade counter 7449 - BCD to 7 segment decoder 7474 -
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full adder using ic 74138 full adder using Multiplexer IC 74151 decoder IC 74138 TTL 74194 74151 multiplexer pin configuration of IC 74138 EP1800JC-EV1 EP1800 0UT20 0UT21 OUT22 0UT23

ALi M6759 A1

Abstract: ALI M6759 Configuration. Pin Name VDD GND P0.7-P0.0 No. (PLCC) Type Description 44 IN Power supply for internal , l l l l 8051 instruction set compatible 8 bit microcontroller 8051/8052 compatible pin out , programming 44 pin PLCC or QFP package General Description The M6759 is an 8032/8052 instruction , . -Proprietary, Confidential, Preliminary- Product Brief M6759: 8 bit MTP Micro-controller Pin Configuration T2EX T2 NC VCC AD0 AD1 AD2 AD3 P1.4 P1.3 P1.2 P1.1 P1.0 NC VCC P0.0 P0.1 P0
Acer Laboratories
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ALi M6759 A1 ALI M6759 M6759 A1 7474 pin out diagram 8052 basic external DIAGRAM OF IC 7474 1830-B 6759DS02

8052 basic

Abstract: 7474 pin out diagram : 8 bit MTP Micro-controller Pin Configuration T2EX T2 NC VCC AD0 AD1 AD2 AD3 P1.4 P1.3 P1.2 P1.1 P1.0 NC VCC P0.0 P0.1 P0.2 P0.3 44-pin PLCC Package RST RXD NC TXD /INT0 , accordingly, as shown in Pinout Configuration. Pin Name VDD GND P0.7-P0.0 No. (PLCC) Type Description , compatible 8 bit microcontroller 8051/8052 compatible pin out Complete static design, wide range of , consumption ROM Code Protection 4.5V~5.5V operation voltage, 12V programming 44 pin PLCC or QFP package
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7474 pin configuration 7474 pin diagram INTERNAL DIAGRAM OF IC 7474 8052 pin structure 3030 micro controller 7474 14 PIN

TC430

Abstract: external DIAGRAM OF IC 7474 speed-up capacitors. ORDERING INFORMATION Part No. TC430C PA TC430IJA TC430M JA Package 8-Pin Plastic 8-Pin CerDIP 8-Pin CerDIP Temperature Range 0 °C to +70°C - 2 5 ° C t o +85°C - 55°C to + 1 25°C PIN CONFIGURATION d ig ita l r r GROUND INPUT [ 2 LL TC430 T ] nc 3 »0 1 © VssE n , Diode Driver Differential Line Driver PIN Diode Driver Level Shifting Driver FUNCTIONAL DIAGRAM V DD , FAST CMOS CCD DRIVER TC430 TEST CIRCUIT VD D (+V|N) 0.1 jiF . C E RA M IC- 0.1 uF . CERAMIC
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teledyne tsc QGD73 Q0073 74S74

RETICON ccd

Abstract: IC TTL 7404 10 11 13 ] VDD 12 ] GND â'" 1 Figure 1. Pinout Configuration * (Pin 17 is N/Cfor RL0256D , Il ^ 1 -II E G r G R E a LT IC - _ O D Series Linear Family N , features very high dynam ic range. The VALUE -D device is a low er co st version w ith all th e sam e features as th e S TAN D ARD -D , but has a m axim um data rate of 10 M H z and slightly reduced dyna m ic , ig u re l show s th e pinout configuration and Figure 2 is a sim plified schem atic diagram . Figure
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RETICON ccd IC TTL 7404 L0256D L0512D L1024D L2048D RL0512DAG-011 RL0512D

pin DIAGRAM OF IC 7474 d flip flop

Abstract: western digital FD1771 . The particular motor interface is chosen by hardwiring the external pin, 3PM. ALL REFERENCE TO , data in which the data is input to the FDDATA pin and the clock is input to the FD Clock pin. The , Disk drive utilizing the FD 1771, This configuration requires the proes$or to handle all data , . external IC's but suffers in performance due to the necessity of the processor to service the F01771 every , DBOUT 1/2 7474 FD MODE C _- - WE Q FDMODE DUMP ODRDS DBIN FD MODE
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pin DIAGRAM OF IC 7474 d flip flop western digital FD1771 ic D flip flop 7474 digital ic 7474 internal circuit diagram fd1771 74ls161 counter FD1771 D1771

ic D flip flop 7474

Abstract: IC 7474 truthtable one entries we shall get: AB +BC + BC A IA A B IB B C IC C INPUTS A B B C , on the zero entries we get instead: F1 = (B + C) (A + B + C) A IA A B IB B C IC C , PLHS501. A typical 7474 type of edge-triggered D flip-flop requires 6 NAND gates as shown in Figure 7 , * * PLHS501 52­Pin PLCC Package Pin Layout * * Date: 10/13/93 Time: 16:42:21 , input/output pin arrangement. Also recognizing that all logic functions could be built from the
Philips Semiconductors
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IC 7474 truthtable philips for ic 7474 7474 D flip-flop circuit diagram PLHS502 IC 7474 flipflop 7474 D flip-flop

logic ic 7676 pin diagram

Abstract: XC6505A CHARACTERISTICS 1/24 XC6505 Series PIN CONFIGURATION *The dissipation pad for the USP-6C package should , when the L-level signal (IC internal circuit shutdown signal) of the CE pin is input. The CL discharge , Input GENERAL DESCRIPTION Even the XC6505 series is a low power consumption such as 5.5 A, the IC , result the VOUT pin quickly returns to the VSS level. The over current protection circuit and the , (No. 5) pin. PIN ASSIGNMENT PIN NUMBER PIN NAME FUNCTIONS 4 VIN Power Input 5
Torex Semiconductor
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logic ic 7676 pin diagram XC6505A ETR0356-002

eb 102H

Abstract: Controller, Serial/Parallel Ports, Configuration RAM, and Real Time Clock Integrates Variety of System , effort, and form factor constraints by replacing 50 IC devices in an equivalent IBM system. The 82304 , on the 82304â'™s V G A SU # pin. Also, the 82304 integrates bit 0 of port 3C3H, which is used to , MicroChannel architectureâ'™s system feedback function. R E A L TIME C L O C K AND CONFIGURATION RAM S U P , FH . A s COM M2, the port is decoded from 2F8 -2 F FH . Configuration is done via the integrated
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eb 102H RAMD11

82306

Abstract: 74590 Package High-lntegration-The 82304, 82303 and 82077 Floppy Disk Controller Replace 50 IC's in IBM Design Supports I/O Peripherals . . . Keyboard/ Mouse Controller, Serial/Parallel Ports, Configuration , , significantly reduce system cost, design effort, and form factor constraints by replacing 50 IC devices in an , on the 82304's V G A S U # pin. Also, the 82304 integrates bit 0 of port 3C3H, which is used to en a , the MicroChannel architecture's system feedback function. REAL TIME CLOCK AND CONFIGURATION RAM
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82306 74590 pin configuration of ic 74373 8259 Programmable Peripheral Interface pin diagram of ic 74373 IC 8259 internal pin diagram RAMD12
Abstract: 3 BUS9 3BUS8 3 QND 3 BUS7 3 BUS6 3 BUSS 3 8US4 3 BUS3 Figure 2. Pin Configuration 7-469 , Figure 5. Talker/Listener Control Configuration Table 3. Mode 0 Pin Description Pin Symbol No. Type , . Talker/Listener Data Configuration 7-472 AFN-00825C ¡nteT 8293 Table 4. Mode 1 Pin , ­ dicate the condition of readiness of de­ v ic e ^ ) to accept data. This pin is TTL compatible. SRQ , input in Mode 2. 7-474 AFN-00825C 8293 P E lliy fiilO G M W Table 5. Mode 2 Pin -
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IEEE-488 AFN-00625C

pin configuration of d flip flip 7474

Abstract: 7474 ic pin configuration S ® N -C h a nn e l M OS T ech n o lo g y PIN CONFIGURATION MRA 1 I CLKINA 2 I CLKOUTA 3 I , in p u ts are designed fo r ze ro -h o ld -tim e (e.g. 7474). A " c lo c k o u t" pin provides gated , setting o f the e rro r flag. A separate reset pin is provided fo r the e rro r flag. No e rro r is , ning flag resumed. ENAA 6 ( MODEA 7 [ EFLGA 8 I EFLGRA 9 | G N D 10 r PACKAGE: 20 pin D.I.P , 173 SECTION ill DESCRIPTION OF PIN FUNCTIONS PIN NO. 1 NAME MASTER RESET-A SYM BOL
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pin configuration of d flip flip 7474 CRC-32

IC 7400

Abstract: pin DIAGRAM OF IC 7474 d flip flop Start Convert input (pin 1). In this configuration, Status (Start Convert) will go low at the end of a , FEATURES â'¢ 24 Pin Hermetically Sealed Leadless Package â'¢ Fast 13/^sec Conversion Time â , +125 °C Available Fully Screened and Processed to MIL-STD-883, Method 5008. 24 PIN LEADLESS PACKAGE , Product "E", "E/B" Models "H", "H/B" Models Storage Temperature Range + 15V Supply ( + Vcc, Pin 15) - 15V Supply (-Vcc, Pin 13) + 5V Supply (+Vdd, Pin 2) Analog Input (Pin 14) Digital Inputs (Pins 1, 24) Digital
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IC 7400 IC-7400 IC7400 7474 D flip flop free IC TTl 7474 free features of ic 7474 d flip flop MN5610 12-BIT MN5616

truth table for ic 74138

Abstract: ALU IC 74183 cycles Elim ination of un u sed gates A utom atic pin and p art assignm ents SALSA logic m inim ization , , 7474, 7476, 7478, 74173, 74174, 74175, 74273, 74374 FREQDIV 7475, 7477, 74116, 74259, 74279, 74373 , . If a pin assignm ent is specified, the Fitter m atches the request. If no pin assignm ents are , achieved, the Fitter generates a U tilization R eport (.RPT) that d ocum ents macrocell and pin assignm ents, in p u t and o u tp u t pin nam es, and buried registers, as well as any u n u sed resources. At
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truth table for ic 74138 ALU IC 74183 16CUDSLR IC 74151 diagram and truth table 74183 alu 74147 pin diagram and truth table
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