NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Catalog Datasheet Results | Type | Document Tags |
| Abstract: ) NOTE: The letter in parenthesis indicates the location of the zero bit in the shift register. D.P. = , Shift Register The 74195 shift left/shift right shift register is the heart of the auto-ranging logic. , DIRECTION OF SHIFT MUST BE REVERSED FOR OHMS MEASUREMENT 2N4119 2N4119 V- FIGURE 5. AUTO-RANGING SCHEMATIC , 7474 is clocked into the register. This occurs 900 counts after autozero begins (D1 strobe). The , digit mode when the 7474 is cleared. Eight hundred counts later the data is strobed into the register ... | Original |
8 pages, |
TTL 7474 precision rectifier zestron 278 74121 application as pulse generator AN028 intersil data sheet 2N2007 74195 TTL shift register 7447 decade counter 7474 D flip-flop circuit diagram zestron reed relay 7474 shift register transistor 2N2007 ICL7103A/ICL8052A AN028 ICL7103A/ICL8052A abstract |
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| Abstract: ) NOTE: The letter in parenthesis indicates the location of the zero bit in the shift register. D.P. = , Shift Register The 74195 shift left/shift right shift register is the heart of the auto-ranging logic. , DIRECTION OF SHIFT MUST BE REVERSED FOR OHMS MEASUREMENT 2N4119 2N4119 V- FIGURE 5. AUTO-RANGING SCHEMATIC , 7474 is clocked into the register. This occurs 900 counts after autozero begins (D1 strobe). The , digit mode when the 7474 is cleared. Eight hundred counts later the data is strobed into the register ... | Original |
8 pages, |
TTL 7474 AN028 7474 shift register 7474 PIN DIAGRAM 7474 D flip-flop circuit diagram application notes 74121 zestron reed relay 74195 shift register 2N4119 74121 application as pulse generator 7474 AN028 intersil 7474 D flip-flop ICL7103A/ICL8052A AN028 ICL7103A/ICL8052A abstract |
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| Abstract: Counter 8-Bit Shift Register 8-Bit Shift Register Quad D-Type Flip-Flop Dual 4-Bit Binary Counter , Flip-Flop 8-Bit Shift Register 8-Bit Shift Register 4-Channel Analogue Multiplexor Decade Counter BCD Counter ( Presettable ) Quad AND/OR Select Gate 14-Stage Ripple Counter 8-Stage Shift Register Divide , Counter Quad 2-Input XOR Gate 7-Segment Display Decade Counter 4-Stage Shift register Similar , ( Schmitt trigger ) 8-Stage Shift Register Dual Monostable Multivibrator 8-Bit Addressable Latch Hex ... | Original |
12 pages, |
decoder 7448 74373 74138 Decoder 74241 7493 flip-flop counter 74244 4070 CMOS XOR 7476 counter 4001 4011 cmos 74374 7476 J-K Flip-Flop 7408, 7404, 7486, 7432 74373 cmos dual s-r latch 7490 Decade Counter datasheet abstract |
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| Abstract: an extensive library of 7400 series latch and register functions 7474 7498 7409 74194 , comes equipped with a dedicated D-type register that can also be configured for J-K or Toggle , Thus, for cases where one register is feeding another, the pASIC logic cell is capable of integrating , followed by the dedicated cell register. 5-6 QAN1 FIGURE 6 A cell design for two edge-triggered registers in a single cell. This allows an 8-bit shift register to be implemented in only 4 logic cells. ... | Original |
6 pages, |
integrated circuit 74105 datasheet 7400 application notes 7400 series 74104 7474 for shift register which logic family is 7474 7498 4 bit 74395 7491 8-bit multiplexor 74171 74105 74194 shift register QL8X12B QL8X12B abstract |
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| Abstract: register. Data moves on the positive edge of theclock.andall clocked inputs are designed for zero-hold-time , last flag bit has been shifted into the shift register of the COM 8004, CLKOUTA will be held high until , (which has been stored in the shift register) is shifted out. The CRC check data is inverted before this , into the shift register. Data will pass through the COM 8004 without effect until a FLAG is received. CRC Check (Reception) When the last bit of a closing flag enters the shift register, ERRCHK will go ... | OCR Scan |
6 pages, |
CRC-32 7474 shift register CRC-32 abstract |
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| Abstract: counter 8-bit serial-out shift register Divide by twelve counter 4-bit binary counter 4-bit serial/par-in/par-out shift register 5-bit serial-in parallel-out shift register Gated J-K master slave flip , parallel output serial shift register 8-bit serial/parallel input shift register Hex D-type flip flops , shift register 4-bit parallel access shift register Preset. counters/latches binary Dual monostable , bidirectional universal shift register Quad 2-input multiplexers with storage 8-bit bidirectional uni.shift ... | Original |
5 pages, |
FZJ115 74hc4000 astable multivibrator 74LS14 ic D flip flop 7474 ic 74ls83 FZL145S IC 74LS192 FZH195 FZJ125 74LS104 FZH265B FZJ105 FZH115 FZH205 74INTEGRATED 74INTEGRATED abstract |
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| Abstract: BSHFT4 BSHFT8 BSHFT16 BSHFT16 LSHFT2Q2 Description 4-bit Shift Register w/ load, enable, clear 8-bit Shift Register w/ load, enable, clear 16-bit Shift Register w/ load, enable, clear 4-bit Bi-Directional Shift Register w/ load, enable, clear 8-bit Bi-Directional Shift Register w/ load, enable, clear 16-bit Bi-Directional Shift Register w/ load, enable, clear 2-bit Dual Shift Register w/ clear , quad 2-input XOR gates 4-bit true/complement elements 8-bit shift register 4-bit data selector ... | Original |
60 pages, |
TTL 7474 74139 Dual 2 to 4 line decoder d-latch by using D flip-flop 7474 8 shift register by using D flip-flop 74823 FULL ADDER schematic of TTL XOR Gates 7474 shift register CI 74139 TTL 7400 full subtractor circuit using nor gates vhdl code for 74194 datasheet abstract |
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| Abstract: 4-bit Shift Register w/ load, enable, clear Load x Enable x Clear x Direction LSB->MSB SHFT8 8-bit Shift Register w/ load, enable, clear x x x LSB->MSB SHFT16 SHFT16 16-bit Shift Register w/ load, enable, clear 4-bit Bi-Directional Shift Register w/ load, enable, clear 8-bit Bi-Directional Shift Register w/ load, enable, clear 16-bit Bi-Directional Shift Register w , action-the state of the register is unchanged. The right shift function loads each bit from its RSI input ... | Original |
56 pages, |
74171 encoder 74174 74194 shift register pin configuration of d flip flip 7474 7474 j-k flip flop 74138 full subtractor circuit using nor gates TTL 74139 7400 QUAD Nor 74594 vhdl code for 8-bit BCD adder data sheet 74139 datasheet abstract |
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| Abstract: ) SB P 2¿ CCD Shift Register V RD2 Even V Video LR R N VRec VSUB N-2 , simultaneously switched through transfer gates, øT, into one of two CCD analog shift registers for readout. The , wavelength in Figure 7. D Series devices require two complimentary shift register clocks, ø1 and ø2, a , CLK Q 7474 D Q 100 ½ 7404 7408 10 pF 100 ½ 10 pF Figure 10. Drive Circuit for D , , allows the designer to select just LIGHT. the right device for a particular application. Typical ... | Original |
8 pages, |
photodiode reticon reticon photodiode array RL1024DKQ-111 RL0512DKQ rl1024dag ttl family 7404 7408 12V 7408 ttl family RL2048DKQ-111 RETICON RL 1024 RL0256DAG-111 7404 gate diagram RETICON datasheet abstract |
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| Abstract: bidirectional Data Register which acts as a parallel buffer for read or write operations, and receives the , register are transferred to the shift register at which time the DRO line is set. Four separate Data , ENABLE IRE (SEEFIGURfi2-61 1/2 7474 C 'BITB NOT USED (COULD BE USED FOR PARITY CHECKING IF , Address Marks for Index,1 D, and Data are identified by a particular pattern not repeated in the , pulses over the lines PH 1, PH2, and PH3 for 3 phase stepping motors or by sending a level over the PH2 ... | Original |
12 pages, |
external DIAGRAM OF IC 7474 floppy Stepping Motors diagram western digital FD1771 internal circuit of ic 7474 underrun floppy diskette 1771 floppy fr1502 western digital data separator 7474 D flip flop pin DIAGRAM OF IC 7474 d flip flop INTERNAL DIAGRAM OF IC 7474 FD1771 FD1771 abstract |
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| printed when a the driver failed to use the PCI BIOS for read and write the configuration registers +-+ | d21xCAPS_ driver for SCO license. The information in this manual is furnished for informational use only, is subject Intel Corporation. Intel Corporation assumes no responsibility or liability for any errors supported for the following devices: Intel 21040 Intel 21040 www.datasheetarchive.com/download/12167383-223044ZC/sco_430.zip (TSUL_INS.TXT) |
Intel | 07/07/1998 | 358.32 Kb | ZIP | sco_430.zip |
| _pullup .ends * * * *SRC=74AS194 74AS194 74AS194 74AS194;74AS194 74AS194 74AS194 74AS194;TTL;74ASxx;4-bit shift register *SYM=T74194 T74194 T74194 T74194 *74AS194 74AS194 74AS194 74AS194 4-BIT BIDIRECTIONAL UNIVERSAL *SHIFT REGISTERS * .subckt 74AS194 74AS194 74AS194 74AS194 clk clrb s1 s0 sl sr ;74ASxx;4-bit shift register *SYM=T74195 T74195 T74195 T74195 *74AS195 74AS195 74AS195 74AS195 4-BIT PARALLEL-ACCESS SHIFT REGISTERS ) * * * *DEVELOPPED FOR INTUSOFT BY JEAN-CLAUDE MBOLI * *Phone:(33) 4 76 44 43 30 Fax:(33) 4 76 44 43 52 _or(rise_delay=3.5n fall_delay=3.5n) .ends * * * *SRC=74AS74;74AS74;TTL;74ASxx;D Flip www.datasheetarchive.com/files/spicemodels/misc/modelos/spice_complete/74as.lib |
Spice Models | 18/04/2010 | 15.28 Kb | LIB | 74as.lib |
| register as it is write only. For this reason, the DWR contents should not be changed while exe- cuting description for additional informa- tion. The DRBR register is not modified when an interrupt or a subroutine occurs. Notes : Care is required when handling the DRBR register as it is write only. For -chip peripherals via the serial data bus and indirectly, for interrupt purposes, through the control registers an MS-DOS PC via a parallel port) DEVICE SUMMARY (See end of Datasheet for Ordering Information www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/4568-v2.htm |
STMicroelectronics | 11/01/2000 | 160.94 Kb | HTM | 4568-v2.htm |
| register as it is write only. For this reason, the DWR contents should not be changed while exe- cuting description for additional informa- tion. The DRBR register is not modified when an interrupt or a subroutine occurs. Notes : Care is required when handling the DRBR register as it is write only. For -chip peripherals via the serial data bus and indirectly, for interrupt purposes, through the control registers an MS-DOS PC via a parallel port) DEVICE SUMMARY (See end of Datasheet for Ordering Information www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/4568-v3.htm |
STMicroelectronics | 25/05/2000 | 160.89 Kb | HTM | 4568-v3.htm |
| Mode Control Register sets PB7 as timer output function. PB6-PB7 can also sink 20mA for direct LED . For instance, when addressing loca- tion 0040h of the Data Space, with 0 loaded in the DWR register is required when handling the DWR register as it is write only. For this reason, the DWR contents bank region. Refer to the Data Space description for additional informa- tion. The DRBR register is DRBR register as it is write only. For this reason, it is not allowed to change the DRBR contents www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/4568-v1.htm |
STMicroelectronics | 20/10/2000 | 167.04 Kb | HTM | 4568-v1.htm |
| the DWR register (as most significant bits), as illustrat- ed in 5 below. For instance, when register as it is write only. For this reason, the DWR contents should not be changed while exe- cuting an description for additional informa- tion. The DRBR register is not modified when an interrupt or a subroutine occurs. Notes : Care is required when handling the DRBR register as it is write only. For this reason, it -chip peripherals via the serial data bus and indirectly, for interrupt purposes, through the control registers. 2 www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/4568.htm |
STMicroelectronics | 02/04/1999 | 158.29 Kb | HTM | 4568.htm |
| ;54ASxx;4-bit shift register *SYM=T74194 T74194 T74194 T74194 *54AS194 54AS194 54AS194 54AS194 4-BIT BIDIRECTIONAL UNIVERSAL *SHIFT REGISTERS * * Copyright Intusoft 1997 * All Rights Reserved * * * ADVANCED SCHOTTKY (AS) DIGITAL LIBRARY BASED ON THE * * TEXAS INSTRUMENTS DATA BOOK (Volume 2) * * * *DEVELOPPED FOR INTUSOFT BY JEAN-CLAUDE MBOLI * *Phone:(33) 4 76 44 43 30 Fax:(33) 4 76 44 43 52 * * * *SRC=54AS74 54AS74 54AS74 54AS74;54AS74 54AS74 54AS74 54AS74;TTL;54ASxx;D Flip-Flop *SYM=T7474 *54AS74 54AS74 54AS74 54AS74 DUAL D-TYPE POSITIVE www.datasheetarchive.com/files/spicemodels/misc/modelos/spice_complete/54as.lib |
Spice Models | 18/04/2010 | 11.8 Kb | LIB | 54as.lib |
| used to shift in the CI data. For each mode the first CCLK edge after CS fall - ing edge can be SUITABLE FOR ISDN, PAIR GAIN AND DECT APPLICATIONS MEETS OR EXCEEDS ETSI EUROPEAN STANDARD SINGLE 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal register description 4/74 GENERAL DESCRIPTION STLC5412 STLC5412 STLC5412 STLC5412 is a complete monolithic transceiver for ISDN Basic access channel of 16 kbit/s plus an additional 4 kbit/s M channel for loop maintenance and other user www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/5634-v2.htm |
STMicroelectronics | 25/05/2000 | 152.33 Kb | HTM | 5634-v2.htm |
| possible for the microprocessor to re - ceive the required register content after several other pending : Monitor) is used for transferring most of the control and status registers; the fourth octet (SC C/I channel is used for TXACT and RXACT registers write and read operation. However, it is possible SINGLE CHIP 2B1Q LINE CODE TRANSCEIVER SUITABLE FOR ISDN, PAIR GAIN AND DECT APPLICATIONS MEETS OR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal register description www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/5634-v1.htm |
STMicroelectronics | 02/04/1999 | 150.49 Kb | HTM | 5634-v1.htm |
| used to shift in the CI data. For each mode the first CCLK edge after CS fall - ing edge can be : Monitor) is used for transferring most of the control and status registers; the fourth octet (SC a time. Note: Special format is used for EOC channel. Read cycle When UID has a register content acknow - ledgement. C/I channel The C/I channel is used for TXACT and RXACT registers write and read CHIP 2B1Q LINE CODE TRANSCEIVER SUITABLE FOR ISDN, PAIR GAIN AND DECT APPLICATIONS MEETS OR EXCEEDS www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/5634.htm |
STMicroelectronics | 20/10/2000 | 157.11 Kb | HTM | 5634.htm |