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74741-163LF Amphenol FCi Board Connector, 30 Contact(s), 5 Row(s), Male, Straight, 0.079 inch Pitch, Press Fit Terminal, Locking, Receptacle, LEAD FREE visit Digikey
74741-101LF Amphenol FCi Board Connector, 30 Contact(s), 5 Row(s), Male, Straight, 0.079 inch Pitch, Press Fit Terminal, Locking, Plug, LEAD FREE visit Digikey
74741-172LF Amphenol FCi Board Connector, 30 Contact(s), 5 Row(s), Male, Straight, 0.079 inch Pitch, Press Fit Terminal, Locking, Plug, LEAD FREE visit Digikey
74743-101LF Amphenol FCi Board Connector, 120 Contact(s), 5 Row(s), Male, Straight, 0.079 inch Pitch, Solder Terminal, Locking, LEAD FREE visit Digikey
74742-107LF Amphenol FCi Board Connector, 60 Contact(s), 5 Row(s), Male, Straight, 0.079 inch Pitch, Solder Terminal, Locking, Plug, LEAD FREE visit Digikey
74742-131LF Amphenol FCi Board Connector, 60 Contact(s), 5 Row(s), Male, Straight, 0.079 inch Pitch, Solder Terminal, Locking, Plug, LEAD FREE visit Digikey

7474 for shift register

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: -Bit Shift Register 8-Bit Shift Register Quad D-Type Flip-Flop Dual 4-Bit Binary Counter Dual Monostable , Quad 2-Input NAND Gate Dual 4-Input NAND Gate Dual D-Type Flip-Flop 8-Bit Shift Register 8-Bit Shift Register 4-Channel Analogue Multiplexor Decade Counter BCD Counter ( Presettable ) Quad AND/OR Select Gate 14-Stage Ripple Counter 8-Stage Shift Register Divide by 8 Counter Triple 3-Input NAND , -Segment Display Decade Counter 4-Stage Shift register Similar Devices 7402 7404 / 7405 / 7406 / 7414 -
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74573 74574 7486 XOR GATE 7486 full adder latch 74574 7408, 7404, 7486, 7432
Abstract: ) NOTE: The letter in parenthesis indicates the location of the zero bit in the shift register. D.P. = , Shift Register The 74195 shift left/shift right shift register is the heart of the auto-ranging logic , DIRECTION OF SHIFT MUST BE REVERSED FOR OHMS MEASUREMENT 2N4119 V- FIGURE 5. AUTO-RANGING SCHEMATIC , 7474 is clocked into the register. This occurs 900 counts after autozero begins (D1 strobe). The , digit mode when the 7474 is cleared. Eight hundred counts later the data is strobed into the register Intersil
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ICL7103A 7474 D flip-flop zestron reed relay 2N2007 application notes 74121 7474 D flip-flop circuit diagram ICL7103A/ICL8052A AN028 ICL8052A ISO9000
Abstract: ) NOTE: The letter in parenthesis indicates the location of the zero bit in the shift register. D.P. = , Shift Register The 74195 shift left/shift right shift register is the heart of the auto-ranging logic , DIRECTION OF SHIFT MUST BE REVERSED FOR OHMS MEASUREMENT 2N4119 V- FIGURE 5. AUTO-RANGING SCHEMATIC , 7474 is clocked into the register. This occurs 900 counts after autozero begins (D1 strobe). The , digit mode when the 7474 is cleared. Eight hundred counts later the data is strobed into the register Intersil
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ICL7103 74121 application as pulse generator zestron 278 transistor 2N2007 Low Cost Digital Panel Meter Designs AN028 intersil
Abstract: Decade counter 8-bit serial-out shift register Divide by twelve counter 4-bit binary counter 4-bit serial/par-in/par-out shift register 5-bit serial-in parallel-out shift register Gated J-K master , -bit parallel output serial shift register 8-bit serial/parallel input shift register Hex D-type flip flops , shift register 4-bit parallel access shift register Preset. counters/latches binary Dual monostable , -bit bidirectional universal shift register Quad 2-input multiplexers with storage 8-bit bidirectional uni.shift Electro Value
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FZH115B fzh261 FZK105 FZH131 FZJ111 FZH115 74INTEGRATED 16-DIL
Abstract: also offers an extensive library of 7400 series latch and register functions 7474 7498 7409 , configured for J-K or Toggle operation. These dedicated registers will typically satisfy the register , available. Thus, for cases where one register is feeding another, the pASIC logic cell is capable of , followed by the dedicated cell register. 5-6 QAN1 FIGURE 6 A cell design for two edge-triggered registers in a single cell. This allows an 8-bit shift register to be implemented in only 4 logic cells QuickLogic
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74171 7478 J-K Flip-Flop 7478 jk 7400 series logic ICs 74594 7498 4 bit QL8X12B QL8X12
Abstract: -bit parallel-out storage register. A single pin serves either as an input for serial entry or as a TRI STATE* serial output. In the Serial-out mode, the data recir culates in the shift register. By means of a separate clock, the contents of the shift register are transferred to the stor age register for parallel outputting. The contents of the stor age register can also be parallel loaded back into the shift register. A , 673A National Semiconductor 74F673A 16-Bit Serial-ln, Serial/Parallel-Out Shift Register -
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74F673ASPC 7474 shift register 7472 PIN DIAGRAM 7473 national 7475 tristate buffer F673A 74F673APC 74F673ASC 5RG16 10Z11
Abstract: Microprocessor Bus Port with Programmable Control. · Dual Byte-Wide Input and Output Register's for , continuous bit rate division without external intervention. Two 74194 shift register macro functions , register. Two 74373 output latches provide a mechanism for processor access to current bit rate count values or current shift register contents. The upper right corner of the schematic shows a controlling , either the SSI or MSI level: for example, individual 7474 elements may be used in design entry, or 74374 -
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74194 shift register 74377 register logicaps 74191 counter 74377 altera logicaps TTL library EPB1400
Abstract: input multiplexer 74194 - universal bidirectional shift register 74180 - 8 bit parity generator , EP1800JC-EV1 74194 (SHIFT REGISTER) I (GND) j- - SLSI (GND) j- SRSI (GND) j- (GND) *- (GND) j , contain 14 MSI TTL functions for user evaluation. · May be erased for other uses upon completion of , variety of logic functions for the purpose of evaluating the high density line of erasable pro grammable , purchased as a pre-programmed EP1800 EPLD along with a suitable mounting socket for breadboarding. Ordering -
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full adder using ic 74138 full adder using Multiplexer IC 74151 decoder IC 74138 TTL 74194 74151 multiplexer pin configuration of IC 74138 0UT20 0UT21 OUT22 0UT23 OUT10 0UT12
Abstract: shift register. Data moves on the positive edge of theclock.andall clocked inputs are designed for , last flag bit has been shifted into the shift register of the COM 8004, CLKOUTA will be held high until , (which has been stored in the shift register) is shifted out. The CRC check data is inverted before this , into the shift register. Data will pass through the COM 8004 without effect until a FLAG is received. CRC Check (Reception) When the last bit of a closing flag enters the shift register, ERRCHK will go -
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CRC-32 8004 FD 300 fd300
Abstract: C ounter (74LS169) MODULO LINEAR FEEDBACK SHIFT REGISTER C3LSR C4LSR C5LSR C6LSR C7LSR C8LSR M odulo M odulo Modulo M odulo Modulo M odulo 7, Linear Feedback Shift Register 15, Linear Feedback Shift Register 31, Linear Feedback Shift Register 63. Linear Feedback Shift Register 127, Linear Feedback Shift Register 255, Linear Feedback Shift Register CLOCK PRESCALER PS2 PS3 PS4 Divide b y , voltage "L " Output voltage Input Current Output Current for off state Power Supply Current IO H = -4 m A -
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RSC-15 M4017C M4028C 74LS179 74LS198 74LS80 74ls198*- 74LS150 74LS94 OAI32 0001L3M TEK-044-9004 NOR03 NAND08 D410L
Abstract: Register w/ load, enable, clear 8-bit Shift Register w/ load, enable, clear 16-bit Shift Register w/ load, enable, clear 4-bit Bi-Directional Shift Register w/ load, enable, clear 8-bit Bi-Directional Shift Register w/ load, enable, clear 16-bit Bi-Directional Shift Register w/ load, enable, clear 2-bit Dual Shift Register w/ clear Load x Enable x Clear x Direction LSB->MSB x x x , register is unchanged. The right shift function loads each bit from itsRSI input, while the left shift QuickLogic
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vhdl code for 74154 4-to-16 decoder vhdl code for 74194 74138 full subtractor 3-8 decoder 74138 vhdl code for 8-bit BCD adder 74823 FULL ADDER
Abstract: 4-bit Shift Register w/ load, enable, clear Load x Enable x Clear x Direction LSB->MSB SHFT8 8-bit Shift Register w/ load, enable, clear x x x LSB->MSB SHFT16 16-bit Shift Register w/ load, enable, clear 4-bit Bi-Directional Shift Register w/ load, enable, clear 8-bit Bi-Directional Shift Register w/ load, enable, clear 16-bit Bi-Directional Shift Register w/ load, enable , register is unchanged. The right shift function loads each bit from its RSI input, while the left shift -
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74138 decoder 3-input-XOR data sheet 74139 7400 QUAD Nor TTL 74139 74138
Abstract: length. All received words in the Data register are transferred to the shift register at which time the , ENABLE IRE (SEEFIGURfi2-61 1/2 7474 C 'BITB NOT USED (COULD BE USED FOR PARITY CHECKING IF , Address Marks for Index,1 D, and Data are identified by a particular pattern not repeated in the , pulses over the lines PH 1, PH2, and PH3 for 3 phase stepping motors or by sending a level over the PH2 , respectively. When reading the serial data from the disk the FD 1771 will look for the desired sector to be -
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pin DIAGRAM OF IC 7474 d flip flop western digital FD1771 ic D flip flop 7474 fd1771 74ls161 counter floppy disk Stepping Motors connection FD1771 D1771
Abstract: as microcontrollers (8051, 6803) and shift registers. See Figure 4 for the timing diagram. The serial , must be inverted before connecting to the SCK input. The internal shift register converts the serial , signal is detected. Once received, the data word will be transferred from the SSI receive shift register , program should read the data from RX before a new data word is transferred from the receive shift register , 135 215 fCLK = 1.28MHz. See Control Inputs Synchronization. :!:5% for Specified :!:5% for Specified Analog Devices
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PD7720 C11j ao37 LPD7720 OP Amplifier A30
Abstract: ) SB P 2¿ CCD Shift Register V RD2 Even V Video LR R N VRec VSUB N-2 N , simultaneously switched through transfer gates, øT, into one of two CCD analog shift registers for readout. The , wavelength in Figure 7. D Series devices require two complimentary shift register clocks, ø1 and ø2, a , CLK Q 7474 D Q 100 ½ 7404 7408 10 pF 100 ½ 10 pF Figure 10. Drive Circuit for D , , allows the designer to select just LIGHT. the right device for a particular application. Typical PerkinElmer Optoelectronics
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RL0256DAG-111 RL1024DKQ-111 RL2048DKQ-111 7404 not gate lm 7404 LM 7408 RL2048dag 7408 12V lm 7404 and pin configuration RL0256D RL0512D RL1024D RL2048D RL0512DAG-111
Abstract: . Inputs and Serial Output . 1-286 247 8-Bit Shift Register with Gated Serial · - Inputs and Serial , &8 &8 &8 .' · · · 1-286 247 1-286 247 1-287 1-287 1-287 1-287 247 247 247 247 8-Bit Shift Register , Clear 1-285 249 1-285 249 1-285 1-285 1-285 1-285 249 249 249 249 4-Bit Shift Register Dual , 74H106 . 74107 74C107 74LS107 ' 74H108. 74109 4-Bit Parallel In/Parallel Out Shift Register 1-287 247 4-Bit Parallel In/Parallel Out Shift Register 1-287 247 4-Bit Parallel In/Parallel Out Shift -
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74LS324 7400 TTL 74LS327 7402, 7404, 7408, 7432, 7400 80C96 74251 multiplexer G0G513S 74C00 74H00 74LS00 74S00 74H01
Abstract: ARRAY 5G F C E L L LIST [~BLOClT SHIFT REGISTER SR41 SR42 M95C SR43 SR44 SR45 SR46 SR47 M94C , CMP8 4 Bit Shift Register 4 Bit Shift Register, Clear Direct 4 Bit Shift Register (74LS95) 4 Bit Shift Register, Set Direct 4 Bit Shift Register, Synchronous ParallelLoad 4 Bit Shift Register, Synchronous ParallelLoad and Clear 4 Bit Shift Register, A synchronous Parallel Load 4 Bit Shift Register, Sync Clear 4 Bit Shift Register (7494) 4 Bit Parallel Access Shift Register (74179) 4 Bit -
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16 bit comparator using 74*85 IC 74LSI39 shift register 74ls96 4 bit synchronous ic 7476 74ls91 counter OAI211 EKG-3-8805 BSC-15 NAND04 AOI22 AOI24 M125C
Abstract: and shift register, thoU and taelup are 2.16V - 0.64V = 95 mV/ns 15 ns Assuming a linear rise , same logic as Fig. 4a. The same analysis holds for the SN7400 series. â¡ 8-Blt Serial Register Shifts Unpredictably Problem: An 8-bit shift register (SN7491A) transfers all of its stored data to , : The shift register in question is an eight-stage serial-in/ serial-out shift register. Its R-S , frequently encountered and its solution. The final item is a summary of guidelines for 54/74 TTL design -
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CA129 S-102
Abstract: complimentary shift register clocks, 01 and 02, a transfer gate pulse, 0T, for normal operation. An additional , through transfer gates, 0j, into one of two CCD analog shift registers for readout. The odd numbered , the right device for a particu lar application. Typical applications include optical character , slightly reduced dynamic The FAST-D device is specified for operation at data rates up to 30 MHz. The LOLIGHT-D device is a wide-aperture version featuring 13 |*m x 26 nm pixels for higher photo sensitivity -
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RL0256DAG-011 RL0512DAG-011 RL1024DAG-011 RL2048DAG-020 RETICON RL 1024 STR 6656 RETICON RL0512DAG011 RL0512DKQ RL0512DAG RL2048DAG-011 RL0256DAG-020 RL0512DAG-020
Abstract: analog shift registers fo r readout. The odd num bered d iodes are sw itched into one register and the , devices require tw o com plim entary shift register clocks, 01 and 02 , a tra n sfe r gate pulse, 0 T, fo , select just th e right device for a particular a pplica­ tion. Typical a pplications include optical ch , is a w ide-aperture version featuring 13 nm x 26 nm pixels for higher photo sensitivity. Functional Description The sensing e lem ents for the D Series Linear C C PD s are a row of diffused p-n -
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IC TTL 7404 RETICON ccd L0256D L0512D L1024D L2048D RL0256DAG-021 RL0512DAG-021
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