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Part Manufacturer Description Datasheet BUY
SN7474J-00 Texas Instruments TTL/H/L SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP14, CERAMIC, DIP-14 visit Texas Instruments
SN7474N-10 Texas Instruments TTL/H/L SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP14, PLASTIC, DIP-14 visit Texas Instruments
SN7474N3 Texas Instruments Dual D-Type Positive-Edge-Triggered Flip-Flops With Preset And Clear 14-PDIP 0 to 70 visit Texas Instruments
SN7474DR Texas Instruments Dual D-Type Positive-Edge-Triggered Flip-Flops With Preset And Clear 14-SOIC 0 to 70 visit Texas Instruments
SN7474J Texas Instruments TTL/H/L SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP14, CERAMIC, DIP-14 visit Texas Instruments
SN7474N-00 Texas Instruments IC TTL/H/L SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP14, PLASTIC, DIP-14, FF/Latch visit Texas Instruments

7474 D flip-flop

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: auto-ranging is necessary. 6 The 7474 D flip-flop controls the 3 1/2 - 4 1/2 digit mode of the ICL7103A , Building an Auto-Ranging DMM with the ICL7103A/ICL8052A A/D Converter Pair Application Note , errors to the system. The development of LSI A/D converters has carved the pathway for a new category , ICL8052A A/D pair represents an excellent example of this new breed of converter products available today , Application Note 028 Basic Circuitry The basic circuit for the ICL7103A/ICL8052A A/D converter remains Intersil
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zestron reed relay 7474 for shift register 2N2007 application notes 74121 7474 D flip-flop circuit diagram zestron 278 AN028 ISO9000
Abstract: auto-ranging is necessary. 6 The 7474 D flip-flop controls the 3 1/2 - 4 1/2 digit mode of the ICL7103A , Building an Auto-Ranging DMM with the ICL7103A/ICL8052A A/D Converter Pair Application Note , errors to the system. The development of LSI A/D converters has carved the pathway for a new category , ICL8052A A/D pair represents an excellent example of this new breed of converter products available today , Application Note 028 Basic Circuitry The basic circuit for the ICL7103A/ICL8052A A/D converter remains Intersil
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ICL7103 74121 application as pulse generator transistor 2N2007 Low Cost Digital Panel Meter Designs AN028 intersil 7474 shift register
Abstract: FAIRCHILD TTL/SSI â'¢ 9N74/5474, 7474 DUAL D TYPE EDGE TRIGGERED FLIP-FLOP / DESCRIPTION â'" The 9N74/5474, 7474 are edge triggered dual D type flip-flops with direct clear and preset inputs and both , positive going pulse. After the clock input threshold voltage has been passed, the data input (D) is locked out and information present will not be transferred to the output. The 9N74/5474, 7474 have the same , IEDIEE IBID D RD Q CP Sp Q wQi , L CP So Q >1 S LJUJLllLJLillilLJ Roi D1 CPi Soi Q1 -
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7474 truth table 7474 ttl 7474 Flip-Flop 7470 of 7474 of d 9N74 9N70/5470 9N74/7474
Abstract: Signetjcs 7474, LS74A, S74 Flip-Flops Dual D-Type Flip-Flop Product Specification Logic Products DESCRIPTION T h e '7 4 is a dual positive edge-triggered D -type flip-flop featuring individual D ata, Clock, S e t and R eset inputs; also com plem entary Q and Ü outputs. S e t (Sp) and R es e t (R D) are asynchro nous active-L O W inputs and operate independently of the Clock input. Infor m ation on the D ata (D) input is trans ferred to the Q output on the LO W -toH IG H transition of -
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74S74 7474 LS ls 7474 74ls74a 74LS74A 100MH N7474N N74LS74AN N74S74N
Abstract: . Information on the Data (D) input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition for , reliable operation. 7474, LS74A, S74 Flip-Flops Dual D-Type Flip-Flop Product Specification TYPE TYPICAL fâ'žAX TYPICAL SUPPLY CURRENT (TOTAL) 7474 25MHz 17mA 74LS74A 33MHz 4mA 74S74 100MHz 30mA NOTE: For , FAN-OUT TABLE PINS DESCRIPTION 74 74S 74LS D Input 1ul 1Sul 1LSul RD Input 2ul 3Sul 2LSul So Input 1ul -
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N74S74D 7474 pin out diagram pin diagram of 7474 74LS74A pin out configuration pin configuration of d flip flip 7474 7474 pin configuration 7474 j-k flip flop N741S74A 1N916 1N3064
Abstract: Digital Integrateci Circuits TTL Flip-Flops A range of standard '7400 series' TTL flip-flops is available in plastic dual-in-line encapsulation. DIC 7470 D.C.CIocked J-K Flip-Flop DIC 7472 J-K Master-Slave Flip-Flop DIC 7473 DUAL J-K Master-Slave Flip-Flop DIC 7474 DUAL D type Edge-Triggered Flip-Flop DIC 7476 DUAL Jâ'"K Master-Slave Flip-Flop with Preset and Clear DIC 7470 DIC 7472 DIC7473 DIC 7474 PRESET 2 [j CLEAR 7 1 8 DIC 7476 TO 116 14 LEAD MAX 5 08 HH -pi |4â'"8-9â'" â'¢1C UH c  -
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7476 J-K Flip-Flop J-K Flip-Flop 7476 7472 Flip-Flop 7476 ttl 7476 7473 dual JK
Abstract: 7474, LS74A, S74 LOGIC DIAGRAM MODE SELECT - FUNCTION TABLE INPUTS OPERATING MODE §D , Signetics 7474, LS74A, S74 Flip-Flops Dual D-Type Flip-Flop Product Specification Logic , Data, Clock, Set and Reset inputs; also com plementary Q and (5 outputs. Set (§D) and Reset (Rq) are asynchro nous active-LOW inputs and operate independently of the Clock input. Infor mation on the Data (D) input is trans ferred to the Q output on the LOW-toHIGH transition of the clock pulse. The D inputs must -
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specifications 7474 Flip-Flops 7474 7474 ttl jk 7474 7474 equivalent 7474 PIN DIAGRAM
Abstract: . Information on the Data (D) input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition for , reliable operation. INPUT AND OUTPUT LOADING AND FAN-OUT TABLE 7474, LS74A, S74 Flip-Flops Dual D-Type Flip-Flop Product Specification TYPE TYPICAL fMAX TYPICAL SUPPLY CURRENT (TOTAL) 7474 25MHz 17mA 74LS74A , Products Data Manual. PINS DESCRIPTION 74 74S 74LS D Input 1ul 1Sul 1LSul HD Input 2ul 3Sul 2LSul 3D -
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74574 8XC660 7474 ttl ti 74574 pin out diagram 7474 J-K Flip-Flop ls 7474 ttl
Abstract: 7474, LS74A, S74 LOGIC DIAGRAM MODE SELECT - FUNCTION TABLE IN PU TS O P E R A T IN G M O D E , P ro d u c t S p e c ific a tio n Flip-Flops 7474, LS74A, S74 DC ELECTRICAL CHARACTERISTICS , u cts P ro d u c t S p e c ific a tio n Flip-Flops 7474, LS74A, S74 TEST CIRCUITS AND , Signetics 7474, LS74A, S74 Flip-Flops Dual D-Type Flip-Flop Product Specification Logic Products DESCRIPTION T h e '7 4 is a dual positive edge-triggered D -type flip-flop featuring -
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pin DIAGRAM OF IC 7474 ic 7474 pin diagram 7474 ic pin configuration IC 7474 pin configuration pin IC 7474 logic ic 7474 pin diagram 7474N 74S74N N741S
Abstract: The Leader in High Temperature Semiconductor Solutions CHT-7474 DATASHEET Revision: 03.3 1-Oct-12 (Last Modified Date) High-Temperature, Dual D-Flip-Flop General Description Features The CHT-7474 is a dual positive-edgetriggered D type Flip-flop. Data on the D input is transferred to the output , on-going) ï'· The CHT-7474 can operate with supply voltages from 3.3 to 5V (±10%). Available in , -Oct-12 Contact CHT-7474 DATASHEET : Gonzalo Picún (+32-10-489214)Oct. 12 (Last Modified Date) SOIC16 4 CISSOID
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7474 14 PIN CHT-7474 CDIL14 CSOIC16 DIL14 DS-080211
Abstract: after clock pulse. DUAL D FLIP FLOP GENERAL DESCRIPTION The 7474 is designed for use where the flexibility of 2 inputs is not required. It has only a single DATA (D) input. The logical level applied to , . . Jll+1 _ . INPUT OUTPUT OUTPUT D Q Q 0 0 l 1 i 0 NOTES: 1. tn := bit time berore -
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ic D flip flop 7474 T flip flop IC JK flip flop IC ic 7474 features of ic 7474 d flip flop 7474
Abstract: +70°/75°C CERAMIC DIP (D) 7445 7446 7447 7448 7449 7450 7451 7453 7454 7460 7470 7472 7473 7474 7475 , TTL/MSI 9393/5493, 7493 4 -B IT BINARY COUNTER D E S C R IP T IO N -T h e T T L /M S I 9393/5 4 , CP a - Simultaneously divisions of 2, 4, 8 and 16 are performed at the Q a , Q g, Qc. and Q d outputs , c, and Q d outputs. Independent use of flip-flop A is available if the reset function coincides with , b Qc Q d 2 3 12 9 8 11 These circuits are completely compatible with T T L and DTL logic -
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STR W 5453 A STR 5453 STR W 5453 STR W 5453 C Truth Table 74190 Truth Table 74192 74H00
Abstract:  , (Each Half) INPUT OUTPUTS @ tn @ tn + 1 D Q Q L H L H H L Asynchronous Inputs: LOW input to Sd , Plastic DIP (P) Ceramic DIP (D) Flatpak (F) PIN OUT COMMERCIAL GRADE Vcc = +5.0 V ±5%, Ta = 0°C to -
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7474PC 74H74PC 74S74PC 74LS74PC 7474DC 74H74DC 74h74p 74LS74DC 74ls74D 74H74D 4S/74S74
Abstract: Functions Featuring: Programmable Flip-Flop Type (D/T/JK/SR) Synchronous or Asynchronous Clocking 8 Product , either the SSI or MSI level: for example, individual 7474 elements may be used in design entry, or 74374 octal equivalents used where appropriate. Programmable flip-flop type (D,T, JK,SR), independent -
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74194 shift register 74377 register logicaps 74191 counter 74377 altera logicaps TTL library EPB1400
Abstract: NATIONAL SENICOND -CLOGIO D2E D | LSDllES D0b371S 2 | T-46-07-09 74 CO NNECTIO N DIAGRAM S PINO UT A 54/7474 54H/74H74 54S/74S74 54LS/74LS74 DUAL D-TYPE POSITIVE EDGETRIG GERED FLIP-FLOP , the clock pulse. Clock trig gering occurs at a voltage level o f the clock pulse and is not d ire c , (Each Half) INPUT @ tn D L H OUTPUTS @ tn + 1 IO O L H PIN PKGS Plastic DIP (P) C eram ic DIP (D) Flatpak (F) OUT A synchronous Inputs: LOW Input to S d sets Q to HIGH level LOW input to C d sets Q to -
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74LS74 truth table DE flip-flop 7474 pin diagram of 74ls74 logic diagram of ic 7474 74S74 national 74ls74 pin configurations 5474DM 54H74DM 54S74DM 54LS74DM 54S74FM 54/74H
Abstract: be used as a building block in an analog-to-digital (A/D) conversion system, by using the VFC to , . Although VFC-based A/D converters are slower than successive-approximation and flash converters, they are comparable in speed to integrating A/D converters. VFC-based A/D converters are thus well suited for low , measured. The resolution of the A/D conversion, of course, is determined by the clock frequency and the , -bit binary counters with output registers, one 4020B 14-stage binary counter, one 7474 dual D-type flip-flop -
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AN-276 MC4044 frequency counter using 8051 74590 Voltage-to-Frequency Converters 74LS221 74ls04hex SN7474 MC6801
Abstract: be used as a bui'ding block in an analog-to-digital IA/D) conversion system, by using the VFC to , speed to integrating A/D converters. VFC-based A/[ > converters are thus well suited for low frequency , and output frequencies that is being measured. The resolution of the A/D conversion, of course, is , counter, one 7474 dual D-type flip-flop with preset and clear, and one inverter of a 74LS04 hex inverter. The 4020B and 7474 provide the timing signal which tells the counters when to start and stop counting -
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ttl 7474 sine wave 74ls221 circuits diagram ICM7208 74ls04 hex inverter 74LS04* hEX INVERTER voltage frequency table ad654
Abstract: also offers an extensive library of 7400 series latch and register functions 7474 7498 7409 , . A B M C DATA Q O D D N E CLOCK F Similarly, designs frequently call for a QuickLogic
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74171 7478 J-K Flip-Flop 7478 jk 7400 series logic ICs 74594 7498 4 bit QL8X12B QL8X12
Abstract: 54/7474 54H/74H74 54S/74S74 54LS/74LS74 LOGIC SYMBOL DESCRIPTION The "74" is a Dual Positive , the clock input. Information on the data (D) input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D inputs must be stable one setup time prior to the LOW-to-HIGH clock , 10 A 2â'" d s° 0 â'"5 12 â'" d s° q -9 3â'" >cp 11 â'" > cp rt> 5 â'" 6 5 -6 V Â¥ 13 Pin , TABLE operating mode inputs outputs ®d rd cp d q q Asynchronous Set L H X X H L Asynchronous -
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N74H74N N74LS74N N7474F N74H74F N74S74F N74LS74F 74ls74 pin configuration S5474F 74H74 7474 D flip flop 74ls74 S54LS74W
Abstract: Dual J-K master slave flip-flop with clear Dual D type pos edge trig flip-flop pre + clear Quad , 74HC42 74LS47 74LS51 74LS53 74LS54 74HC51 7472 7473 74LS73 74HC73 7474 7475 , Quad D flip flop Synchronous decimal counter with set and reset inputs and N-input Synchronous 4 , 7474 7475 7476 7480 7482 7483 7485 7486 7490 7491 7492 7495 7496 74104 74107 74121 Electro Value
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FZH115B fzh261 FZK105 FZH131 FZJ111 FZH115 74INTEGRATED 16-DIL
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