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SN7474N3 Texas Instruments IC TTL/H/L SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP14, PLASTIC, MS-001AA, DIP-14, FF/Latch ri Buy
SN7474DR Texas Instruments IC TTL/H/L SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14, PLASTIC, SOIC-14, FF/Latch ri Buy
SN7474N Texas Instruments IC TTL/H/L SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP14, PLASTIC, MS-001AA, DIP-14, FF/Latch ri Buy

7474 D flip-flop

Catalog Datasheet Results Type PDF Document Tags
Abstract: auto-ranging is necessary. 6 The 7474 D flip-flop controls the 3 1/2 - 4 1/2 digit mode of the ICL7103A ICL7103A , Building an Auto-Ranging DMM with the ICL7103A/ICL8052A ICL7103A/ICL8052A A/D Converter Pair Application Note , errors to the system. The development of LSI A/D converters has carved the pathway for a new category , ICL8052A ICL8052A A/D pair represents an excellent example of this new breed of converter products available , Application Note 028 Basic Circuitry The basic circuit for the ICL7103A/ICL8052A ICL7103A/ICL8052A A/D converter remains ... Original
datasheet

8 pages,
148.71 Kb

74195 TTL shift register data sheet 2N2007 7447 decade counter 74121 application as pulse generator AN028 intersil zestron 278 7474 pin out diagram 7474 D flip-flop circuit diagram zestron reed relay 7474 shift register transistor 2N2007 ICL7103 ICL7103A/ICL8052A AN028 ICL7103A/ICL8052A abstract
datasheet frame
Abstract: auto-ranging is necessary. 6 The 7474 D flip-flop controls the 3 1/2 - 4 1/2 digit mode of the ICL7103A ICL7103A , Building an Auto-Ranging DMM with the ICL7103A/ICL8052A ICL7103A/ICL8052A A/D Converter Pair Application Note , errors to the system. The development of LSI A/D converters has carved the pathway for a new category , ICL8052A ICL8052A A/D pair represents an excellent example of this new breed of converter products available , Application Note 028 Basic Circuitry The basic circuit for the ICL7103A/ICL8052A ICL7103A/ICL8052A A/D converter remains ... Original
datasheet

8 pages,
118.05 Kb

7474 for shift register Low Cost Digital Panel Meter Designs 74195 shift register precision rectifier 7474 7474 shift register zestron reed relay AN028 intersil Low Cost Digital Panel Meter Designs" 7474 D flip-flop circuit diagram 74121 application as pulse generator zestron 278 ICL7103A/ICL8052A AN028 ICL7103A/ICL8052A abstract
datasheet frame
Abstract: The Multibus Design Guidebook W r it t e n f o r p r o fe s s io n a ls a n d s t u d e n t s a , fam ily D e ta ils o f the M u ltib u s/IE E E -7 9 6 and o f the M ultichannel, iS B X , and i L B X , interface designs A n d m uch, m uch m o re - all in one co m p lete reference! McGraw-Hill Book Company S erving the N eed fo r K n o w le d g e 1221 A venue of th e A m e rica s New York, NY 10020 , , covering: Structure of the Multibus/IEEE-796 system, an industry standard D ifferent architectures that ... OCR Scan
datasheet

449 pages,
127549.52 Kb

8086 microprocessor based project 80286 schematic intel 8080 family intel 8080 microprocessor parallel bus arbitration national semiconductors book clock national semiconductor logic 1981 Multibus arbitration protocol Motorola Bipolar Power Transistor Data interfacing 8289 with 8086 Intelligent Opto Sensor datasheet abstract
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Abstract: Digital Integrateci Circuits TTL Flip-Flops A range of standard '7400 series' TTL flip-flops is available in plastic dual-in-line encapsulation. DIC 7470 D.C.CIocked J-K Flip-Flop DIC 7472 J-K Master-Slave Flip-Flop DIC 7473 DUAL J-K Master-Slave Flip-Flop DIC 7474 DUAL D type Edge-Triggered Flip-Flop DIC 7476 DUAL J-K Master-Slave Flip-Flop with Preset and Clear DIC 7470 DIC 7472 DIC7473 DIC7473 DIC 7474 PRESET 2 [j CLEAR 7 1 8 DIC 7476 TO 116 14 LEAD MAX 5 08 HH -pi |4-8-9- •1C UH c £ MAX I ... OCR Scan
datasheet

1 pages,
35.71 Kb

TTL 7472 jk 7474 7474 7472 ttl 7474 flip flops 7470 TTL Jk 7476 7474 ttl 7474 J-K Flip-Flop TTL 7476 Flip-Flop 7476 7473 dual JK 7476 7474 D flip-flop datasheet abstract
datasheet frame
Abstract: FAIRCHILD TTL/SSI • 9N74/5474 9N74/5474, 7474 DUAL D TYPE EDGE TRIGGERED FLIP-FLOP / DESCRIPTION - The 9N74/5474 9N74/5474, 7474 are edge triggered dual D type flip-flops with direct clear and preset inputs and both Q and , time after clock pulse. LOGIC DIAGRAM (EACH FLIP-FLOP) 5-112 FAIRCHILD TTL/SSI . 9N74/5474 9N74/5474, 7474 , characteristics as the 9N70/5470 9N70/5470, 7470 gated (edge triggered) flip-flop circuits. They can result in a significant , clock SCHEMATIC DIAGRAM (EACH FLIP-FLOP) Component values shown are typical. TRUTH TABLE (Each Flip-Flop ... OCR Scan
datasheet

2 pages,
123.43 Kb

FLIPFLOP SCHEMATIC 7474 DIP Flip-Flop on off 7474 fairchild d 7474 Flip-Flop 7470 9N74 7474 D flip-flop 7474 ttl of 7474 of d ttl 7474 7474 7474 D flip-flop circuit diagram 9N74/5474 9N74/5474 abstract
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Abstract: Signetjcs 7474, LS74A LS74A, S74 Flip-Flops Dual D-Type Flip-Flop Product Specification Logic Products DESCRIPTION T h e '7 4 is a dual positive edge-triggered D -type flip-flop featuring individual D ata, Clock, S e t and R eset inputs; also com plem entary Q and Ü outputs. S e t (Sp) and R es e t (R D) are asynchro nous active-L O W inputs and operate independently of the Clock input. Infor m ation on the D ata (D) input is trans ferred to the Q output on the LO W -toH IG H transition of ... OCR Scan
datasheet

5 pages,
149.33 Kb

74S74 7474 7474 D flip-flop 7474 D flip-flop circuit diagram LS74A LS74A abstract
datasheet frame
Abstract: Signetics 7474, LS74A LS74A, S74 Flip-Flops Dual D-Type Flip-Flop Product Specification Logic Products DESCRIPTION The '74 is a dual positive edge-triggered D-type flip-flop featuring individual Data, Clock, Set and Reset inputs; also com plementary Q and (5 outputs. Set (§D) and Reset (Rq) are asynchro nous active-LOW inputs and operate independently of the Clock input. Infor mation on the Data (D) input is trans ferred to the Q output on the LOW-toHIGH transition of the clock pulse. The D inputs must ... OCR Scan
datasheet

5 pages,
148.59 Kb

pin diagram of 7474 Flip-Flops 7474 74S74 7474 D flip-flop 7474 ttl 7474 pin configuration specifications 7474 7474 74LS74A pin out configuration TTL 7474 7474 pin out diagram LS74A LS74A abstract
datasheet frame
Abstract: reliable operation. 7474, LS74A LS74A, S74 Flip-Flops Dual D-Type Flip-Flop Product Specification TYPE TYPICAL f„AX TYPICAL SUPPLY CURRENT (TOTAL) 7474 25MHz 17mA 74LS74A 74LS74A 33MHz 4mA 74S74 74S74 100MHz 30mA NOTE: For , Signetics Logic Products DESCRIPTION The '74 is a dual positive edge-triggered D-type flip-flop , on the Data (D) input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition for ... OCR Scan
datasheet

5 pages,
146.64 Kb

7474 ttl 74LS 74LS74A N7474N N74LS74AN N74S74D N74S74N LS74A 7474 PIN DIAGRAM 74S74 pin configuration of d flip flip 7474 7474 j-k flip flop 7474 pin configuration 74LS74A pin out configuration LS74A abstract
datasheet frame
Abstract: reliable operation. INPUT AND OUTPUT LOADING AND FAN-OUT TABLE 7474, LS74A LS74A, S74 Flip-Flops Dual D-Type Flip-Flop Product Specification TYPE TYPICAL fMAX TYPICAL SUPPLY CURRENT (TOTAL) 7474 25MHz 17mA 74LS74A 74LS74A , Signetics Logic Products DESCRIPTION The '74 is a dual positive edge-triggered D-type flip-flop , on the Data (D) input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition for ... OCR Scan
datasheet

5 pages,
151.41 Kb

jk 7474 N7474N 7474 LS N74LS74AN N74S74D N74S74N 7474 J-K Flip-Flop 7474 D flip-flop circuit diagram 8XC660 7474 ttl ti 74574 pin out diagram specifications 7474 7474 D flip-flop 74574 LS74A LS74A abstract
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Abstract: (Each Flip-Flop) 'n + 1 Q Qn 0 1 Qn tn = bit time before iclock pulse. In + ] = bit time after clock pulse. DUAL D FLIP FLOP GENERAL DESCRIPTION The 7474 is designed for use where the flexibility of 2 inputs is not required. It has only a single DATA (D) input. The logical level applied to this , ) Operating free-air temperature range, TA.0-70°C (MIN-MAX) TRUTH TABLE (Each Flip-Flop , clock; tn . . Jll+1 _ . INPUT OUTPUT OUTPUT D Q Q 0 0 l 1 i 0 NOTES: 1. tn := bit ... OCR Scan
datasheet

1 pages,
60.54 Kb

7474 flip flop 7474 d flip D flip flop IC 7474 flip flops ic for jk flip flop IC 7474 flipflop master slave jk flip flop 7474 truth table 7474 D flip flop features of ic 7474 d flip flop 7474 ic 7474 jk flip flop ic pin IC 7474 datasheet abstract
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] da_out .model da_out vcdac .ENDS XLS74 XLS74 XLS74 XLS74 *7474 D Flip-Flop MCE Nodes: S,D,CP,R,QN,Q *MCE mixed-mode D V(3)=0V V(4)=4.5V .ENDS X7474 X7474 X7474 X7474 *74F74 74F74 74F74 74F74 D Flip-Flop MCE Nodes: S,D,CP,R,QN,Q *MCE mixed-mode D .IC V(3)=0V V(4)=4.5V .ENDS X74F74 X74F74 X74F74 X74F74 *74HC74 74HC74 74HC74 74HC74 D Flip-Flop MCE Nodes: S,D,CP,R,QN,Q *MCE mixed-mode D .IC V(3)=0V V(4)=4.5V .ENDS X74HC74 X74HC74 X74HC74 X74HC74 *74LS74 74LS74 74LS74 74LS74 D Flip-Flop MCE Nodes: S,D,CP,R,QN,Q *MCE mixed-mode D Flip-Flop pkg:DIP14 DIP14 DIP14 DIP14 (A:4,2,3,1,6,5)(B:10,12,11,13,8,9) .SUBCKT X74LS74 X74LS74 X74LS74 X74LS74 10 7 5 8 3 4 XU1A 10 6 3
www.datasheetarchive.com/files/spicemodels/misc/modelos/7474.sub
Spice Models 21/02/2008 2.04 Kb SUB 7474.sub
*74LS74 74LS74 74LS74 74LS74 D Flip-Flop MCE Nodes: S,D,CP,R,QN,Q *MCE mixed-mode D Flip-Flop pkg:DIP14 DIP14 DIP14 DIP14 (A:4,2,3,1,6,5)(B:10,12,11,13,8,9) .SUBCKT X74LS74 X74LS74 X74LS74 X74LS74 10 7 5 8 3 4 XU1A 10 6 3 4 7410 XU1B 4 8 11 3 7410 XU1C 11 8 7 9 7410 XU2A 6 5 9 11 7410 XU2B 12 8 5 6 7410 XU2C 10 9 6 12 7410 .IC V(3)=0V V(4)=4.5V .ENDS X74LS74 X74LS74 X74LS74 X74LS74
www.datasheetarchive.com/files/spicemodels/misc/models/7474.sub
Spice Models 17/09/2010 0.3 Kb SUB 7474.sub
No abstract text available
www.datasheetarchive.com/download/48664731-299145ZC/bae65022linux.tgz
Kaleidoscope 22/08/2005 11421.08 Kb TGZ bae65022linux.tgz
* * * *SRC=7474;7474;TTL;74xx;D Flip-Flop *SYM=T7474 T7474 T7474 T7474 *7474 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED *FLIP-FLOPS WITH PRESET & CLEAR * .subckt 7474 clrbar d clk prebar q qbar *FAMILY TTLin TTLin TTLin TTLin * * * *SRC=7470;7470;TTL;74xx;J-K Flip-Flop *SYM=T7470 T7470 T7470 T7470 *7470 AND-GATED J-K POSITIVE-EDGE-TRIGGERED *FLIP-FLOPS ) .ends * * * *SRC=7472;7472;TTL;74xx;J-K Flip-Flop *SYM=T7472 T7472 T7472 T7472 *7472 AND-GATED fall_delay=6n) .ends * * * *SRC=7473;7473;TTL;74xx;J-K Flip-Flop *SYM=T7473 T7473 T7473 T7473 *7473
www.datasheetarchive.com/files/spicemodels/misc/modelos/spice_complete/7400.lib
Spice Models 18/04/2010 72.32 Kb LIB 7400.lib
OR2 .ENDS *INCLUDE DIGITAL.LIB * * SRC=DFFPC;DFFPC;Digital;Generic;D Flip-Flop (2-MSSRs * * SRC=JKFFPC;JKFFPC;Digital;Generic;JK Flip-Flop .SUBCKT JKFFPC 8 7 12 6 4 3 5 * j clk k .SUBCKT AND4 1 2 3 4 5 * A B C D Out B1 5 0 V= V(1)&V(2)&V(3)&V(4) RD 6 5 1 CD 5 0 .87NF .ENDS * * SRC=OR4;OR4;Digital;Generic;4 Input OR .SUBCKT OR4 1 2 3 4 5 * A B C D * * SRC=NAND4;NAND4;Digital;Generic;4 Input NAND .SUBCKT NAND4 1 2 3 4 5 * A B C D Out B1 6 0 V=
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Spice Models 18/04/2010 17.77 Kb LIB digital.lib
* bss 2/8/94 * .SUBCKT 7430 A B C D E F G H Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(8) DPWR DGND + A B C D E F G H Y + DLY_30 IO_STD * bss 2/10/94 * .SUBCKT 7442A A B C D + O0 O1 O2 O3 O4 O5 O6 O7 O8 O9 + optional D + O0_O O1_O O2_O O3_O O4_O O5_O O6_O O7_O O8_O O9_O + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} + + LOGIC: + abar = {~A} + bbar = {~B} + cbar = {~C} + dbar = {~D} + +
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Spice Models 18/04/2010 128.15 Kb LIB digdemo.lib
* DIGITAL LIBRARY 7400- * * - 7400 - * Quad 2-Input Nand Gates * * The TTL Logic Data Book, 1988, TI Pages 2-3 to 2-7 * bss 2/2/94 * .SUBCKT 7400 1A 1B 1Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(2) DPWR DGND + 1A 1B 1Y + DLY_00 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .model DLY_00 ugate (tplhTY=11ns tplhMX=22ns tphlTY=7ns tphlMX=15ns) .ENDS 7
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Spice Models 18/04/2010 473.91 Kb LIB dig000.lib
HCF4011B HCF4011B HCF4011B HCF4011B HCF4012B HCF4012B HCF4012B HCF4012B HCF4023B HCF4023B HCF4023B HCF4023B 2023 DUAL 'D' - TYPE FLIP-FLOP HCF4013B HCF4013B HCF4013B HCF4013B 2024 10 TO 4 LINE BCD PRIORITY ENCODER HCF4016B HCF4016B HCF4016B HCF4016B 2028 HEX "D" - TYPE FLIP-FLOP HCF40174B HCF40174B HCF40174B HCF40174B 2029 COUNTERS/DIVIDERS HCF4017B HCF4017B HCF4017B HCF4017B HCF4022B HCF4022B HCF4022B HCF4022B 2030 4-BIT FLIP-FLOP WITH CLEAR M74HC175 M74HC175 M74HC175 M74HC175 1916 ARITHMETIC LOGIC UNIT/FUNCTION GENERATOR M74HC181 M74HC181 M74HC181 M74HC181 1917 FUNCTION LOOK HCF4026B HCF4026B HCF4026B HCF4026B HCF4033B HCF4033B HCF4033B HCF4033B 2039 DUAL-J-K MASTER-SLAVE FLIP-FLOP HCF4027B HCF4027B HCF4027B HCF4027B 2040 BCD-TO-DECIMAL DECODER HCF4028B HCF4028B HCF4028B HCF4028B 2041 M74HC266 M74HC266 M74HC266 M74HC266 M74HC7266 M74HC7266 M74HC7266 M74HC7266 1935 TRIPLE 3-INPUT NOR GATE M74HC27 M74HC27 M74HC27 M74HC27 1936 OCTAL D TYPE FLIP FLOP WITH CLEAR M74HC273 M74HC273 M74HC273 M74HC273
www.datasheetarchive.com/files/stmicroelectronics/stonline/db/psearch.txt
STMicroelectronics 02/02/2001 240.03 Kb TXT psearch.txt
Preset and Clear * 7473 Dual J-K Flip-Flops with Clear * 7474 3 50 .MODEL Dmodel D + IS=5.3253E-12 3253E-12 3253E-12 3253E-12 + N=3.4748 + RS=1.0000E-3 0000E-3 0000E-3 0000E-3 + CJO=1.0000E-12 0000E-12 0000E-12 0000E-12 + M=.3333 + 4 3 50 .MODEL Dmodel D + IS=5.3253E-12 3253E-12 3253E-12 3253E-12 + N=3.4748 + RS=1.0000E-3 0000E-3 0000E-3 0000E-3 + CJO=1.0000E-12 0000E-12 0000E-12 0000E-12 + M=.3333 + D1N750 D1N750 D1N750 D1N750 D(Is=880.5E-18 5E-18 5E-18 5E-18 Rs=.25 Ikf=0 N=1 Xti=3 Eg=1.11 Cjo=175p M=.5516 + Vj=.75 Fc=.5 Isr=1.859n Nr=2 * each part. Each part was characterized using the Parts option. * .model MV2201 MV2201 MV2201 MV2201 D(Is=1.365p Rs=1
www.datasheetarchive.com/files/spicemodels/misc/eval.lib
Spice Models 20/12/2001 295.35 Kb LIB eval.lib
root option unique="0" id="219" des.en="Catalog" APPLICATIONNOTES: 219 LISTING: 219 NUMBEROFPRODUCTS: 9259 option unique="1" id="282" des.en="Products by function" APPLICATIONNOTES: 282 LISTING: 282 NUMBEROFPRODUCTS: 5571 option unique="3" id="41685" des.en="Analog and mixed-signal devices" APPLICATIONNOTES: 41685 SGTABLE: 41685 SGINTERACTIVE: 41685 LISTING: 41685 NUMBEROFPRODUCTS: 139 option unique="18" id="42890" des.en="Data converters" APPLICATIONNOTES: 42890
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Philips 17/06/2005 3887.26 Kb HTML catalog_test_6-6.html