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746uA

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Abstract: Variances Expected at 25°C. FIGURE 7 DESIGN EXAMPLE. TOTAL VDROP TO COMPENSATE = 744mV, I+IN = 74.6µA TERM , 0.165 0.0055 0.33 106.4 ­0.004 ­0.015 VOS + VOS/I+IN · (100µA ­ 74.6µA) + VOS/VIOUT · (1.2V ­ 0.8V) + ... Original
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38 pages,
509.86 Kb

LT6110 LT6110 abstract
datasheet frame

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www.datasheetarchive.com/download/30954826-35126ZD/rp00c87.zip (sstv857.ibs)
IDT 16/04/2002 7.91 Kb ZIP rp00c87.zip