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74373 output port

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Abstract: (74373) Output to Internal Bus Bus Transceiver(74245) Output to Bus Port Input to Internal Bus , 74373 or 74377, CM O S or TTL) and two byte-wide output latches (similar to 74373). (Hereafter, the , elements consist of two input buffer registers, two output latches, and a bus port transceiver. Control , ) of the output latch, and port Output Enable (OE) of the bus port transceiver. User-defined logic , strobe for the input registers, output latches and bus transceiver port. In addition, Pins 14 and 7 -
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function of latch ic 74373 IC 74373 logitech 99 mouse IC EPB1400 EPB1400-2
Abstract: registers (similar to 74373 or 74377, CMOS or TTL) and two byte-wide output latches (similar to 74373). , registers, 2 output latches and a bus port transceiver. All byte-wide elements communicate via the internal , consist of two input buffer registers, two output latches, and a bus port transceiver. Control signals for , input register, Output Latch Enable (OLE) and Read Enable (RE) of the output latch, and port Output , transceiver port. In addition, Pins 14 and 7 (CLK1 and CLK2) may act as fast clocks for the output latches -
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latch 74373 74373 truth table 74373 cmos dual s-r latch Latches 74373 74245 truth table TTL 74373
Abstract: output latches (similar to 74373). (Hereafter, the input functions will sim ply be referred to as input , registers, two output latches, and a bus port transceiver. Control signals for each byte-wide element are , ) of the output latch, and port O utput Enable (OE) of the bus port transceiver. User-defined logic , strobe for the input registers, output latches and bus transceiver port. In addition, Pins 14 and 7 , Internal Bus RINP8 A RBUSLA LINP8 LBUSI LBUSO BUSX 8-Bit O utput Latch(74373) Output to -
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EP1200
Abstract: output latches (similar to 74373). (Hereafter, the input functions will simply be referred to as input , registers, 2 output latches and a bus port transceiver. All byte-wide elements communicate via the internal , consist of two input buffer registers, two output latches, and a bus port transceiver. Control signals for , , and port Output Enable (OE) of the bus port transceiver. User-defined logic within these Control , registers, output latches, and the transceiver port. During normal operation, data passes from the -
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74245 BUFFER IC pin diagram of 74245 BUFFER IC IC 74245 80386 microprocessor pin out diagram 74245 buffer 74245 20 pin ic
Abstract: Microprocessor Bus Port with Programmable Control. · Dual Byte-Wide Input and Output Register's for , register. Two 74373 output latches provide a mechanism for processor access to current bit rate count , the Silicon level. The device consists o f a dedicated Byte-wide Bus-lnterface Port and Input/O utput , Input and Output Registers allows the implementation of functions in the device which are loosely , bidirectional, generic slave interface of the EPB1400 Bus Port fits virtually any microprocessor. Control -
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74194 shift register 74377 register logicaps 74191 counter 74377 altera logicaps TTL library
Abstract: Port transmitter output INT0 (P3.2) : External Interrupt 0 INT1 (P3.3) : External Interrupt 1 T0(P3 , ALE Low TPDH 0 - - nS Port Output to ALE TPDA 1 TCP - - nS Note , additional 4-bit I/O port P4; three 16bit timer/counters; a hardware watchdog timer and a serial port. These , port, additional INT2 / INT3 (available on 44-pin PLCC/QFP package) · Three 16-bit timer/counters · One full duplex serial port(UART) · Watchdog Timer · Eight sources, two-level interrupt Winbond Electronics
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W78LE52 80C52 S5-P W78C51 W78LE52-24 W78LE52F
Abstract: (P3.1) : Serial Port transmitter output INT0 (P3.2) : External Interrupt 0 INT1 (P3 , TPDH 0 - - nS Port Output to ALE TPDA 1 TCP - - nS Note: Ports are , I/O ports; an additional 4-bit I/O port P4; three 16-bit timer/counters; a hardware watchdog timer and a serial port. These peripherals are supported by eight sources two-level interrupt capability , · One extra 4-bit bit-addressable I/O port, additional INT2 / INT3 (available on 44-pin PLCC/QFP Winbond Electronics
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W78LE54 W78LE54-24 W78LE54F W78LE54F-24 W78LE54P W78LE54P-24
Abstract: - nS Port Input Hold from ALE Low TPDH 0 - - nS Port Output to ALE TPDA , .16 7.3.5 Port Access Cycle , . 18 Port Access Cycle , bytes RAM; four 8-bit bi-directional and bit-addressable I/O ports; an additional 4-bit I/O port P4; three 16-bit timer/counters; a hardware watchdog timer and a serial port. These peripherals are Winbond Electronics
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W78E054C40PL W78E054C W78E054C40DL w78e54b W78E54B-24/40 W78E54C/W78E054C
Abstract: are described below: RXD(P3.0) : Serial Port receiver input TXD(P3.1) : Serial Port transmitter output , Port Input Hold from ALE Low Port Output to ALE TPDS TPDH TPDA 1 TCP 0 1 TCP - - nS nS , and bit-addressable I/O ports; an additional 4-bit I/O port P4; three 16-bit timer/counters; a hardware watchdog timer and a serial port. These peripherals are supported by eight sources two-level , -bit bi-directional ports One extra 4-bit bit-addressable I/O port, additional INT2 / INT3 (available on 44-pin PLCC Winbond Electronics
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W78LE52C/W78L052C
Abstract: port. TxD (P3.1): Serial output port. INT0 (P3.2): External interrupt. Serve as A14 during memory , Description 7-4 - These bits are reserved. 3 P4.3 Port 4 Data bit that output to pin P4.3 at mode 0. 2 P4.2 Port 4 Data bit that output to pin P4.2 at mode 0. 1 P4.1 Port 4 Data bit that output to pin P4.1 at mode 0. 0 P4.0 Port 4 Data bit that output to pin P4.0 at mode , address depends on the content of P2EAL and P2EAH. =11 : Undefined. PORT 2 OUTPUT DATA BUS MUX Integrated Circuit Solution
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MC012-0C 74244 uses and functions MC012 p41al TI 74244 74244 IC89E54/58/64 16/32/64-K IC89E54 IC89E58 IC89E64 80C51
Abstract: data #XX to pin P4.3-P4.1. PORT 2 OUTPUT DATA BUS INTERNAL DATA BUS PORT 2 74373 WRITE MUX , : input, O: output, I/O: bi-directional, H: pull-high, L: pull-low, D: open drain Port 4 Port 4, SFR , P2.7-P2.0 will output and latch the value 55H. When Port2 is configured as 74244 or 74373 function, the instruction " MOV P2,#XX " will write the data #XX to P2 register only but not output to port , Hold from ALE Low TPDH 0 - - nS Port Output to ALE TPDA 1 TCP - - nS Winbond Electronics
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W78E365 w78e62bp w78e62 8051 tcp ip W78E365D W78E365F
Abstract: Bus Address Latches â  Integrated Parallel Port a Low pQWer CHMOS Technology â  Integrated Card Setup Port (96H) B 100.pin Plastic Quad Flat Package The 82303 Local Channel Support , equivalent IBM system. The 82303 integrates most all logic required to implement a parallel port. This port operates either as a standard parallel port or as a MicroChannel architecture compatible "extended modeâ' (bi-directional) port. The 82303 also integrates the Card Setup Port (96H) and several peripheral bus address -
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82303 P103RD P103W P101RD M60STR
Abstract: TPDH 0 - - nS Port Output to ALE TPDA 1 TCP - - nS Note: "" (due to , port P4; three 16-bit timer/counters; a hardware watchdog timer and a serial port. These peripherals , address space · Four 8-bit bi-directional ports · One extra 4-bit bit-addressable I/O port, additional , serial port (UART) · Watchdog Timer · Eight sources, two-level interrupt capability · EMI reduction , onto the Port 0 address/ data bus during fetch and MOVC operations. When internal ROM access is Winbond Electronics
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W78IE54 W78IE54P DC-40
Abstract: Port transmitter output RST XTAL1 XTAL2 VSS VDD P0.0 - P0.7 P1.0 - P1.7 P2.0 - P2.7 P3.0 - , ALE Low TPDH 0 - - nS Port Output to ALE TPDA 1 TCP - - nS Note , port P4; three 16-bit timer/counters; a hardware watchdog timer and a serial port. These peripherals , -bit bi-directional ports · One extra 4-bit bit-addressable I/O port, additional INT2 / INT3 (available on 44-pin PLCC package) · Three 16-bit timer/counters · One full duplex serial port (UART) · Watchdog Timer · Winbond Electronics
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W78IE52 W78IE52P
Abstract: input TXD(P3.1) : Serial Port transmitter output INT0 (P3.2) : External Interrupt 0 INT1(P3 , Input Setup to ALE Low Port Input Hold from ALE Low Port Output to ALE SYMBOL TPDS TPDH TPDA MIN. 1 TCP , bytes RAM; four 8-bit bi-directional and bitaddressable I/O ports; an additional 4-bit I/O port P4; three 16-bit timer/counters; a hardware watchdog timer and a serial port. These peripherals are , Four 8-bit bi-directional ports · One extra 4-bit bit-addressable I/O port, additional INT2 / INT3 Winbond Electronics
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Abstract: PARAMETER SYMBOL MIN. TYP. MAX. UNIT Port Input Setup to ALE Low Port Input Hold from ALE Low Port Output , . 17 Port Access Cycle , /O ports; an additional 4-bit I/O port P4; three 16-bit timer/counters; a hardware watchdog timer and a serial port. These peripherals are supported by eight sources two-level interrupt capability. To , -bit bit-addressable I/O port, additional INT2 / INT3 (available on 44-pin PLCC/QFP package) Three 16-bit timer Winbond Electronics
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W78E52CP-40 W78E52C
Abstract: . PORT 2 OUTPUT DATA BUS MUX INTERNAL DATA BUS 74373 WRITE 16-BIT COMPARATOR P2CN1 ADDRESS , output and latch the value 55H. When Port 2 is configured as 74244 or 74373 function, the instruction , .0-P4.3 RxD (P3.0): Serial input port. TxD (P3.1): Serial output port. INT0 (P3.2): External interrupt , bit that output to pin P4.3 at mode 0. 2 P4.2 Port 4 Data bit that output to pin P4.2 at mode 0. 1 P4.1 Port 4 Data bit that output to pin P4.1 at mode 0. 0 P4.0 Port 4 Data Integrated Circuit Solution
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pin configuration 74373 ph43 1237h 16K/32K/64K IC89E54/58/64-12PL IC89E54/58/64-12W IC89E54/58/64-12PQ IC89E54/58/64-24PL IC89E54/58/64-24W
Abstract: .1) : Serial Port transmitter output ALE P3.0 - P3.7 INT0 (P3.2): External Interrupt 0 INT1 (P3.3): External , PARAMETER SYMBOL MIN. TYP. MAX. UNIT Port Input Setup to ALE Low Port Input Hold from ALE Low Port Output , . 12 Output Disable Condition , . 18 Port Access Cycle , . 21 Port Access Cycle Winbond Electronics
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Q719 39AD W78IE52/W78I052A
Abstract: . MAX. UNIT Port Input Setup to ALE Low Port Input Hold from ALE Low Port Output to ALE TPDS TPDH , . 12 Output Disable Condition , . 19 -1- W78E52B 10.4 10.5 11. 11.1 11.2 12. 12.1 12.2 12.3 13. Port Access Cycle , -bit bi-directional and bitaddressable I/O ports; an additional 4-bit I/O port P4; three 16-bit timer/counters; a hardware watchdog timer and a serial port. These peripherals are supported by eight sources two-level Winbond Electronics
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Abstract: mathematical computation, and output the result to another port, requiring 500 machine cycles of CPU time , requires the use of a Page 3 of 12 74373-type latch to demultiplex the lower byte of address. Figure 3 , available, their power consumption must also include that associated with a 74373 series latch as well as , waveform generator, with the ability to output sine, triangle, or square waves. The current consumption , that automatically restores the device to full operation when an external interrupt or serial port Maxim Integrated Products
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DS80C320 Sine Wave Generator using 8051 disadvantages of microcontroller 8051 Digital Alarm Clock using 8051 digital clock with alarm using 8051 square wave generator by 8051 piezoelectric crystals DS87C520 8051-B DS1620 AN1771 APP1771
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