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DUALOUTPUT-ISOFLYBACK-REF Texas Instruments Dual Output Isolated Flyback Design: 5V @ 0.2A, 12V @ 2.1A w/2 addl out 3.3V @ 0.5A, 5V @ 0.5A visit Texas Instruments
CD4508BNSR Texas Instruments CMOS Dual 4-Bit Latch 24-SO -55 to 125 visit Texas Instruments Buy
CD4508BNSRE4 Texas Instruments CMOS Dual 4-Bit Latch 24-SO -55 to 125 visit Texas Instruments
CD4508BD3 Texas Instruments CMOS Dual 4-Bit Latch 24-CDIP SB -55 to 125 visit Texas Instruments
CD4508BF3A Texas Instruments CMOS Dual 4-Bit Latch 24-CDIP -55 to 125 visit Texas Instruments
CD4042BF3A Texas Instruments CMOS Quad Clocked ''D'' Latch 16-CDIP -55 to 125 visit Texas Instruments

74373 cmos dual s-r latch

Catalog Datasheet MFG & Type PDF Document Tags

74573

Abstract: 74574 Multivibrator Octal Buffer Octal Buffer Octal Buffer Octal Bus Transceiver 8-Bit Addressable Latch Dual 5 , D-Type Latch Octal D-Type Latch Dual Decade Counter Dual 4-Bit Binary Counter Octal D-Type Latch , Octal D-Type Latch Octal D-Type Latch Octal D-Type Latch 8-Bit Magnitude Comparator 74373 / 74374 / 74533 / 74574 / 4042 74373 / 74374 / 74533 / 74573 / 4042 74373 / 74374 / 74533 / 74573 / 4042 CMOS , Dual Monostable Multivibrator 8-Bit Addressable Latch Hex Buffer Decade Counter BCD to 7
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latch 74373

Abstract: 74373 truth table registers (similar to 74373 or 74377, CMOS or TTL) and two byte-wide output latches (similar to 74373). , (74377) Input from Internal Bus No Write Strobe (WS) LINP8 8-Bit Input Latch(74373) Input from External Pins LBUSI 8-Bit Input Latch(74373) Input from Internal Bus LBUSO 8-Bit Output Latch(74373) Output to , used. OUTPUT LATCHES LBUSO is a flow-through output latch similar to the 74373. The latch enable is , at up to 25MHz Clock Rate. Dual Byte-Wide Input and Output Registers for Fully Buffered
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EP1200

Abstract: transparent latches or edge-triggered registers (similar to 74373 or 74377, CMOS or TTL) and two byte-wide , (WS) 8-Bit Input Latch(74373) Input from External Pins 8-Bit Input Latch(74373) Input from Internal Bus RINP8 A RBUSLA LINP8 LBUSI LBUSO BUSX 8-Bit O utput Latch(74373) Output to , used. O U T P U T LATCHES LBUSO is a flow -through output latch sim ilar to the 74373. The latch , Port with Programmable Control for use with 8, 16 and 32-bit MPUs at up to 25MHz Clock Rate. Dual
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IC 74373 truth table

Abstract: IC 74373 (74373) Input from External Pins 8-Bit Input Latch(74373) Input from Internal Bus 8-Bit Output Latch , used. OUTPUT LATCHES LB U S O is a flow-through output latch similar to the 74373. The latch enable , Programmable Control for use with 8, 16 and 32-bit MPUs at up to 25MHz Clock Rate. Dual Byte-Wide Input and , : Programmable Flip-Flop Type (D/T/JK/SR) Programmable Clocking Dual Feedback for Implementing Buried , 74373 or 74377, CM O S or TTL) and two byte-wide output latches (similar to 74373). (Hereafter, the
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74245 BUFFER IC

Abstract: pin diagram of 74245 BUFFER IC transparent latches or edge-triggered registers (similar to 74373 or 74377, CMOS or TTL) and two byte-wide , No Write Strobe (WS) LINP8 8-Bit Input Latch(74373) Input from External Pins LBUSI 8-Bit Input Latch(74373) Input from Internal Bus LBUSO 8-Bit Output Latch (74373) Output to Internal Bus BUSX Bus , flow-through output latch similar to the 74373. The latch enable is based on an AND function of two control , , 16 and 32-bit MPUs at up to 25MHz Clock Rate. Dual Byte-Wide Input and Output Registers for Fully
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counter 74168

Abstract: 3-8 decoder 74138 is able to convert levels of both CMOS and TTL for all input/output buffers. Ten types of master , dual-layer metal H CMOS (Effective gate length: 1.0 microns) â'¢ High speed and low power dissipation , CMOS and TTL levels are available.) â'¢ All pins of pull-up or pull-down MOS (100 Ki2) are available , . of unit cell Notes Inverters 1 INV 1 nvert gate 1 2 INV2 Dual invert gates 1 NAND gates 3 2ND 2 , 6ND 6-input NAND gate 5 8 7ND 7-input NAND gate 5 9 8ND 8-input NAND gate 6 10 2ND2 Dual 2
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asynchronous 4bit up down counter using jk flip flop

Abstract: counter 74168 is able to convert levels of both CMOS and TTL for all input/output buffers. Ten types of master , available. (Both CMOS and TTL levels are available.) â'¢ All pins of pull-up or pull-down MOS (100 KÂ , Notes Inverters 1 INV Invert gate 1 2 INV2 Dual invert gates 1 NAND gates 3 2ND 2-input NAND gate , -input NAND gate 5 8 7ND 7-input NAND gate 5 9 8ND 8-input NAND gate 6 10 2ND2 Dual 2-input NAND , -input NOR gate 6 18 2NR2 Dual 2-input NOR gates 2 AND gates 19 2AD 2-input AND gate 2 20 3AD 3
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74139 for bcd to excess 3 code

Abstract: design a bcd counter using jk flip flop convert levels of both CMOS and TTL for all input/output buffers. Ten types of master chips are prepared , '¢ All pins of schmitt input circuit are available. (Both CMOS and TTL levels are available ) â'¢ All , . of unit ceil Notes Inverters 1 INV Invert gate 1 2 INV2 Dual invert gates 1 NAND gates 3 2ND 2 , 6ND 6-input NAND gate 5 8 7ND 7-input NAND gate 5 9 8ND 8-input NAND gate 6 10 2ND2 Dual 2 , 8-input NOR gate 6 18 2NR2 Dual 2-input NOR gates 2 AND gate 19 2AD 2-input AND gate 2 20
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priority encoder 74148

Abstract: priority encoder 74147 -wide AND-OR gate 10 3 8.4 Dual gate 1-35 INV2 Dual inverter gate 1 10 2.3 1-36 2ND2 Dual 2-input NAND gate 2 5 32 1-37 2NR2 Dual 2-input NOR gate 2 5 3.6 1-38 2AD2 Dual 2-input AND gate 3 10 3.3 1-39 20R2 Dual 2-input OR gate 3 10 3.8 SR latch MO LTND S-R NAND latch 3 8 5.4 1-41 LTNR S-R NOR latch 3 , convert levels of both CMOS and TTL for all input/output buffers. Five types of master chips are prepared , available. (Both CMOS and TTL levels are availa-ble.f â'¢ All pins of pull-up or pull-down resistance (120
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function of latch ic 74373

Abstract: full adder using ic 74138 gate 1-33 1-34 1-35 1-36 Dual gate 1-37 1-38 1-39 SR latch 1-40 1-41 M2 M3 Internal driver 1-44 1-45 , gate Dual inverter gate Dual 2 -in put N A N D gate Dual 2 -in put NOR gate Dual 2 -in put A N D gate Dual 2-in put OR gate S-R N A N D latch S-R NOR latch Internal through driver-1 Internal through driver , -type latch w ith reset D -type flip flo p F lip flo p 1-50 DFR D -type flip flo p w ith , /reset and L S S D D-type latch Toggle flip flop with reset Toggle flip flop with set/reset 8 8 8 8 8
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74138n

Abstract: 74373 cmos dual s-r latch ll pins o f p u ll-u p o r p u ll-d o w n M O S of s c h m itt in p u t c irc u it are CMOS and , R gate 8 -in p u t N O R gate Dual 2 -in p u t N O R gates 2 -in p u t A N D gate 3 -in p u t A N D , OR gate 5 -in p u t OR gate 6 -in p u t OR gate 7 -in p u t OR gate 8 -in p u t OR gate Dual 2 -in p , e la tch w ith reset D -ty p e latch D -ty p e la tc h w ith reset D -ty p e latch D -ty p e la tc h , g e r 10 11 13 15 1 1 1 6 11 5 (3) (3) (3) (3) 1. Negative edge latch 2 . P ositive edge la
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74373 cmos dual s-r latch

Abstract: 74373 verilog ^ ^ ^ ^ ^ ^ ^ ^ jE L E C T R O N i KGL80 Gate Array Library 0.5um 3.3V CMOS Process , V DD = 3.3V, V BB = 5V, TA = 25°C , Typical Process CMOS C M O S Schm itt Trigger Input , LD 6 LD 6D 2 LD 7 LD 7D 2 LD 8 LD 8D 2 LD S2 LD S6 LSO LS0D2 LS1 LS2 D Latch w ith A ctive High D Latch w ith A ctive High, 2X Drive D Latch w ith A ctive High, Scan D Latch w ith A ctive High, Scan, 2X Drive D Latch w ith A ctive High, Q O u tp u t O nly D Latch w ith A ctive High, Q O u tp u t Only, 2X
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74373 cmos dual s-r latch 74373 verilog A022A 74152 PIN DIAGRAM application of ic 74153 T749 VSS30 VSS30I VSS30P VSS50

7408, 7404, 7486, 7432

Abstract: RF400U TGC100 Series CMOS Gate Arrays RELEASE 3.0, REVISED JANUARY 1990 · · · Twelve Arrays with up , SCOPETM Testability Macros TGC100 Series 1-|xm EPICTM CMOS Technology: - Double-Level Metal , MACRO Figure 1. TGC100 CMOS Gate Array description The Texas Instruments TGC100 Series comprises 12 gate arrays, each fabricated using T l's 1-nm advanced silicon-gate CMOS EPIC process. The process , u m e n t s POST OFFICE BOX 6 5 5 3 0 3 · DALLAS, TEXAS 752 65 TGC100 Series 1-jim CMOS Gate
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7408, 7404, 7486, 7432 RF400U functional diagram of 7400 and cd 4011 180 nm CMOS standard cell library TEXAS INSTRUMENTS s273 cmos 7404 TS000LJ TS002LJ TSB01LJ TSB02LJ TDB10LJ 120LJ

JRC 45600

Abstract: 45600 JRC CMOS/TTL TYPE 74193 74194A 74244 74260 74260 74266 74273 74279 74283 74373 SIMILAR GA MACRO S193LJ S , TGC100 Series 1-|im CMOS Gate Arrays RELEASE 4.0. REVISED SEPTEMBER 1991 14 Arrays with up to , -SCOPETM Testability Macros TGC100 Series 1-nm EPICTM CMOS Technology -Double-Level Metal, Slllclded-Poly , C R O description Figure 1. TGC100 CMOS Gate Array The Texas Instruments TGC100 Series comprises 14 gate arrays, each fabricated using Tl's 1-|.im advanced silicon-gate CMOS EPIC process. The
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JRC 45600 45600 JRC YD 803 SGS TDA 7277 krp power source sps 6360 TDA 5072 ZOP020 ZOP021 ZOP023 ZOP022 ZOP024 ZOP025

0221l

Abstract: APPLICATION NOTES CD 7474 IC xliii 1 5 Standard functions LOGIC FAMILIES CMOS HE4000B family specifications CMOS HE4000B , RAM Bipolar TTL PROM Bipolar ECL RAM Bipolar ECL PROM Bipolar ECL CAM CMOS EPROM CMOS RAM 77 , 83 83 DIGITAL LCD drivers; CMOS Display drivers; bipolar Clock timers; CMOS A/D and D/A converters; NMOS Miscellaneous; bipolar ECL AD/DA converter CMOS Remote I/O expander Memories 84 84 , transmission combination CMOS ICs for telephone subscriber sets: DTMF dialler with redial pulse diallers
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0221l APPLICATION NOTES CD 7474 IC TGC119 bit-slice IPF 830 cI 74150

cm .02m z5u 1kv

Abstract: pin configuration of BFW10 dual op amplifier vcc out1 - in + in This information was added by a third party and may be , : 24257A function: 32kx8 High-speed CMOS SRAM package: 28-pin PDIP,28 manufacturer: Winbond added-by , -name: 27C040 function: 512kx8 CMOS EPROM package: 32-pin Ceramic DIL,32 manufacturer: AMD , -4000 Dual 3-input NOR gates and inverter. 1A 1B 1C /1Y GND +-+ |1 +-+ 14| |2 13 , -4002, 744002 Dual 4-input NOR gates. +-+ +-+ Page 34 _
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cm .02m z5u 1kv pin configuration of BFW10 B2X84 TDA3653 equivalent TRIAC TAG 9322 la4347 BS9000 D3007

RSQ035P03

Abstract: PT-2130FP BID C DOLLY L IST L OGO LIST SA F E TY & RELIA L TY PIN SYSTE M DIGITA L IC's MEMORIES, MOS CMOS .EC L , TT L MICR OP R OC E SSOR SPE CIA L FUN CTION IC's (DIGITAL l LINE AR) K ARR AYS LIN E A R IC's (PUR CH ) -MADE IC's IC's INDEX (COL ORE D PGS) ,C INC L : PR GMD, SC RN D, IC A PPL ICATION N OTE S HEAT SI NK S I NSU L ATOR S T R ANSISTORS POW ER SMAL L SIG N AL ARR AYS " ~ TRANSISTORS cE T " It ` T R N SIST d f?'_ SC R & SIN! i ;- S T RIAC & '1 1J
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RSQ035P03 PT-2130FP CCI SMART POSITIONER C330 SCA103T TEA 1732 NXP pj 39 ZENER 4K AT-DEC71 LN11CP23 P393-ND LN11WP24 P395-ND LN11WP34

Sony CXA1191M

Abstract: philips ecg master replacement guide Delay Line Programmable O ne-Shot Pulse Generator 4- in- 1 High-Speed Silicon Delay Line 4-B it Dual , Nonvolatile SRAM 64K Nonvolatile SRAM +5V Powered Dual RS-232 Transmitter/Receiver DATA BOOK Automatic , Evaluation Kit CyberKey Carrier Evaluation Kit Battery Manager Chip Smart Battery Dual Digital Potentiometer , EconoRAM Time Chip DS1609 Dual Port RAM DS1610 Partitioned NV Controller DS1611 Programmable System Monitor , NV SRAM 3V Partitionable 128K x 16 NV SRAM Dual Audio Taper Potentiometer Dual Audio Taper
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Sony CXA1191M philips ecg master replacement guide FZK101 FZK 101 Siemens CMC 707 am radio receiver philips ecg semiconductors master replacement guide Z8530 Z8531 Z86E04
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