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LTC2938HDE#TRPBF Linear Technology LTC2938 - Configurable 4-Supply Monitors with Watchdog Timer; Package: DFN; Pins: 12; Temperature Range: -40°C to 125°C visit Linear Technology - Now Part of Analog Devices Buy
LTC2939HMS#TRPBF Linear Technology LTC2939 - Configurable 6-Supply Monitors with Watchdog Timer; Package: MSOP; Pins: 16; Temperature Range: -40°C to 125°C visit Linear Technology - Now Part of Analog Devices Buy
LTC2938IDE#PBF Linear Technology LTC2938 - Configurable 4-Supply Monitors with Watchdog Timer; Package: DFN; Pins: 12; Temperature Range: -40°C to 85°C visit Linear Technology - Now Part of Analog Devices Buy
LTC2938HMS#TRPBF Linear Technology LTC2938 - Configurable 4-Supply Monitors with Watchdog Timer; Package: MSOP; Pins: 12; Temperature Range: -40°C to 125°C visit Linear Technology - Now Part of Analog Devices Buy
LTC2939IMS#TRPBF Linear Technology LTC2939 - Configurable 6-Supply Monitors with Watchdog Timer; Package: MSOP; Pins: 16; Temperature Range: -40°C to 85°C visit Linear Technology - Now Part of Analog Devices Buy
LTC2938CMS#PBF Linear Technology LTC2938 - Configurable 4-Supply Monitors with Watchdog Timer; Package: MSOP; Pins: 12; Temperature Range: 0°C to 70°C visit Linear Technology - Now Part of Analog Devices Buy

7421 pin configuration

Catalog Datasheet MFG & Type PDF Document Tags

7421 pin configuration

Abstract: TTL 7421 Material Copyrighted By Its Respective Manufacturer _ r CYPRESS Pin Configuration PRELIMINARY Dual , SRAMs â'¢ 112-pin Burndy Connector, Part Number CELP2X56SC3Z48 â'¢ Single 5V (±5%) power supply â , are latched. The modules are configured as a 112-pin card-edge memory module. It is constructed , D19 d21 Vcc D23 NC D25 d27 GND D 29 D31 NC (A2_! for 7421) NC (A3_, for 7421) Vcc A5 A7 Ag A11 An A15 NC (A17for 7421) NC GND dirtyo TAG, tag3 tag5 GND TAG7 NC ALE WEo Vcc GND WE4
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7421 pin configuration TTL 7421 tag a2 Intel 82420 TAG 93 0A20C CYM742 CYM7420 CYM7421 8K/32K 38-M-00065 G0171G2

7421 ttl AND gate

Abstract: TTL 7421 load (LSul) is 20/jA l,H and -0.4mA l|L. PIN CONFIGURATION '20, '21 LOGIC SYMBOL LOGIC SYMBOL (IEEE , Signetics I 7420, 7421, LS20, LS21, S20 Gates Dual Four-Input NAND ( 20) AND ('21) Gate Logic , 8mA 74LS20 10ns 0.8mA 74S20 3 ns 8mA 7421 12ns 8mA 74LS21 9ns 1.7mA ORDERING CODE FUNCTION TABLE , Manufacturer 853-0546 81501 Signetics Logic Products Gates Product Specification 7420, 7421, LS20, LS21 , Product Specification 7420, 7421, LS20, LS21, S20 DC ELECTRICAL CHARACTERISTICS (Over recommended
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7421 ttl AND gate PIN CONFIGURATION 7420 TTL 7420 logic gate 7421 AND 74LS20 PIN CONFIGURATION 7420 SIGNETICS N7420N N74LS20N N74S20N N7421N N74LS21N N74LS20D

ic 7421

Abstract: TTL 7421 Signetics I 7420, 7421, LS20, LS21, S20 Gates H Dual Four-Input NAND ('20) AND ('21) Gate Product Specification Logic Products TYPE 7420 74LS20 74S20 7421 74LS21 TYPICAL PROPAGATION DELAY , ) is 50juA l|H and -2.0m A I|l, and 74LS unit load (LSul) is 2 0 iiA l|H and -0.4m A l|L. PIN CONFIGURATION LOGIC SYMBOL '2 0 , '2 1 LOGIC SYMBOL (IEEE/IEC) '2 0 , '2 1 1 2 2 -5 4 -Ç s -e ^ & 6 , 5 853-0546 81501 Signetics Logic Products Product Specification Gates 7420, 7421
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ic 7421 IC 7420 pin configuration ic 7421 function ic 7421 7421 IC OF IC 7421 N74S20D N74LS21D WF07S70S WF07S80S
Abstract: Pin Configuration Dual Read-out SIMM Top View GND â¡2 d4 d6 VCC NC De D10 D 12 GND , SRAMs â'¢ 112-pin Burndy Connector, Part Num­ ber CELP2X56SC3Z48 â'¢ Single 5V (±5%) power supply The modules are configured as a 112-pin card-edge memory module. It is Logic Block Diagram , Ag A , a 13 a 15 NC (A 17 for 7421) NC GND DIRTYO TAG, ta g 3 ta g 5 GND ta g 7 NC ALE , 54 55 56 â¡ 3 3 â¡ 3 â¡ â¡ GND WE4 We2 we3 v cc NC (ÃE, for 7421) N C (U 5 -
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CYM7421PB 112-P

TTL 7421

Abstract: 7421 ttl AND gate , and 74LS unit load (LSul) is 20/jA l|H and -0.4mA l|L. 50jjA I|h and PIN CONFIGURATION LOGIC SYMBOL , Signetics I 7420, 7421, LS20, LS21, S20 Gates Dual Four-Input NAND ('20) AND ('21) Gate Logic , 10ns 8mA 74LS20 10ns 0.8mA 74S20 3ns 8mA 7421 12ns 8mA 74LS21 9ns 1.7mA ORDERING CODE FUNCTION , Specification Gates 7420, 7421, LS20, LS21, S20 ABSOLUTE MAXIMUM RATINGS (Over operating free-air temperature , Product Specification Gates 7420, 7421, LS20, LS21, S20 DC ELECTRICAL CHARACTERISTICS (Over recommended
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N74LS21 74LS21 PIN CONFIGURATION 74LS gates 7420 pin configuration TTL 74ls21 74LS20 fanout LS03500S LS03490S

d1266

Abstract: 7421 pin configuration CA 95134 D 408-943-2600 April 1994 PRELIMINARY Pin Configuration Dual Readout SIMM Top , NC (A2-1 for 7421) NC (A3-1 for 7421) VCC 82 26 VCC A4 83 27 A5 A6 84 , 32 A15 A16 89 33 NC (A17 for 7421) NC 90 34 NC GND 91 35 GND , VCC OE0 107 51 CS0 NC (OE1 for 7421) 108 52 NC (CS1 for 7421) PD0 109 , PRELIMINARY Pin Descriptions Name Description A[18:4] Host Address Bus A3-A0 Host Address Bit
Cypress Semiconductor
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CYM7420PB-20C CYM7421PB-20C d1266 7421 PM-09 PM09 Package YM7421

7421 pin configuration

Abstract: 7420 pin configuration PIN CONFIGURATION LOGIC SYMBOL LOGIC SYMBOL (IEEE/IEC) '2 0 , ' 21 1 2 S. 6 4 S & 9 10 12 , Signehcs I 7420, 7421, LS20, LS21, S20 Gates Dual Four-Input NAND ('20) AND ('21) Gate Product Specification Logic Products TYPE 7420 74LS20 74S20 7421 74LS21 TYPICAL PROPAGATION DELAY , S pecification Gates 7420, 7421, LS20, LS21, S20 ABSOLUTE MAXIMUM RATINGS PARAMETER VCC , Signetics Logic Products P roduct S pecification Gates 7420, 7421, LS20, LS21, S20 DC ELECTRICAL
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74LS20 function table 7420 F0758 7421 AND gate F07580S TA-25

sn 7421

Abstract: 2W2C power contacts and impedance for coaxial contact etc., as well as the accessory configuration. Pcb , S4 Solder version Male contacts 20 30 40 09 69 281 7421 09 69 281 7422 09 69 281 7423 09 69 281 5421 09 69 281 5422 09 69 281 5423 Female contacts 20 30 40 09 69 181 7421 09 , 30 40 09 69 282 7421 09 69 282 7422 09 69 282 7423 09 69 282 5421 09 69 282 5422 09 69 282 5423 Female contacts 20 30 40 09 69 182 7421 09 69 182 7422 09 69 182 7423 09 69 182
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21WA4 sn 7421 2W2C d-sub harting SN50N CONNECTOR D-SUB 09 69 202 0072 FEMALE MIXED 7 CONTACTS 17w2

d-sub harting

Abstract: sn 7421 contact etc., as well as the accessory configuration. Pcb connectors are delivered fully loaded thus , contacts 10 20 30 40 09 69 281 7420 09 69 281 7421 09 69 281 7422 09 69 281 7423 09 69 281 , 7420 09 69 181 7421 09 69 181 7422 09 69 181 7423 09 69 181 5420 09 69 181 5421 09 69 181 5422 09 69 181 5423 Male contacts 10 20 30 40 09 69 282 7420 09 69 282 7421 09 69 282 7422 , 10 20 30 40 09 69 182 7420 09 69 182 7421 09 69 182 7422 09 69 182 7423 09 69 182 5420
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M 2W2C D-SUB 9 PIN solder cup MALE CONNECTOR 21W1 27W2 36W4 MIL-C-24

23472

Abstract: . Peak IF current, 40mA RAY-6U LO Power Level 23 dBm Pin Configuration Port LO RF IF Gnd Ext , .03 .xxx ± .015 inch. Material and Finish: Header material: C.R.S. Pin material: #52 alloy. Finish , B14-045-01. Pin's meniscus (of header): 0.015" max. Special Tolerances: Pin diameter ±.005 inch. L M N , 5.59 5.61 5.58 5.60 5.71 5.85 5.69 5.30 5.27 81.53 79.86 76.21 73.93 76.26 74.21 82.38 80.63 77.59
Mini-Circuits
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23472 DC-100

KB3910

Abstract: CONNECTOR 16 pin mitsumi pioneer Diagram 200-PIN DDR SODIMM CLK GEN AMD CPU Sempron K8 4,5,6,7 IDT CV137 3 DDR 333/400 , PCMCIA SLOT Support TypeII 28 PWR SW TPS2224AP 28 PCMCIA I/F TI PCI 7421 2* Slot Cardbus 1* 1394 , 3010 Series ATI M24 (RADEON X700) for Aspire 5010 Series Embedded in ATI SB400 KB3910 TI PCI 7421 10 , ATI SB400 Embedded in ATI SB400 Embedded in ATI SB400 TI PCI 7421 Controller Processor Item CPU , 5010) uOG 754 pin 1.5V High speed: 1.2V Low speed: 1.2V => for RAM 2.5V =>for Hypertransport 1.2V
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CONNECTOR 16 pin mitsumi pioneer ATI SB400 UJDA750 ATI Radeon x700 sony DVD player with usb port circuit diagram amd athlon II x2 240 DDR333 2-200H RJ-45 RJ-11

566 pin diagram

Abstract: bq 735 EM78567/566/565 8-BIT MICRO CONTROLLER IV.Pin Configuration P75/INT5 P76/INT6 P77/INT7 , Fig1. Pin Assignment EM78567/566/565 8-BIT MICRO CONTROLLER XIII. DIE PAD DIAGRAM 1. EM78565/566/567 MASK DIE Package Pin Descriptions. NO. DIE Pad Package Pin EM78565 Name Name AM/BM , NC 18 13 20 -742.1 -1000 19 P8_5_ P85 NC NC 19 14 21 -612.1 , 1000 46 P6_7_ P67 1 32 42 39 46 75 1000 50 NC PIN 1,2,47,48 2
ELAN Microelectronics
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566 pin diagram bq 735 565 pin diagram micro controller bm p71 BM P60 EM78567AR EM78567BR EM78566AR EM78566BR P70/INT0 P71/INT1

marking 29

Abstract: DF782 DC OPERATING POWER at Pin 3 3 MTTF vs. Junction Temp. -45°C to 85°C 1,000,000 -65°C to 150°C 100,000 MTTF (Years) 10,000 Pin Connections RF IN 1 RF OUT 3 DC 3 , Q wt .062 grams 1.57 0.2 Typical Biasing Configuration R BIAS Rbias (Required) Vcc , 4.70 37.74 -20.04 0.10 -74.21 -12.40 0.24 -12.09 1.18 5000.00 -16.33
Mini-Circuits
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DF782 marking 29 GALI-29 2002/95/EC DC-7000

HA 12045

Abstract: IC 7487 chosen from adjacent locations on the wafer. These features combined with the pin configuration make this , 0.1 * 0.45 i z i = * 0.13 ± 0.0! ~ i 0 - 0.1 k PIN CONFIGURATION (Top View) 6 4 Q1 1 2 Q2 3 PIN CONNECTIONS 1. Collector (Q1) 2. Emitter (Q1) 3. Collector (Q2) 4. Base (Q2) 5. Emitter (Q2) 6. Base (Q1) C1 E1 C2 Note: Pin 3 is identified with a circle on the bottom of the , (automatic balanced bridge method), with emitter connected to guard pin of capacitances meter. 3-276
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HA 12045 IC 7487 TRANSISTOR 023 3010 k 3531 transistor pt 6964 pin IC 7479 UPA826TF NE685 IS21EI2 UPA826TF-T1

MC68HC

Abstract: TE 2161 motorola .28 MCU Block Diagram. 29 1.5 Pin , ). 35 1.5.3 External Reset Pin (R S T ). 36 1.5.4 External Interrupt Pin (IRQ). 36 1.5.5 External Filter Capacitor Pin (CGMXFC).36 1.5.6 Port A Input/Output (I/O , Redundant M o d e .70 5.4.5 MCU Configuration
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MC68HC TE 2161 motorola 08EB8

k 3531 transistor

Abstract: . These features combined with the pin configuration make this device ideal for balanced or mirrored , ) PIN CONFIGURATION PIN CO NNECTIO NS 1. Collector (Q1) 2. Em itter (Q1) 3. Collector (Q2) 4. Base (Q2) 5. Em itter (Q2) 6. Base (Q1) Note: Pin 3 is identified with a circle on the bottom of the , easured with capacitance m eter (autom atic balanced bridge method), with em itter connected to guard pin , -7.53 -11.10 -14.56 -17.91 -21.19 -23.71 -26.91 -29.05 -31.52 -35.51 -41.12 -44.56 -49.87 -59.91 -74.21
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UPA833TF

Abstract: ha 7741 designs. PIN CONFIGURATION (Top View) n n n uu u Note: UNITS (iA HA 100 GHz GHz PF dB dB dB dB HA HA 75 GHz pF dB dB 7 2.5 4.0 MIN PIN CONNECTIONS 1. Collector (Q1) 2. Emitter (Q1) 3. Collector (Q2) 4. Base (Q2) 5. Emitter (Q2) 6. Base (Q1) Pin 3 is identified with a circle on the bottom , 10 mA 6-PIN THIN-TYPE SMALL MINI MOLD PACKAGE 2 DIFFERENT BUILT-IN TRANSISTORS (Qi: NE688, Qi: NE685 , measured with capacitance meter (automatic balanced bridge method), with emitter connected to guard pin of
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UPA833TF ha 7741 13924 NE68830 NE68530 UPA833TF-T1 UPA836TF

transistor c 3531

Abstract: UPA826 chosen from adjacent locations on the wafer. These features combined with the pin configuration make this , 0.1 ^5 I V5 0 - 0.1 AU Note: Pin 1 is the lower left m ost pin as the package lettering is oriented and read left to right. PIN CO NNECTIO NS Collector (Q1) Em itter (Q1) Collector (Q2) Base (Q2 , connected to guard pin of capacitances meter. California Eastern Laboratories UPA826TF ABSOLUTE , -29.05 -31.52 -35.51 -41.12 -44.56 -49.87 -59.91 -74.21 UPA826TF TYPICAL SCATTERING PARAMETERS Q1 V
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UPA826 transistor c 3531 PA826TF-T1

transistor d 13009

Abstract: transistor j 13009 higher density designs. PIN CONFIGURATION (Top View) PIN CONNECTIONS 1. Collector (Q1) 2. Emitter (Q1) 3. Collector (Q2) 4. Base (Q2) 5. Emitter (Q2) 6. Base (Q1) Note: Pin 3 is identified , Q2:1S21EI2 = 8.5 dB TYP at f = 2 GHz, Vce = 3 V, Ic = 10 mA · · 6-PIN THIN-TYPE SMALL MINI MOLD , (automatic balanced bridge method), with emitter connected to guard pin of capacitances meter. 3-304 , -44.56 -49.87 -59.91 -74.21 UPA832TF TYPICAL SCATTERING PARAMETERS Q1 VCE = 3 V, Ic = 3 mA, Zo = 50
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transistor d 13009 transistor j 13009 IC 566 vco IC 8085 pin NE856 NE85630 UPA835TF UPA832TF-T1

LA4182

Abstract: 12-pin stereo amplifier ., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN 41596HA(II)/O207KI/2146KI/4025KI/O291KI,TS No.742-1/9 , circuit board only Cu-foiled area reduced board IC only Ambient temperature, Ta - °C Pin , configuration, where ch.1 operates as a noninverting amplifier and ch.2 as an inverting amplifier. The output of ch.1 is divided with R5, R6 and led to pin 1 and then input to ch.2. Since the attenuation degree , LA4182 so that the voltage at pin 6 can follow the supply voltage regulation. In the steady state, this
SANYO Electric
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EN742G 12-pin stereo amplifier DIP12F
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