NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Catalog Datasheet Results | Type | Document Tags |
| Abstract: 2.1 2.2 Device Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.1.1 Pinout: 80-Pin LQFP . . . . . . . . . . . . , : 100-Pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.1.3 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21 2.2.4 RESET Pin . . . ... | Original |
636 pages, |
HCS08 infrared transmitter receiver rs232 LCD segment display MCF51EM128 microcontroller opto isolator chn 731 soft start motor control diagram AD161 MCF51EM256 mac 87A6 display lcd 13pin 7411 pin configuration MCF51EM256 abstract |
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| Abstract: Ver. 1121 HPMX-7411 Preliminary Datasheet W-CDMA Modulator/IF VGA HPMX-7411 _ Features General Description Pin Configuration (looking down thru top of package) · 60 , reliability. The BCC24 BCC24 package and the pin layout minimizes printed circuit board space. The HPMX-7411 is , BCC24 BCC24 Agilent H X-7411 PM Functional Block Diagram LO YY W W VCOout -R I I IF /2 IF Q Q TxAgcAdj pwrDn The HPMX-7411 modulator/VGA offers a highly integrated ... | Original |
1 pages, |
wireless vga circuit BCC24 HPMX-7411 pin configuration of 7411 quadrature modulator wcdma modulator 7411 datasheet 7411 and 7411 pin configuration pin diagram of 7411 7411 7411 pin diagram PIN CONFIGURATION 7411 HPMX-7411 abstract |
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| Abstract: (LSul) is 20jaA lIH and -0.4mA l|L. PIN CONFIGURATION '10, '11 December 4, 1985 LOGIC SYMBOL "10 , Signetics I 7410, 7411, LS10, LS11, S10, S11 Gates Triple Three-Input NAND ('10), AND ('11 , (TOTAL) 7410 9ns 6mA 74LS10 74LS10 10ns 1.2mA 74S10 74S10 3ns 12mA 7411 10ns 11mA 74LS11 74LS11 9ns 2.6mA 74S11 74S11 5ns , 7410, 7411, LS10, LS11, S10, S11 ABSOLUTE MAXIMUM RATINGS (Over operating free-air temperatures unless , Specification Gates 7410, 7411, LS10, LS11, S10, S11 DC ELECTRICAL CHARACTERISTICS (Over recommended operating ... | OCR Scan |
4 pages, |
74LS gates AND 7411 74LS11 function table 7411 pin configuration 7411 TTL LS 7411 LS 7411 7410 SIGNETICS 74LS11 pin configuration TTL 74LS10 74LS10 function table 7410 pin configuration TTL 7410 AND propagation delay 74LS10 74S10 74LS10 abstract |
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| Abstract: and -0.4mA l|L. PIN CONFIGURATION LOGIC SYMBOL '10, '11 E Å' Å' «1 !Z Tili 1- ]3 \Z "AJ JutT SI , Signetics I 7410, 7411, LS10, LS11, S10, S11 Gates Triple Three-Input NAND (10), AND ('11) Gates , ) 7410 9ns 6mA 74LS10 74LS10 10ns 1.2mA 74S10 74S10 3ns 12mA 7411 10ns 11mA 74LS11 74LS11 9ns 2.6mA 74S11 74S11 5ns 19mA , Its Respective Manufacturer Signetics Logic Products Product Specification Gates 7410, 7411, LS10 , By Its Respective Manufacturer Signetics Logic Products Product Specification Gates 7410, 7411 ... | OCR Scan |
4 pages, |
LS10 N7410N N7411N N74LS10N N74LS11N 7411 pin configuration of 7411 74LS10 74LS gates N74S10N 74ls TTL family 74LS11 pin configuration TTL 7410 11 input 7411 pin configuration 74LS10 abstract |
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| Abstract: , 7411, 7415 Pin Name Pin No. Functions Input/Output Configuration LC7410 LC7410 LC7411 LC7411 LC7416 LC7416 1/2 V , JAPAN 6105KI 6105KI. TS JIJ No. 1852-1/9 11036613 LC7410 LC7410, 7411, 7415 Pin Anignment S ï ? 11 ì I 11 ï CL Ç. B ou , $ysterrtt5tfntrol Pin Description Pin Name Pfn " ^ â- V-:. -y' .Fil net ions Input/Output Configuration LC7410 LC7410 LG , detect output. ßI="H", SP="H". No. 1852-5/9 LC7410 LC7410, 7411, 7415 Pin Name Pin No. Functions Input , No. 1852 LC741 LC741 0,741 1,7415 HP SANYO C MOS LSI VTR (ß/VHS) SERVO CIRCUIT The LC7410 LC7410, 7411, 7415 ... | OCR Scan |
9 pages, |
3 phase pwm signal generator ic servo sanyo j88 CMOS 7411 DtP30 PIN CONFIGURATION 7411 HP 7415 transistor 2Fn IC 7415 LC7416 U741 LC741 LC7410 LA7110 LC741 abstract |
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| Abstract: 1052-4/9 LC7410 LC7410, 7411, 7415 Pin Name Pin No. Functions Input/Output Configuration LC7410 LC7410 LC7411 LC7411 , 6105KI 6105KI. TS JIJ No. 1852.1/9 11036613 LC7410 LC7410, 7411, 7415 Pin Anignment S s ¡Î 11 ì I 11 ? CL B S , ) 34 32 REC time mode detect output. IH="H", SP="H". No. 1852-5/9 LC7410 LC7410, 7411, 7415 Pin Name Pin No. Functions Input/Output Configuration LC7410 LC7410 LC7411 LC7411 LC7415 LC7415 B1I (B) LP , No. 1852 LC741 LC741 0,741 1,7415 HP SANYO C MOS LSI VTR (R/VHS) SERVO CIRCUIT The LC7410 LC7410, 7411 ... | OCR Scan |
9 pages, |
vhs motor drum DIP42S LA7110 LC7410 LC7411 LC7415 PIN CONFIGURATION 7411 7411 pin configuration PIN CONFIGURATION 7415 ua 7411 qcp_e u741 Op Amp HP 7415 CMOS 7411 LC741 LC7410 LC741 abstract |
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| Abstract: utilized here was supplied by Broadcom (Part No. TB5218 TB5218). The board provides eight 40 PIN Medium , SX-7210 SX-7210 SX-7411* SX-7411* SX-7411 SX-7411 MT-RJ DUPLEX NIC FAST ETHERNET CABLE , , via Netcoms SX-7411 (MT-RJ) and SX-7210 SX-7210 (MII) NIC cards with the evaluation board. The Netcom Systems Smart Bits allows Ethernet traffic testing of a communication link. The schematic configuration shown , Results/Comments SX-7210 SX-7210 BCM5218 BCM5218 KTB SX-7411 HFBR-5903 HFBR-5903 HFCT-5903E HFCT-5903E Full Duplex and Half Duplex ... | Original |
5 pages, |
transceiver Broadcom BCM 100BASE full duplex BLM11A601S broadcom bcm 100BASE-FX ic 5218 a L411 PIN CONFIGURATION 7411 SX-7210 SX-7411 BCM5218 bcm 5903 FX mode ethernet schematic HFBR-5903/HFCT 5903E HFBR-5903/HFCT abstract |
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| Abstract: 54/7411 54H/74H11 54H/74H11 54S/74S11 54S/74S11 54LS/74LS11 54LS/74LS11 ORDERING CODE (See Section 9 for further Package and Ordering Information.) PIN CONFIGURATION PACKAGES PIN CONF. COMMERCIAL RANGES VCC = 5V ± 5%; Ta - 0°C to *70°C MILITARY RANGES VCC = 5V ± 10°A; tA = -55°C to -125°c Plastic DIP Fig. A Fig. A N7411N N7411N • N74H11N N74H11N N74S11N N74S11N • N74LS11N N74LS11N Ceramic DIP Fig. A Fig. A N7411F N7411F • N74H11F N74H11F N74S11F N74S11F • N74LS11F N74LS11F S5411F S5411F • S54H11F S54H11F S54S11F S54S11F • S54LS11F S54LS11F Flatpak Fig. B Fig. A S5411W S5411W • S54H11W S54H11W S54S11W S54S11W • S54LS11W S54LS11W INPUT AND OUTPUT LOADING ... | OCR Scan |
1 pages, |
N74H11N N74S11N N74S11F N74LS11N N74LS11F N7411F N74H11F N7411N 74ls characteristics 74LS11 pin configuration PIN CONFIGURATION 7411 54H/74H11 54S/74S11 54LS/74LS11 54H/74H11 abstract |
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| Abstract: . 23 Figure 6. Pin Configuration for the Maxwell Capacitance and Partial Inductance Matrix , inductance matrix. Figure 6. Pin Configuration for the Maxwell Capacitance and Partial Inductance Matrix , line formed by this pin configuration is given by Z diff = 2 Chapter 7 Lloop - M 12 C + C12 , skew is measured for every pin configuration shown in Figure 6 on page 29. In each measurement the , return pin. Use EIA-364-103 EIA-364-103 standard or provided in Section 7.4.1.1, Test Procedure, on page 34. See ... | Original |
40 pages, |
40 pin zif socket amd athlon PIN LAYOUT amd athlon PIN LAYOUT voltage ground AMD Socket 754 datasheet Socket 754 EIA-364-20 amd athlon 64 3000 EIA-364-27 distance measurement using ir EIA-364-103 amd athlon 64 socket 754 socket S1 datasheet abstract |
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| Abstract: FUNCTIONAL DIAGRAM PIN CONFIGURATION SOIC (W) (top view) TSSOP (Y) (top view) RH0 VCC 1 , DP 19 7411 18 VCC SI DP 19 7411 18 NC A1 8 17 SCK NC 8 17 NC , No. MD-2114 MD-2114 Rev. J DP7411 DP7411 PIN DESCRIPTIONS SI: Serial Input Pin SOIC Pin TSSOP Name 1 19 VCC 2 20 RL0 SO: Serial Output SO is the serial data output pin. This pin is , Chip Select SCK: Serial Clock SCK is the serial clock pin. This pin is used to synchronize the ... | Original |
16 pages, |
MS-013 7411 pin diagram memory 2114 DP7251 pin diagram of 7411 DP704 DP7411 DP7411 abstract |
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| SECTION 7 CHI Module SECTION 7 CHI Module 7.1 Overview 7.1.1 Related Pins 7.2 Interface Requirements 7.2.1 Frame Structure and Serial Timing 7.2.2 Configurations 7.3 Implementation 7.3.1 Block Diagram 7.3.2 Transmitter 7.3.3 Receiver 7.3.4 Clock and Control Generation 7.3.5 DMA Address Generation 7.3.6 Related Interrupts 7.4 CHI TX Start Register 7.4.10 CHI TX Holding Register 7.4.11 CHI RX Holding Register www.datasheetarchive.com/files/toshiba/micon2/3905_12/doc/sec07.htm |
Toshiba | 14/07/1998 | 1.74 Kb | HTM | sec07.htm |
| SECTION 7 CHI Module SECTION 7 CHI Module 7.1 Overview 7.1.1 Related Pins 7.2 Interface Requirements 7.2.1 Frame Structure and Serial Timing 7.2.2 Configurations 7.3 Implementation 7.3.1 Block Diagram 7.3.2 Transmitter 7.3.3 Receiver 7.3.4 Clock and Control Generation 7.3.5 DMA Address Generation 7.3.6 Related Interrupts 7.4 CHI TX Start Register 7.4.10 CHI TX Holding Register 7.4.11 CHI RX Holding Register www.datasheetarchive.com/files/toshiba/micon2/3922/doc/sec07.htm |
Toshiba | 02/09/1998 | 1.7 Kb | HTM | sec07.htm |
| . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.3 System Block Diagram and Pin Assignment Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.4 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.2 System Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-53 5.7.4 MCU Module Pin Function During Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-53 5.7.5 Pin States During Reset www.datasheetarchive.com/download/39719868-313936ZC/mc68332um_zip.zip (m332TOC.pdf) |
KyteLabs | 11/06/2002 | 2809.58 Kb | ZIP | mc68332um_zip.zip |
| . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 1.6 MC68F375 MC68F375 MC68F375 MC68F375 Pin Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 Section 2 SIGNAL DESCRIPTIONS 2.1 Pin Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.2 System Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.2.1 SCIM Module Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-57 4.7.7 Pin State During Reset www.datasheetarchive.com/download/34551609-313958ZC/mc68f375rm_zip.zip (f375TOC.pdf) |
KyteLabs | 11/06/2002 | 4595.78 Kb | ZIP | mc68f375rm_zip.zip |
| (USART) with dedicated Programmable Baudrate Generator • 40 Multifunctional Input / Output Pins, 8 Input Pins, 2 Ports with 10mA Sinking Current (total max. 100mA) • Extended Power Saving Modes with Wake 7411-X-X-7600 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 / T2 CC 1/ IN T4 P5 . 0/ T 2C C0 /IN T3 V D D V S S C508 P-SDIP-64 P-SDIP-64 P-SDIP-64 P-SDIP-64 C508 Block Diagram C508 Pin Configuration OTP / ROM 32 K x 8 10-bit ADC 16-bit Capture/Compare Unit T2 (4 Channel PWM) Oscillator Watchdog www.datasheetarchive.com/files/infineon/mc_data/dave/products/smart.dip!/smart/manuals/p508.pdf |
Infineon | 01/02/2000 | 2321.8 Kb | DIP | smart.dip |
| (USART) with dedicated Programmable Baudrate Generator • 40 Multifunctional Input / Output Pins, 8 Input Pins, 2 Ports with 10mA Sinking Current (total max. 100mA) • Extended Power Saving Modes with Wake 7411-X-X-7600 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 / T2 CC 1/ IN T4 P5 . 0/ T 2C C0 /IN T3 V D D V S S C508 P-SDIP-64 P-SDIP-64 P-SDIP-64 P-SDIP-64 C508 Block Diagram C508 Pin Configuration OTP / ROM 32 K x 8 10-bit ADC 16-bit Capture/Compare Unit T2 (4 Channel PWM) Oscillator Watchdog www.datasheetarchive.com/files/infineon/mc_data/dave/products/c508.dip!/c508/documents/p508.pdf |
Infineon | 01/02/2000 | 5502.86 Kb | DIP | c508.dip |
| The TwinCAN Module=44 Parallel Ports=48 Protected Bits=50 Pin Definitions and Port Functions=51 XC164 XC164 XC164 XC164 Logic Symbol (100-pin package)=51 Pin Configuration for XC164 XC164 XC164 XC164 in 100-Pin Package=52 Pin Definitions for XC164 XC164 XC164 XC164 in 100-Pin Package=53 Memory Organization=62 Organization in Memory=62 Address _MSGFGCRH3=411 CAN_MSGFGCRH4=411 CAN_MSGFGCRH5=411 CAN_MSGFGCRH6=411 CAN_MSGFGCRH7=411 CAN_MSGFGCRH8 =411 CAN_MSGFGCRL3=411 CAN_MSGFGCRL4=411 CAN_MSGFGCRL5=411 CAN_MSGFGCRL6=411 CAN_MSGFGCRL7=411 CAN www.datasheetarchive.com/files/infineon/mc_data/dave/products/xc164cs_v27.dip!/xc164cs/data/xc164cs.def |
Infineon | 25/11/2003 | 10263.06 Kb | DIP | xc164cs_v27.dip |
| The TwinCAN Module=44 Parallel Ports=48 Protected Bits=50 Pin Definitions and Port Functions=51 XC164 XC164 XC164 XC164 Logic Symbol (100-pin package)=51 Pin Configuration for XC164 XC164 XC164 XC164 in 100-Pin Package=52 Pin Definitions for XC164 XC164 XC164 XC164 in 100-Pin Package=53 Memory Organization=62 Organization in Memory=62 Address _MSGFGCRH3=411 CAN_MSGFGCRH4=411 CAN_MSGFGCRH5=411 CAN_MSGFGCRH6=411 CAN_MSGFGCRH7=411 CAN_MSGFGCRH8 =411 CAN_MSGFGCRL3=411 CAN_MSGFGCRL4=411 CAN_MSGFGCRL5=411 CAN_MSGFGCRL6=411 CAN_MSGFGCRL7=411 CAN www.datasheetarchive.com/download/98335158-166806ZC/xc164cs_v2.8.zip (xc164cs.def) |
Infineon | 17/01/2005 | 10664.18 Kb | ZIP | xc164cs_v2.8.zip |
| Document Format Size Document Number Date Update Pages Portable Document Format 836K 7411 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 Emulator Configuration Configuration Figure 1 shows a general configuration for the ST7MDT1/2-EMU2 emulator kit. The ST7-HDS2 up the emulator configuration so that you can begin your debugging session. Once assembled and station performs a real-time emulation of Figure 1: ST7MDT1/2-EMU2 General Configuration Parallel Port www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/7411.htm |
STMicroelectronics | 22/02/2001 | 84.04 Kb | HTM | 7411.htm |
| F | |* | [Pin] signal_name model_name R_pin L_pin C_pin | 1 NC NC VCC POWER 0.033 4.231n 0.630p | [Diff_pin] inv_pin vdiff tdelay_typ tdelay_min tdelay_max | | The 'A/Y' pin is Diff_pin and the 'B/Z' pin is the inv_pin capacitance value Rref = 50 |Note: 50 Ohm load; single ended configuration Vref = 2.5V NA 2.00 -1.101E-02 101E-02 101E-02 101E-02 NA NA 1.95 -7.411E-03 NA www.datasheetarchive.com/files/texas-instruments/simulation-models/sllc131.ibs |
Texas Instruments | 07/08/2011 | 17.8 Kb | IBS | sllc131.ibs |