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Part Manufacturer Description Datasheet BUY
SN7407N-00 Texas Instruments TTL/H/L SERIES, HEX 1-INPUT NON-INVERT GATE, PDIP14 visit Texas Instruments
SN7407N Texas Instruments Hex Buffers/Drivers With Open-Collector High-Voltage Outputs 14-PDIP 0 to 70 visit Texas Instruments Buy
SN7407N-10 Texas Instruments TTL/H/L SERIES, HEX 1-INPUT NON-INVERT GATE, PDIP14 visit Texas Instruments
SN7407D Texas Instruments Hex Buffers/Drivers With Open-Collector High-Voltage Outputs 14-SOIC 0 to 70 visit Texas Instruments Buy
SN7407NSR Texas Instruments Hex Buffers/Drivers With Open-Collector High-Voltage Outputs 14-SO 0 to 70 visit Texas Instruments Buy
TPL7407LPW Texas Instruments 40V, 7-Channel NMOS Array, Low Side Driver 16-TSSOP -40 to 125 visit Texas Instruments

7407 connection diagram

Catalog Datasheet MFG & Type PDF Document Tags

7407 connection diagram

Abstract: transistor Comparison Tables high beta and high fT ( 1 5 GHz) was se- TL H 7407 ­ 5 FIGURE 5 LM161 Schematic Diagram 3 TL H 7407 ­ 6 FIGURE 6 LM160 Schematic Diagram tended for interfacing to TTL logic direct , 74 Series TTL Loads ns max 25 AN-87 C1995 National Semiconductor Corporation TL H 7407 , capacitance Figure 2 shows typical delay variation with temperature TL H 7407 ­ 3 FIGURE 3 Offset , input voltage is relatively TL H 7407 ­ 4 FIGURE 4 LM161 Common Mode Range g 15V op amp supplies
National Semiconductor
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LM260 LM360 LM261 LM361 NE529 7407 connection diagram transistor Comparison Tables 7407 ttl 7407 7407 application note LM361 application note A760C

7417 TTL

Abstract: 7407 connection diagram is 30 mA for the 9N07/5407 and 40 mA for the 9N07/7407 and 9N17/7417. LOGIC AND CONNECTION DIAGRAM DIP (TOP VIEW) FLATPAK (TOP VIEW) Vcc SCHEMATIC DIAGRAM (EACH BUFFER/DRIVER) RM^Rijliïl WWW ri n ri , FAIRCHILD TTL/SSI . 9N07/5407, 7407 â'¢ 9N17/5417, 7417 HEX BUFFER/DRIVER (WITH OPEN-COLLECTOR HIGH-VOLTAGE OUTPUT) DESCRIPTION â'" These TTL/SSI hex buffer/driver feature high voltage open collector output , Range -55 25 125 0 25 70 °C Output HIGH Level Voltage, Vqh 9N07/5407, 7407 30 30 Volts 9N17/5417
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7417 TTL 7404 fan out 7417 9n07 TTL 7417 5407 9N17/ 9N07/7407 9N07XM/5407XM 9N17XM/5417XM 9N07XC/7407XC 9N17XC/7417XC

TTL LS 7407

Abstract: CI 7407 /22 mW High Speed Schottky 54S/74S 3 ns/19 mW Logic/Connection Diagram'2' S Tu a SI , FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D7 54/7430, 54H/74H30 54S/74S30, 54LS/74LS30 Vcc NC NC NC D8 54S/74S133, 54LS/74LS133 Vcc Ifl ffl 13 13 El R El El D9 54S/74S134 Vcc E , D15 54/7407, 54/7417 Vcc ra la ra la ei m rai m SJ a iii lai iii id id ili a iii GND Vcc , Buffer (OC/15 V) â'" â'" 54/7417 â'" â'" D15 3I,6A,9A 10 Hex Buffer (OC/30 V) â'" â'" 54/7407 â'" â
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TTL LS 7407 CI 7407 CI 7402 TTL LS 7402 ls 7408 CI 74LS02 54S/74S02 54LS/74LS02 54LS/74LS28 74LS33 54LS/74LS27 54LS/74LS

texas instruments 7407

Abstract: . NC â' No internal connection ORDERING INFORMATION TA ORDERABLE PART NUMBER PACKAGEâ , SN7417DR TOP-SIDE MARKING 0°C to 70°C 7407 7417 SN7407N SN7417N SN7417N SN7407 , dissipation is 145 mW, and average propagation delay time is 14 ns. logic diagram, each buffer/driver , -1-260C-UNLIM 0 to 70 7407 SN7407DE4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 7407 SN7407DG4 ACTIVE SOIC D 14 50 Green
Texas Instruments
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texas instruments 7407 SN5407 SN5417 SN7417 SDLS032G ISO/TS16949
Abstract: . NC â' No internal connection ORDERING INFORMATION TA ORDERABLE PART NUMBER PACKAGEâ , SN7417DR TOP-SIDE MARKING 0°C to 70°C 7407 7417 SN7407N SN7417N SN7417N SN7407 , dissipation is 145 mW, and average propagation delay time is 14 ns. logic diagram, each buffer/driver , -1-260C-UNLIM 0 to 70 7407 SN7407DE4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 7407 SN7407DG4 ACTIVE SOIC D 14 50 Green Texas Instruments
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74HC07

Abstract: Size of 74HC07 (multistandard) - SCART type connection to TV - Video signal pattern generator or video source (VCR, Sat Receiver, etc.) - +5V power supply The connection diagram (see Figure 1) shows how the evaluation , given in Figure 2. Figure 1 : STV5730 Evaluation Connection Diagram VIDEO IN +5V 0V Dgnd , STV5730 - OSD CHIP QUICK EVALUATION GUIDE 5730-09.EPS Figure 2 : STV5730 Evaluation Board Diagram , interface connection errors are encountered, (or the evaluation board supplies have not been set), the
STMicroelectronics
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74HC07 Size of 74HC07 STV5730-OSD 2N2222 Cbord functions of a colored tv
Abstract: 18 17 16 15 14 9 10 11 12 13 6Y NC 5A NC 5Y NC - No internal connection ORDERING INFORMATION , SN7417N SN7407 SN7417 SNJ5407J SNJ5417J SNJ5407W SNJ5407FK 7407 TOP-SIDE MARKING Package drawings , . Typical power dissipation is 145 mW, and average propagation delay time is 14 ns. logic diagram, each , SN5417J 7407 7407 7407 7407 7407 7407 SN7407N SN7407N SN7407 SN7407 Addendum-Page 1 PACKAGE , and regulatory requirements in connection with such use. TI has specifically designated certain Texas Instruments
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7407PC

Abstract: 7407 connection diagram 07 54/7407 ¿9/0&3 9 HEX BUFFER/DRIVER (With Open-Collector High-Voltage Output) ORDERING CODE: See Section 9 PKGS PIN OUT COMMERCIAL GRADE MILITARY GRADE PKG TYPE Vcc = +5.0 V ±5%, Ta = 0°C to +70° C Vcc = +5.0 V ±10%, Ta = -55° C to +125° C Plastic DIP (P) A 7407PC 9A Ceramic DIP (D) A 7407DC 5407 DM 6A Flatpak (F) A 7407FC 5407 FM 3I CONNECTION DIAGRAM PINOUT A [± Å' Å' [I EE d gnd[T 1 f 3 t f 1«! Vcc 33 m a bg I] 11 INPUT LOADING/FAN-OUT: See Section 3
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5407FM 5407DM IS417

74HC07

Abstract: STV5730 (multistandard) - SCART type connection to TV - Video signal pattern generator or video source (VCR, Sat Receiver, etc.) - +5V power supply The connection diagram (see Figure 1) shows how the evaluation , given in Figure 2. Figure 1 : STV5730 Evaluation Connection Diagram 0V Dgnd VIDEO IN +5V , STV5730 - OSD CHIP QUICK EVALUATION GUIDE 5730-09.EPS Figure 2 : STV5730 Evaluation Board Diagram , interface connection errors are encountered, (or the evaluation board supplies have not been set), the
STMicroelectronics
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schematic diagram scart Receiver connector PHILIPS colour television schematic 14 VERTICAL COLOUR TV SCHEMATIC DIAGRAM horizontal COLOUR TV SCHEMATIC DIAGRAM specifications tv pattern generator

mcb circuit diagram

Abstract: mcb internal circuit diagram . Outputs are open collector (7407) with pull up resistors. The opto common supplies optical isolator power for limits, home and remote Party Line select (on J1). · 5 Volt operation MCB BLOCK DIAGRAM , six contact signal arrangement allows direct connection of a hand held terminal. Pin Out 45 1 2 , collector (7407) circuits. Signals are easily interfaced to power drivers. Pin Signal 1 +5v 3
Advanced Micro Systems
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MCB-24 MCB-50 mcb circuit diagram mcb internal circuit diagram opto isolator rs422 SMC-C24 3 phase DC motor ESC circuit type b mcb RS-232 RS-422 RS-232/422 RS-485

PC MOTHERBOARD CIRCUIT diagram

Abstract: ALL MOTHERBOARD CIRCUIT DIAGRAM SAMPLE. Information in this document is provided in connection with an Intel specification. No license , - the NLX Motherboard and the NLX Riser. Connection between the two is made via the NLX edge , R LINE OUT L LINE OUT FP_SPKR_EN U8 MUTE 5Vsb VCC CODEC U3 Q2 7407 7407 U4 , . Microphone Signal Control Implementation Figure 3 shows a block diagram of one possible solution to control
Intel
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PC MOTHERBOARD CIRCUIT diagram ALL MOTHERBOARD CIRCUIT DIAGRAM free circuit diagram of motherboard ATX MOTHERBOARD CIRCUIT diagram intel motherboard circuit diagram

74LS08 Quad 2-Input AND Gates

Abstract: TTL 74s32 FAIRCHILD DIGITAL TTL SSI FUNCTIONS (Cont'd) Logic/Connection Diagram'2' D10 D11 D12 D13 Std. TTL 54/74 1 0 ns/10 mW 9000 Series 8 ns/10 mW High Speed 54H/74H 6 ns/22 mW High Speed Schottky 54S/74S 3 ns/19 mW E £ NOR Gates 1 2 3 4 5 6 7 8 ~c o o c S U. L o w Power Schottky 54LS/74LS 5 ns/2 mW 5 'a t 0) o > IS o (0 C L Quad 2-Input Quad 2-Input Triple 3-Input Dual 4-Input w , /74LS21 54/7417 54/7407 54/7408 54/7409 54 H 74 HOB - - 54S/74S08 54S/74S09 9S41 D15 D15 D16
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74LS08 Quad 2-Input AND Gates TTL 74s32 TTL 7408 54LS or 2 input 74Ls32 74LS11 and 74LS32 54LS/74LS260 54LS/74LS08 54LS/74LS09 54LS/74LS11 54LS/74LS15 54LS/74LS21

IC 7486

Abstract: CI 74LS08 FAIRCHILD DIGITAL TTL SSI FUNCTIONS (Cont'd) E £ Function'1' 9000 Series 8 ns/10 mW Low Power Schottky 54LS/74LS 5 ns/2 mW Std. TTL 54/74 10 ns/10 mW High Speed 54H/74H 6 ns/22 mW High Speed Schottky 54S/74S 3 ns/19 mW Logic/Connection Diagram'2' Packages'3' NOR Gates 1 Quad 2-lnput 54LS/74LS02 54/7402 â'" 54S/74S02 D10 3I,6A,9A 2 Quad 2-lnput 9015 â'" â'" â'" â'" D11 4L,6B 3 Triple , '" D15 3I,6A,9A 10 Hex Buffer (OC/30 V) - â'" 54/7407 â'" â'" D15 3I,6A,9A 11 Quad 2-lnput â'" 54LS
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IC 7486 CI 74LS08 IC TTL 7432 7408 TTL 7408 ic diagram IC TTL 7402 54H/74H08 54H/74H11 54S/74S11 54S/74S15 LS/74LS21 54H/74H21

CI 7408

Abstract: 74LS series logic gates FAIRCHILD DIGITAL TTL SSI FUNCTIONS (Cont'd) E a o o e 3 LL 9000 Series 8 ns/10 mW Low Power Schottky 54LS/74LS 5 ns/2 mW Std. TTL 54/74 10 ns/10 mW High Speed 54H/74H 6 ns/22 mW High Speed Schottky 54S/74S 3 ns/19 mW Logic/Connection Diagram'2' S Tu a SI , ) â'" â'" 54/7417 â'" â'" D15 3I,6A,9A 10 Hex Buffer (OC/30 V) â'" â'" 54/7407 â'" â'" D15 3I,6A,9A
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CI 7408 74LS series logic gates 7408 and TTL 7486 7408 CI 74LS86 54LS/74LS32 54S/74S32 54LS/74LS86 54S/74 54S/74S86 54LS/74LS136

CI 74LS08

Abstract: 7432 TTL fairchild ns/22 mW High Speed Schottky 54S/74S 3 ns/19 mW Logic/Connection Diagram'2' S Tu a SI , FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D16 547408, 54H/74H08, 54S/74S08, 54LS/74LS08 54/7409, 54S/74S09, 54LS/74LS09 Vcc ) EI EI na fri EI iyi FI ¿J a lil liJ Li] Iii liJ 111 llJ OND D19 54/7421, 54H/74H21 54LS/74LS21 Vcc NC s J â'" D17 9S41 Vcc RRPIIiRRRR , Buffer (OC/15 V) â'" â'" 54/7417 â'" â'" D15 3I,6A,9A 10 Hex Buffer (OC/30 V) â'" â'" 54/7407 â'" â
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7432 TTL fairchild TTL 7421 74LS21 ttl 7432 TTL 7409 TTL 74ls32 54S/74S135 74LS266 54LS/74LS386

logic diagram of 7432

Abstract: CI 7408 . Description No. of Bits â o » .P-c Power Dissipation mW (Typ) Logic/Connection Diagram Package(s) 1 , / Connection Diagram Package(s) OR Gates 8 Dual 3/3 OR 95110 2.5 145 E81 6B 9 Dual 3/3 OR 10110/10510 , /Connection Diagram'2' S Tu a SI , FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D16 547408, 54H/74H08, 54S/74S08, 54LS/74LS08 , 10 Hex Buffer (OC/30 V) â'" â'" 54/7407 â'" â'" D15 3I,6A,9A 11 Quad 2-lnput â'" 54LS/74LS08 54/7408
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logic diagram of 7432 7408 s.i 7486 nor FL 9014 DIAGRAM OF 74LS08 7408, 7486, 7432 93S43 93S62

CI 7408

Abstract: CI 74LS08 Speed 54H/74H 6 ns/22 mW High Speed Schottky 54S/74S 3 ns/19 mW Logic/Connection Diagram'2' S Tu a SI , FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D65 54/7413, 54LS/74LS13 Vcc NC HKiEiraiaram 3 LlI lil Id li] li] LàJ Ui NC QND D66 54/74125, 54LS/74LS125 Vcc E D O E D O ism a ra a in ~?i r?i Lj ui lii y ili iii u E D O E D O QND D67 54/74126, 54LS/74LS126 Vcc E D O E DO , 9 Hex Buffer (OC/15 V) â'" â'" 54/7417 â'" â'" D15 3I,6A,9A 10 Hex Buffer (OC/30 V) â'" â'" 54/7407
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TTL 74ls21 CI 7413 74LS125 TTL 74126 74LS126 7409 54LS/74LS365 54LS/74LS366 54LS/74LS367 54LS/74LS368

Z427

Abstract: FL 9014 FAIRCHILD DIGITAL TTL SSI FUNCTIONS (Cont'd) c o 5S agic/Conne Diagram Std. TTL 54/74 1 ns/10 mW lig h Speed Schottky 54S/74S ns/19 mW ig h Speed 54H/74H ns/22 mW 9000 Series ns/10 mW ~'c o u c 3 U. D w Power Schottky ILS/74LS ns/2 mW 5 < 0 o (0 £L < D at E a > NOR Gates 1 2 3 4 5 6 7 8 C , -Input Triple 3-Input (OC) Dual 4-Input - - - - 54/7417 54/7407 54/7408 54/7409 - - - - , D23 4L,6B,9B D94 3I,6A,9A Notes on follow ing pages 9-4 FAIRCHILD LOGIC/CONNECTION DIAGRAMS
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Z427 74LS32 74ls86 74LS02 74LS08 74LS11 54/Z427

7411 pin diagram

Abstract: TTL 7408 mW Logic/Connection Diagram'2' S Tu a SI , FAIRCHILD LOGIC/CONNECTION DIAGRAMS D93 54LS/74LS379 1 A 4 5 12 13 | E D0 Di D2 D3 CP Oo Qi Q2 03 lltlfltl 3 2 6 7 11 10 14 15 Vcc = Pin 16 GND = Pin 8 DIGITAL -TTL D94 9386, 74LS266, 54LS/74LS386 Vcc raianangnnnn 111 III Iii Lil liJ 111 III GND D95 54LS/74LS398 4 5 7 6 , ,9A 10 Hex Buffer (OC/30 V) â'" â'" 54/7407 â'" â'" D15 3I,6A,9A 11 Quad 2-lnput â'" 54LS/74LS08 54
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7411 pin diagram DS 7409 74LS574 TTL 7408 DIAGRAMS 74LS386 74LSS02 54LS/74LS399 54LS/74LS574 54LS/74LSS02 54LS/74LS568 54LS/74LS569

PWm matlab source code

Abstract: Park transformation . ADMC200-EVAL BOARD HARDWARE The system block diagram is shown in Figure 1, while the full circuit diagram is , 1. ADMC200-EVAL Board System Block Diagram can be taken from the ADMC200/ADMC201 reference output or through the analog connection block. The CONVST pin can be connected to the PWMSYNC pin or to , Table I. ADMC200-EVAL Ground Jumpers ADMC200 Connection Connected to SGND Ground Plane JUMPER , VII. Table IV. ADMC200-EVAL PWM Connector Connector Name ADMC200 Connection 0 VL Connected to
Analog Devices
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ADDS-2101-EZ-LAB 74LS04 PWm matlab source code Park transformation 74LS04 Hex Inverter Gate function table clarke transformation pin configuration and description OF IC 74ls04 AN-407 ADMC21 ADMC200/ ADMC201 ADSP-2105
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