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MC100EP446MNG ON Semiconductor Serial to Parallel Converter, 3.3 V / 5 V, 8-Bit, CMOS / ECL / TTL Data Input, QFN32, 5x5, 0.5P, 3.1x3.1EP, 74-TUBE visit Digikey
CD4504BKMSR Intersil Corporation HEX TTL/CMOS TO CMOS TRANSLATOR, INVERTED OUTPUT, CDFP16 visit Intersil
HIP2101EIB Intersil Corporation 100V/2A Peak High-Frequency Half Bridge Driver with TTL Logic Inputs; DFN12, QFN16, SOIC8; Temp Range: -40° to 85°C visit Intersil
ISL54222IRUZ-T Intersil Corporation TTL/H/L SERIES, 2 LINE TO 1 LINE MULTIPLEXER, TRUE OUTPUT, PQCC10, 1.80 X 1.40 MM, ROHS COMPLIANT, PLASTIC, MO-255,TQFN-10 visit Intersil
ISL6700IBZ-T Intersil Corporation 80V/1.25A Peak High-Frequency Half Bridge Driver with TTL Logic Inputs; QFN12, SOIC8; Temp Range: -40° to 85°C visit Intersil
HIP2101EIBZT Intersil Corporation 100V/2A Peak High-Frequency Half Bridge Driver with TTL Logic Inputs; DFN12, QFN16, SOIC8; Temp Range: -40° to 85°C visit Intersil

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Part : TT2274T-TL-E Supplier : ON Semiconductor Manufacturer : Rochester Electronics Stock : 2,100 Best Price : - Price Each : -
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74 ttl

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: 54/74 TTL. All address lines and data-in are latched on chip to simplify system design. Data-out is , ) with a fan-out of two Series 54/74 TTL loads. Data-out is the same polarity as data-in. The output is , CL = 100 pF, Load = 2 Series 74 TTL gates *CAC 70 ns taIR) Access time from RAS tRLCL = MAX, CL = 100 pF Load = 2 Series 74 TTL gates tRAC 120 ns ta(G) Access time after G low CL = 100 pF, Load =- 2 Series 74 TTL gates â'¢ 30 ns *dis(CH) Output disable time after CAS high CL = 100 pF, Load = 2 Series -
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TMS4416 SMJ4416 16KX4 20D6 RP1001 384-WORD
Abstract: Chip-Enable Inputs for OR-Tie Capability Fan-out to 1 Series 74 TTL Load 3-State Outputs and Output Enable , 4039. The common input/outputs are fully compatible with Series 74 TTL. The device requires a single 5 , Series 54/74 TTL with no external pull-up resistors. chip enable 1 and chip enable 2 (CE 1 and CE2) To , are forced to the high-impedance state. The common I/O terminals can be driven directly by Series 74 TTL and the buffers can drive Series 74 TTL circuits without external resistors. functional block Texas Instruments
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18-PIN intel 2111 TMS4042-2 4042 PIN DIAGRAM TMS4042 Tms 1000 4042 BE 256-WORD
Abstract: , including clocks, are compatible with Series 54/74 TTL. All address lines and data-in are latched on chip to , pull-up resistor required) with a fan-out of two Series 54/74 TTL loads. Data-out is the same polarity as , TMS4416-12 MIN MAX UNIT ta(C) Access time from CAS C|_ = 100 pF, Load = 2 Series 74 TTL gates *CAC 70 ns ta(R) Access time from RAS tRLCL = MAX, C|_ = 100 pF Load = 2 Series 74 TTL gates tRAC 120 ns ta(G) Access time after G low C(_ = 100 pF, Load = 2 Series 74 TTL gates 30 ns tdisfCH) Output disable time -
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TMS4416-20 TM4416FE8-20 HJR 1-2C pin diagram for all 74 series ttl gates TMS4416-15 ao 4416 texas 74 series TTL logic gates texas 74 series logic gates TM4416FE8 TMS4416-1 TM4416FE8-1 0430S
Abstract: realized. All inputs and outputs, including clocks, are compatible with Series 74 TTL. All address lines , required) with a fan CD out of two Series 74 TTL loads for each output. Data out is the same polarity as , MAX MIN MAX "tatCl Access time from CAS C(_ = 100 pF. Load = 2 Series 74 TTL gates tCAC 75 90 ns ta(R) Access time from RAS lRLCL = MAX. Load = 2 Series 74 TTL gates tRAC 120 150 ns Output disable time «dislCH) aftar CAS high CL = 100 pF, Load = 2 Series 74 TTL gates *OFF 0 40 0 40 ns PARAMETER -
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TM4164EC4-12 TM4164EC4-20 TM4164EC4-15 65536X4 TM4164EC4 TM4164EC4-16 TM4256EC4
Abstract: with Series 74 TTL. All address lines and data in are latched on chip to simplify system design. Data , compatibility (no pull-up resistor required) with a fan out of two Series 74 TTL loads for each output. Data out , MAX MIN MAX *a(C) Access time from CAS CL = 100 pF, Load = 2 Series 74 TTL gates tCAC 75 90 ns 1a(R) Access time from RAS «RLCL = MAX, Load = 2 Series 74 TTL gates «RAC 120 150 ns Output disable time tdis(CH) _ after CAS high Cl = 100 pF, Load = 2 Series 74 TTL gates »OFF 0 40 0 40 ns Texas 5104 -
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TM4164 4164 dynamic ram 4164 ram DYNAMIC RAM 65536 TEXAS RAM 4164 tlu 011 TM4164FL8 TM4164FM8 TMS4164FPL
Abstract: allow a minimum 200 mV noise margin when driven by a series 74 TTL device. The TTL compatible open-drain buffer is guaranteed to drive 1 series 74 TTL gate. The low capacitance of the address and control inputs , a fan-out of one Series 74 TTL gate. A low logic level results from conduction in the open-drain , *: CL - SOpF. flL ' 2.2 ktt, Load = 1 Serie* 74 TTL «ate. - 50 pF. RL - 2 ? k(ï, Load - 1 Serie» 74 , Full TTL Compatibility on All Inputs (No Pull-up Resistors Needed) Râ"¢ â'¢ Registers for -
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7512-24 40501 TMS 4050 NL TMS4050 4096-BIT 1975-REV1SED 300-M
Abstract: input noise immunity is 200 mV. The TTL-compatible buffer is guaranteed to drive two Series 74 TTL gates , compatibility with a fan-out of two Series 74 TTL gates. The output is in the high-impedance (floating) state , V ICC Supply current from VCC 2 Series 74 TTL loads 100 Supply current from VOO , , Load = 1 Series 74 TTL gate. +Test conditions: CL = 50 pF, Load = 1 Series 74 TTL gate. write cycle , 200 ns tTest conditions: CL ~ 50 pF, trICE) ~ 20 ns, Load ~ 1 Series 74 TTL gate. +Test Texas Instruments
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TMS4060 RD4000 TMS 250 4060 PIN DIAGRAM 40601 40602 400-M
Abstract: Capability in Common I/O Data Bus Systems Fan-out to 1 Series 74 TTL Load · Power Dissipation . 175 , fully compatible with Series 74 TTL The device requires a single 5-volt power supply_ The TMS 4043 , one of 256 4-bit words. The address inputs can be driven directly from standard Series 54/74 TTL with , , CE must be low and high. The common I/O terminals can be driven directly by Series 74 TTL and the buffers can drive Series 74 TTL circuits without external resistors. Riw a functional block Texas Instruments
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TMS4043 intel 2112 c mos 4043 40431 40432 16-PIN I/01-1/04
Abstract: DI2 Fan-out to 1 Series 74 TTL Load DI4 DI1 D01 Output Interface Two Chip-Enable Inputs , compatible with Series 74 TTL, including the single 5-volt power supply. The TMS 4039 series is manufactured , address inputs can be driven directly from standard Series 54/74 TTL with no external pull·up resistors , O°C to 70°C, 1 Series 74 TTL load, 40 Output disable time from output enable (see Note 3) 0 Texas Instruments
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22-PIN intel 2101 TMS4039 40392 TMS403 TMS4039JL
Abstract: The clock and all inputs can be driven from Senes 74 TTL circuits and all outputs can drive TTL , TYpt MAX UNIT Propagation detoy time, low-to-high-level 1 Series 74 TTL Load + 10 pF OR 10 Mil + 10 pF (MOS Load) (tee Not« 2Ï 1 Series 74 TTL Load + 10 pF (aee Note 2) 100 160 nt Propagation delay time , , high-to-low-level output 100 160 60 50 m m ."aâ'".- TTL load ,. « a â'" - « « - .e«â'"â'" * « » â -
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74TTL 64-BIT 10MI2
Abstract: with Series 54/74 TTL. All address lines and data-in are latch ed on chip to simplify system design , resistor required) with a fan-out of two Series 5 4 /74 TTL loads. Data-out is the same polarity as data-in , Series 74 TTL gates ta(R) Access time from RAS tRLCL = MAX, CL = 100 pF Load = 2 Series 74 TTL gates t a , C(_ = 100 pF, Load = 2 Series 74 TTL gates CL = 100 pF, Load = 2 Series 74 TTL gates CL = 100 pF, Load = 2 Series 74 TTL gates tOFF 0 0 30 30 30 ns ns ns *CAC 70 ns ALT. SYMBOL T M S4416-12 MIN M AX -
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4416-15 24-PIN 4416FE8-12 S4416 J4416
Abstract: Fan-out 1 Series 74 TTL Load OR-Tie Capability · CE A3 10 8 VCC II GND , requirements. In addition all inputs and outputs are fully compatible with Series 74 TTL, including the single , nanoseconds for the TMS 4035. The address inputs can be driven from standard Series 54/74 TTL with no external , write cycle. This input can be driven from Series 54/74 TTL with no external pull·up resistors , Output load All timing requirements 2.2V 0.65 V 20 ns 1 Series 74 TTL load, CL = 100 pF . 50 Texas Instruments
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TMS4034 intel 2102 Static RAM TMS4035 2102 Static RAM power must office 650 TMS4035JL 1024-WORD 1-81T 1974-REVISED
Abstract: Series 74 TTL circuits. A 200-mV noise margin is guaranteed in this configuration, which eliminates the , 74 TTL circuit as long as a pull-up resistor to VCC is employed in order to provide a high-level , 74 TTL gate. A low logic level results from conduction in the open·drain output buffer while a high , Series 74 TTL gate CL = 50 pF, MIN 0 VOL = 0.4 V 0.4 VSS 5 V rnA VI = -0.6 to , ~ 50 pF, RL ~ 2.2 kn to 5.5 V, Load ~ 1 Series 74 TTL gate. kn to 5.5 V, Load ~ 1 Series 74 TTL Texas Instruments
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4051 16 PIN DIAGRAM 40511 4051 pin diagram 4051 timing diagram TMS4051 4096-81T
Abstract: Static Charge Protection o Output Interface 3-State Fan-Out 1 Series 74 TTL Load 1/00 II I , 74 TTL, including the single 5-volt power supply. The TMS 4036 series is manufactured using TI , Series 54/74 TTL with no external pull-up resistors required. 75 PRELIMINARY DATA SHEET , buffers are in the high-impedance state. CE may be driven from Series 74 TTL. For a more complete , This input is also compatible with Series 74 TTL circuits. II input/output buffer (1/00-1/07 Texas Instruments
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20-PIN TMS4036-2 40361 40362 tms4036 4036 64-WORD I/00-1/07
Abstract: conserve power. All inputs and outputs, including clocks, are compatible with Series 74 TTL. All address , direct TTL compatibility (no pull-up resistor required) with a fan out of two Series 74 TTL loads. Data , ) Access time from CAS CL = 100 pF, Load = 2 Series 74 TTL gates -
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TMS4164 TMS4116 TMS4500A THCT4501 TMS4164-15 tms4500 TMS4164A TMS4164-20 536-BIT MIL-STD-883B
Abstract: 74 TTL. All address lines and data in are latched on chip to simplify system design. Data out is , Series 74 TTL loads. Data out is the same polarity as data in. The output is in the high-impedance , 100 pF, Load = 2 Sériés 74 TTL gâtes lCAC 60 75 ns tatR) Access time from RAS tRLCL = MAX, Load = 2 Sériés 74 TTL gâtes «RAC 120 150 ns Output disable time tdis{CH) _ after CAS high C|_ = 100 pF, Load = 2 Sériés 74 TTL gâtes tOFF 0 30 0 30 ns O «< 0) 3 o u > o OL ® (A parameter -
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16S1151 oasi TM4256FC1 TM4257FC1 TM425 1024K TMS425
Abstract: (including program data inputs) can be driven by series 74 TTL circuits without the use of external pull-up resistors, and each output can drive one Series 74 TTL circuit without external resistors. The data outputs , '¢ Pin-Compatible With I2758 â'¢ All Inputs/Outputs Fully TTL Compatible â'¢ Static Operation (No Clocks, No , Standard TTL Loads â'¢ No Pull-Up Resistors Required TMS2758 24-PIN CERAMIC DUAL-IN-LINE PACKAGE (TOP , , but all programming signals are TTL levels and require a single 50-millisecond pulse. For programming -
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TMS2758JL 2516 eprom eprom 2516 2516 eprom texas 2758 eprom 2758 192-BIT 758-J
Abstract: be driven directly from Series 74 TTL circuits without the use of external components. The push-pull output buffer will drive a TTL or MOS load without external components. Two input terminals are provided , ° C -0.8 mA l , CONDITIONS MIN MAX UNIT 'PLH Propagation delay time output from clock low-to-high-level 1 Series 74 TTL Load , °C NOTE 2: TTL compatibility of all inputs is ensured by incorporation of internal pull-up resistors -
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TMS 1024 1024-BIT
Abstract: realized. All inputs and outputs, including clocks, are compatible with Series 74 TTL. All address lines , compatibility (no pull-up resistor required) with a fan CO out of two Series 74 TTL loads for each output. Data , -12 TM4164EOE-15 UNIT MIN MAX MIN MAX ta(C) Access time from CAS CL = 100 pF, Load = 2 Series 74 TTL gates tCAC 75 90 ns ta(R) Access time from RAS tRLCL = MAX, Load = 2 Series 74 TTL gates fRAC 120 150 ns Output disable time «dis(CH) _ after CAS high C|_ = 100 pF, Load = 2 Series 74 TTL gates 'OFF 0 40 0 -
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TM4164EQ5-15 TM4164EQ5-20 TM41 TM4164EQ5 TM4164EQ5-1 64EQ6-20 TM4161EQ5-12
Abstract: MODULES All inputs and outputs, including clocks, are compatible with Series 74 TTL. All address lines , provide direct TTL compatibility (no pull-up resistor required) with a fan jg- out of two Series 74 TTL , 100 pF, Load = 2 Series 74 TTL gates «CAC 60 75 ns la(RI Access time from RAS tRLCL = MAX, Load = 2 Seríes 74 TTL gates tRAC 120 150 ns Output disable time «dis(CH) ^ after CAS high C[_ = 100 pF, Load = 2 Series 74 TTL gates 'OFF 0 35 0 35 ns PARAMETER TEST CONDITIONS ALT. SYMBOL TM425_EQ5-20 MIN MAX -
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TM4256EQ5 TM4257EQ5 EQ5-12 EQ5-15 EG5-12
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