NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Catalog Datasheet Results | Type | Document Tags |
| Abstract: Increasing the data rate from 200Mbps to 700Mbps has a very minimal affect on DCD (e.g. 110ps to 120ps). Jitter is increased by ~50ps at 700Mbps. Even with these increases, not only the DCD is low, but also the , data rates are at 700Mbps. The jitter noise has a substantial affect on DCD when the number of , 4.0 Figure 2b. Single Input and Output at 700Mbps Duty Cycle Distortion in Broadcast Mode In , input is broadcast to 80 outputs at 200Mbps and 700Mbps, a minimal jitter and DCD is observed (see ... | Original |
5 pages, |
TDS794D OCX1601 OCX160 I-CUBE Crosspoint Switches OCX160 abstract |
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| Abstract: alignment and up to 700Mbps in static alignment mode. The objective of this technical note is to provide a , 350MHz DDR (700Mbps) · Transmit interface with speeds up to 500MHz DDR (1000Mbps) · 256 logical ports , provide system- and chip-level debug · Full-rate SPI4.2 interface running at 350MHz DDR (700Mbps , receive interface with speeds up to 350MHz DDR (700Mbps) · Transmit interface with speeds up to 450MHz ... | Original |
9 pages, |
POWR1208 pDS4102-DL2A ORSPI4-2FE1036C IXF18101 TN1116 OC-192 TN1116 abstract |
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| Abstract: up to 700Mbps in static alignment mode. This document discusses the SPI4.2 interoperability tests , up to 350MHz DDR (700Mbps) · Transmit interface w/speeds up to 500MHz DDR (1000Mbps) · 256 logical , modes provide system- and chip-level debug · Full-rate SPI4.2 interface running at 350MHz DDR (700Mbps ... | Original |
9 pages, |
AX4000 PM3388 TN1121 OC-192 PM-3388 PM3388 abstract |
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| Abstract: Mbps IPSec (3DES/SHA-1) · LZS and MPPC compression engines run at up to 700Mbps and increase the ... | Original |
2 pages, |
ARC-4 hifn 7751 7851 PB HIFN datasheet abstract |
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| Abstract: , LVPECL, BLVDS, RSDS · 700Mbps+ I/O buffers · 400Mbps DDR memory interfaces Eight I/O Banks Per , /O Cells (PIC) include sysIO buffers that support over 20 interfaces at up to 700Mbps and 400Mbps ... | Original |
4 pages, |
ECP10 EC20 EC15 DDR400 ec20 encoder datasheet abstract |
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| Abstract: , HSTL, Differential HSTL, Differential SSTL, LVPECL, BLVDS, RSDS · 700Mbps+ I/O buffers · 333Mbps , ) include sysIO buffers that support over 20 interfaces at up to 700Mbps and 333Mbps DDR memory ... | Original |
4 pages, |
LFXP10 lattice real time clock 144 pin DDR333 1000X datasheet abstract |
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| Abstract: /MAX9218 /MAX9218 shown in Figure 5) that deliver up to 700Mbps using only a single twisted-pair copper wire. That ... | Original |
5 pages, |
simple diagram for electronic clock MAX9217 MAX9214 MAX9213 LVDS advantages disadvantages APP3570 datasheet abstract |
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| Abstract: engines run at up to 700Mbps and increase the effective data rate throughput of the 7854 when enabled ... | Original |
2 pages, |
vhdl code for uart communication sdk 03 SAS controller chip AES RSA chips 7854-PB4 7814-PB4 6500 CPU NORTEL OC-12 AES chips datasheet abstract |
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| Abstract: 700Mbps and increase the effective throughput · HSP architecture enables FIPS 140-1 level 3 compliance ... | Original |
2 pages, |
8165-PB5 8065PB5 new 7901 datasheet abstract |
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| Abstract: 1517-Pin SMPTE-424 VID (mV) VICM (D C)(V) VO CM (V) (3) Max Min Typ Ma x Dm ax 700Mbps 1.55 - - 0.05 Dm ax 700Mbps VC M = 1.25V - 0.3 2.625 100 VC M = 1.25V - 2.5 , Max Min Typ Ma x Min Typ Max 0.6 Dm ax 700Mbps 1.6 (5) - - - - - - ... | Original |
40 pages, |
SSTL-18 SSTL-15 datasheet abstract |
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| Abstract: Application Report SCAA074 SCAA074 Â September 2004 Dual Purposes: Data Buffer, the Other Face of the CDCP1803 CDCP1803 H. McClendon, C. Sterzik, K. Mustafa . High Performance Analog ABSTRACT The CDCP1803 CDCP1803 is a clock driver by design, but can be used as a data buffer. The CDCP1803 CDCP1803 performance as a data buffer is demonstrated both in terms of the bit error rate (BER) and eye pattern diagrams. The CDCP1803 CDCP1803 is tested over several signaling rates and d ... | Original |
7 pages, |
TDS694C CDC1803 CDCM1802 CDCP1803 eye pattern 9349 transistor voltage diagram PRBS anritsu HP6624A system DC power supply HP6624A SCAA074 SCAA074 abstract |
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| Abstract: SPI-4.2 Interoperability with PMC-Sierra XENON Family in Stratix GX Devices May 2003, ver. 1.0 Introduction Application Note 228 The system packet interface level 4Âphase 2 (SPI-4.2) specification, defined by the Optical Internetworking Forum (OIF), is fast becoming the most common interface for packet transfers between physical (PHY) and link layer devices in multi-gigabit applications, including: asynchronous transfer mode (ATM), packet over SONET/SDH (STS-192/STM-64 STS-192/STM-64), 10 Giga ... | Original |
22 pages, |
hmzd connector PM3388 PM3392 PM5390 PM5392 SFP altera SFP LVDS altera smartbits STM-64 SFP Xenon 175 STS-192/STM-64 OC-192 STS-192/STM-64 abstract |
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| Abstract: ERBT Compact Sonet OC-12 OC-12 PIN-Transimpedance Amplifier Optical Receiver Modules Features â- InGaAs PIN Photodiode and GaAs Transimpedance Amplifier â- Meets Sonet sensitivity and overload requirements â- Automatic gain control â- Integrated 4-pin package â- Connector receptacle and fiber pigtailed versions â- Higher bandwidth than ERM535A ERM535A series ERM535 ERM535 Applications â- Sonet receivers Add/Drop Multiplexers Digital Crossconnects Test Equipment â- Fiber Channel receivers â- Digital video â- ... | OCR Scan |
3 pages, |
ir photodiode amplifier ERM535RST ERM535RSC-FM ERM535RFC2 ERM535FJ-S EPITAXX amplifier schematic ERM535 12-pin transimpedance amplifier OC-12 OC-12 abstract |
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| Abstract: TM A CONEXANT BUSINESS 2,047 Multichannel Synchronous Communications ControllerÂMUSYCCTM CX28560 CX28560 Highly Integrated, Fully Featured Multichannel HDLC Controller with a 32-bit POS-PHY Interface The CX28560 CX28560 is an advanced multichannel synchronous communications controller (MUSYCCTM) that formats and > K E Y F E AT U R E S > 700 Mbps full-duplex throughput > JTAG boundary scan test support > 32-bit full-duplex standard POS-PHY Level 3 bus > 32 independent serial interfaces ... | Original |
2 pages, |
hdlc CX29503 CX28560 CX28560 abstract |
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| Abstract: SPI-4.2 Interoperability with the Intel IXF1110 IXF1110 in Stratix GX Devices May 2003, ver. 1.0 Introduction Application Note 227 The system packet interface level 4Âphase 2 (SPI-4.2) specification, defined by the Optical Internetworking Forum (OIF), is fast becoming the most common interface for packet transfers between physical (PHY) and link layer devices in multi-gigabit applications, including: asynchronous transfer mode (ATM), packet over SONET/SDH (STS-192/STM-64 STS-192/STM-64), 10 Gigabit Et ... | Original |
18 pages, |
IXF1110 IXF1010 IXD1110 Gigabit Logic Gigabit Ethernet MAC SPI IXP2800 STS-192/STM-64 IXF1110 abstract |
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| Abstract: BCM5825 BCM5825 ® HIGH-PERFORMANCE SECURITY PROCESSOR SUMMARY OF BENEFITS FEATURES · High-performance VPN and SSL security processor · High-performance security coprocessor enables both secure web and high-performance VPN applications · Web servers · Layer 4+ switches · Web appliances with integrated SSL · Access devices · Firewalls · VPN enabled routers · VPN appliances (IPsec/ SSL) · 1-Gbps system throughput - AES-CBC, AES-CTR - DES-CBC, 3DES-CBC - HMAC-SHA-1, HMAC-MD5 - Sin ... | Original |
2 pages, |
BCM5823 BCM5821 BCM5825 BCM5825 abstract |
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| Abstract: Lattice ORSPI4 / Intel® IXF18101 IXF18101 Physical Layer Device Interoperability March 2004 Technical Note TN1059 TN1059 Introduction The System Packet Interface Level 4, Phase 2 (SPI4.2), was defined by the Optical Internetworking Forum (OIF) as an interface for packet and cell transfers between a Physical Layer (PHY) device and a link layer device for applications requiring up to 10 Gbps aggregate bandwidth. Example applications include ATM, Packet over SONET/SDH, and 10 Gigabit Ethernet. Typicall ... | Original |
12 pages, |
IXF1810X IXF18101 TN1059 IXF18101 abstract |
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| Abstract | Saved from | Date Saved | File Size | Type | Download |
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| _phase_ucf.align,v $ ################################################################################ #$RCSfile: snk_dyn_700mbps_ucf.per,v $ #$Revision: 1.1.2.1 $ #$Date: 2002/11/01 13 StatClk"; #TIMESPEC "TS_SnkStatClk" = PERIOD "SnkStatClk" 200 MHz HIGH 50 %; #EOF: $RCSfile: snk_dyn_700mbps .clk,v $ ################################################################################ #$RCSfile: src_700mbps_ucf.per,v $ #$Revision: 1.1.2.1 $ #$Date: 2002/11/01 13 _SrcStatClk" = PERIOD "SrcStatClk" 200 MHz HIGH 50 %; #EOF: $RCSfile: src_700mbps www.datasheetarchive.com/download/91401815-995983ZC/xapp525.zip (bridge_top.ucf) |
Xilinx | 31/03/2004 | 399.48 Kb | ZIP | xapp525.zip |